Rohm BU9882FV-W Edid memory (for display) Datasheet

Memory for Plug & Play
EDID Memory
(For display)
BR24C21,BR24C21F,BR24C21FJ,BR24C21FV,
BU9882-W,BU9882F-W,BU9882FV-W
No.09002EAT02
BR24C21,BR24C21F,BR24C21FJ,BR24C21FV
●Description
TM
TM
BR24C21F,BR24C21FJ,BR24C21FV are serial EEPROMs that support DDC1 /DDC2 interfaces
for Plug and Play displays.
●Features
TM
TM
1) Compatible with both DDC1 /DDC2
2) Operating voltage range: 2.5V to 5.5V
3) Page write function: 8bytes
4) Low power consumption
Active (at 5V)
: 1.5mA (typ)
Stand-by (at 5V) : 0.1µA (typ)
5) Address auto increment function during Read operation
6) Data security
Write enable feature (VCLK)
Write protection at low Vcc
7) Various packages available: DIP-T8(BR24C21) / SOP8(BR24C21F) / SOP-J8(BR24C21FJ) / SSOP-B8(BR24C21FV)
8) Initial data=FFh
9) Data retention: 10years
10) Rewriting possible up to 100,000 times
●Absolute maximum ratings (Ta=25℃)
Parameter
Supply Voltage
Power Dissipation
Storage Temperature
Operating Temperature
Terminal Voltage
Symbol
VCC
Pd
800
Rating
-0.3～+6.5
(DIP-T8)
450
(SOP8)
450
350
Tstg
Topr
-
Unit
V
*1
*2
(SOP-J8)
(SSOP-B8)
-65～+125
-40～+85
-0.3～VCC+0.3
*3
mW
*4
℃
℃
V
* Reduce by 8.0 mW/C over 25C (*1), 4.5mW/℃ (*2,3), and 3.5mW/℃ (*4)
●Memory cell characteristics
Parameter
Supply Voltage
Input Voltage
Symbol
VCC
VIN
Rating
2.5～5.5
0～VCC
Unit
V
V
●Recommended operating conditions
Write/Erase Cycle
Min.
100,000
Limits
Typ.
-
Max.
-
Cycle
Data Retention
10
-
-
Year
Parameter
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© 2009 ROHM Co., Ltd. All rights reserved.
1/22
Unit
2009.04 - Rev.A
BR24C21,BR24C21F,BR24C21FJ,BR24C21FV,
BU9882-W,BU9882F-W,BU9882FV-W
Technical Note
●Electrical characteristics - DC (Unless otherwise specified, Ta=-40℃～+85℃､VCC=2.5V～5.5V)
Limits
Parameter
Symbol
Unit
Condition
Min.
Typ.
Max.
“H” Input Voltage 1
VIH1
0.7VCC
V
SCL, SDA
“L” Input Voltage 1
VIL1
0.3VCC
V
SCL, SDA
“H” Input Voltage 2
VIH2
2.0
V
VCLK
“L” Input Voltage 2
VIL2
0.8
V
VCLK, VCC≧4.0V
“L” Input Voltage 3
VIL3
0.2VCC
V
VCLK, VCC＜4.0V
“L” Output Voltage
VOL
0.4
V
SDA, IOL=3.0mA
Input Leakage Current
ILI
-1
1
µA
SCL, VCLK, VIN=0V～VCC
Output Leakage Current
ILO
-1
1
µA
SDA, VOUT=0V～VCC
Operating Current
ICC
3.0
mA
VCC=5.5V, fSCL=400kHz
Standby Current
ISB
10
100
µA
VCC=5.5V, SDA=SCL=VCC,VCLK=GND *1
Note: This IC is not designed to be radiation-resistant
*1 Transmit-Only Mode - After power on, the BR24C21/F/FJ/FV is in Standby mode and does not provide the clock to the VCLK pin.
After the clock is provided to VCLK, the device is switched from Standby to Transmit-Only Mode, and the operating current flows.
Bi-directional Mode - The BR24C21/F/FJ/FV is in Standby mode after each command is performed.
●Electrical characteristics - AC (Unless otherwise specified, Ta=-40℃～+85℃,VCC=2.5V～5.5V)
Standard-mode
Fast-mode
VCC=2.5V～5.5V
VCC=2.5V～5.5V
Parameter
Symbol
Unit
Min.
Typ.
Max.
Min.
Typ.
Max.
fSCL
-
-
400
-
-
100
kHz
Data Clock High Period
Data Clock Low Period
SDA and SCL Rise Time
SDA and SCL Fall Time
Start Condition Hold Time
Start Condition Setup Time
Input Data Hold Time
tHIGH
tLOW
tR
tF
tHD:STA
tSU:STA
tHD:DAT
0.6
1.3
0.6
0.6
0
-
0.3
0.3
-
4.0
4.7
4.0
4.7
0
-
1.0
0.3
-
µs
µs
µs
µs
µs
µs
ns
Input Data Setup Time
tSU:DAT
100
-
-
250
-
-
ns
Output Data Delay Time(SCL)
Stop Condition Setup Time
Bus Free Time
Write Cycle Time
Noise Spike Width (SDA and SCL)
tPD
tSU:STO
tBUF
tWR
tI
0.6
1.3
-
-
0.9
10
0.1
4.0
4.7
-
-
3.5
10
0.1
µs
µs
µs
ms
µs
-
1.0
0.5
0.1
4.0
4.7
0
4.0
0
-
-
2.0
1.0
0.1
µs
µs
µs
µs
µs
µs
µs
µs
Clock Frequency
AC OPERATING CHARACTERISTICS (Transmit-Only Mode)
Output Data Delay Time(VCLK)
VCLK High Period
VCLK Low Period
VCLK Setup Time
VCLK Hold Time
Mode Transition Time
Transmit-Only Powerup Time
Noise Spike Width (VCLK)
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© 2009 ROHM Co., Ltd. All rights reserved.
tVPD
tVHIGH
tVLOW
tVSU
tVHD
tVHZ
tVPU
tVI
0.6
1.3
0
0.6
0
-
2/22
2009.04 - Rev.A
BR24C21,BR24C21F,BR24C21FJ,BR24C21FV,
BU9882-W,BU9882F-W,BU9882FV-W
Technical Note
●Block diagram
N.C. 1
1 Kbit
EEPROM
ARRAY
ADDRESS
DECODER
SLAVE・WORD
7bit
DATA
ADDRESS REGISTER
START
N.C. 3
VCC
7
VCLK
6
SCL
5
SDA
8bit
7bit
N.C. 2
8
REGISTER
STOP
CONTROL LOGIC
ACK
GND 4
HIGH VOLTAGE
VCC LEVEL DETECT
Fig.1 Block Diagram
●Pin layout diagram
VCC
VCLK
SCL
SDA
(入力)
BR24C21
入出
BR24C21F
BR24C21FJ
BR24C21FV
N.C.
N.C.
N.C.
GND
Fig.2 Pin Layout
Pin Name
VCC
GND
N.C.
SCL
I/O
IN
SDA
IN/OUT
VCLK
IN
Functions
Power Supply
Ground (0V)
No Connection
Serial Clock Input for Bi-directional Mode
Slave and Word Address,
*1
Serial Data Input, Serial Data Output
Clock Input (Transmit-Only Mode)
Write Enable (Bi-directional Mode)
*1 An open drain output requires a pull-up resistor.
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© 2009 ROHM Co., Ltd. All rights reserved.
3/22
2009.04 - Rev.A
BR24C21,BR24C21F,BR24C21FJ,BR24C21FV,
BU9882-W,BU9882F-W,BU9882FV-W
Technical Note
●Synchronous data timing
tR
t HIGH
tF
SCL
SCL
t SU:DAT
t HD:STA
t LOW
t HD:DAT
SDA
SDA
(IN)
D0
ACK
tWR
WRITE DATA(n)
t PD
t BUF
STOP CONDITION
SDA
(OUT)
START CONDITION
Fig.4 Write Cycle Timing
START BIT
STOP BIT
SCL
SCL
tSU:STA
tHD:STA
tSU:STO
SDA
SDA
STOP BIT
START BIT
VCLK
Fig.3 Synchronous Data Timing
・SDA data is latched into the chip at the rising edge of the SCL clock.
WRITE COMMAND
tVSU
t VHD
Fig.5 Write Enable Timing
・Output data toggles at the falling edge of the SCL clock.
●Transmit-only mode
・After power is on, the BR24C21/F/FJ/FV is in Transmit-Only Mode. In this mode data can be output by providing the clock
to the VCLK pin.
・When the power is on, the SCL pin needs to be set to VCC(High level).
・SDA is at high-impedance during input of the first 9 clocks. At the 10th rising clock edge of VCLK data is output. After
power on, the output data is as follows:
00h address data → 01h address data → 02h address data → …
The address is incremented by one, after every 9 clocks of VCLK. All addresses are output in this mode.
When the counter reaches the last address, the next output data is 00h address data. (See Fig. 6)
・In this mode, the NULL bit (High data) is output between the address data and the next address data. (See Fig. 7)
・The read operation is in Transmit-Only Mode and can be started after the power is stabilized.
tVHIGH tVLOW
Vcc
VCLK
SCL
tVPD
9
1
10
SDA
VCLK
D1
ADDRESS n
DATA
ｔVPU
D7
SDA
D6
D5
D4
D0
D7
NULL BIT
DATA=1
D6
ADDRESS n+1
DATA
D3
00h ADDRESS DATA
Fig.7 Null Bit
Fig.6 Transmit Only Mode
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© 2009 ROHM Co., Ltd. All rights reserved.
4/22
2009.04 - Rev.A
BR24C21,BR24C21F,BR24C21FJ,BR24C21FV,
BU9882-W,BU9882F-W,BU9882FV-W
Technical Note
●Bi-directional mode
○Bi-directional Mode and Recovery Function
・The BR24C21/F/FJ/FV can be switched from Transmit-Only Mode to Bi-directional Mode by providing a valid High to Low
transition at the SCL pin, while the state of SDA is at high-impedance.
・After a valid high to low transition on the SCL pin, the BR24C21/F/FJ/FV begins to count the VCLK clock. If the VCLK
counter reaches 128 clocks without the command for Bi-directional Mode, the device reverts to Transmit-Only Mode
(Recovery function). The VCLK counter is reset by providing a valid high to low transition at the SCL pin. After reversal
to Transmit-Only Mode the device begins to output data (00h address data) with the 129th rising clock edge of VCLK.
・If the BR24C21/F/FJ/FV is switched from Transmit-Only Mode and receives the command for Bi-directional
Mode and responds with an Acknowledge, it is impossible to revert to Transmit-Only Mode. (Power down is the only
way to revert to Transmit-Only Mode.) Unless the input device code is “1010”, the device does not respond with an
Acknowledge. If the VCLK counter reaches 128 clocks afterwards, it is possible to revert to Transmit-Only Mode for
Recovery function. If the Master generates a STOP condition during the Slave address, before an Acknowledge is input,
it is possible to revert to Transmit-Only Mode.
・When the device is switched from Transmit-Only Mode to Bi-direction Mode, the period of tVHZ needs to be held.
Bi-d
irectional
Bi-directional
T r aTransition
n s i t i o n Mode
M o dwith
e wpossibility
i t h p o s stoi b i l i t y
t o rreturn
e t u n to
e Transmit-Only
t o T r a n s mMode
it-Only Mode
Tra nsm it -o nl y
ＭＯＤＥ Transmit-only
１
２
３
４
T r a nTransmit-Only
smit-Only
ＭＯＤＥ
１２７ １２８ １２９
１
ＶＣＬＫ
BBi-directional
i-directional
TTransition
ransitio
n M
o dpossibility
e w i t h p to
ossibility
Mode
with
treturn
o r e tto
u nTransmit-Only
e t o T r a nMode
smit-Only Mode
Transmit-oOnly
Tra nsm it -o nl y
２
B i - d i rBi-directional
ectional
p a r m parmanently
anently
ｎ＜１２８
ｎ
ＶＣＬＫ
ＳＣＬ
ＳＣＬ
A D DADDRESS
R E S S 00h
00h
ｔＶＨＺ
ｔＶＨＺ
Ｄ７ Ｄ６ Ｄ５ Ｄ４
Ｓ
ＳＤＡ
１
０
１
０
＊
＊
＊ Ｒ/Ｗ ＡＣＫ
ＳＤＡ
Fig.8 Recovery Mode
Fig.9 Mode Change
*Don’t care
○Bi-directional Mode
START Condition
・All commands are proceeded by the START condition, which is a High to Low transition of SDA when SCL is High.
・The BR24C21/F/FJ/FV continuously monitors the SDA and SCL lines for the START condition and will not respond to
any commands until this condition has been met.
(See Fig. 3 Synchronous Data Timing)
STOP Condition
・All commands must be terminated by a STOP condition, which is a Low to High transition of SDA when SCL is High.
・The STOP condition causes the internal write cycle to write data into the memory array after a write sequence.
・The STOP condition is also used to place the device into standby power mode after read sequences.
・A STOP condition can only be issued after the transmitting device has released the bus.
(See Fig.3 Synchronous Data Timing)
Device Addressing
・Following the START condition, the Master outputs the device address of the Slave to be accessed. The most
significant four bits of Slave address are the “device type indentifier,” For the BR24C21/F/FJ/FV this is fixed as
“1010.”
・The next three bits of the slave address are inconsequential.
・The last bit of the stream determines the operation to be performed. When set to “1”, a READ operation is selected.
When set to “0”, a WRITE operation is initiated.
R/W set to "0" ・ ・ ・ ・ ・ ・ ・ ・ WRITE (This bit is also set to "0" for random read operation)
R/W set to "1" ・ ・ ・ ・ ・ ・ ・ ・ READ
1010
＊
＊
＊
_
R/W
＊：Don’t care
○Write Protect Function
・Write Enable (VCLK)
When using the BR24C21/F/FJ/FV in Bi-directional Mode, the VCLK pin can be used as a write enable pin. Setting
VCLK High allows normal write operations, while setting VCLK low prevents writing to any location in the array.
(See Fig.5 Write Enable Timing)
Changing VCLK from High to Low during the self-timed program operation will not halt programming of the device.
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© 2009 ROHM Co., Ltd. All rights reserved.
5/22
2009.04 - Rev.A
BR24C21,BR24C21F,BR24C21FJ,BR24C21FV,
BU9882-W,BU9882F-W,BU9882FV-W
Technical Note
●Bidirectional mode command
○Byte Write
When the Master generates a STOP condition, the BR24C21/F/FJ/FV begins the internal write cycle to the nonvolatile array.
S
T
A
R
T
SDA
LINE
W
R
I
T
E
SLAVE
ADDRESS
1 0 1 0 * *
WORD
ADDRESS
WA
0
WA
* 6
*
R A
/ C
W K
S
T
O
P
DATA
D7
D0
A
C
K
A
C
K
VCLK
*:Don’t care
Fig.10 Byte Write Cycle Timing
○Page Write
If the Master transmits the next data instead of generating a STOP condition during the byte write cycle, the
BR24C21/F/FJ/FV transfers from byte write function to page write function. After receipt of each word, the three lower
order address bits are internally incremented by one, while the high order four bits of the word address remains
constant.
If the master transmits more than eight words, prior to generating the STOP condition, the address counter will “roll
over,” and the previous transmitted data will be overwritten.
S
T
A
R
T
SDA
LINE
W
R
I
T
E
SLAVE
ADDRESS
WORD
ADDRESS
（ ）
WA
* 6
1 0 1 0 ＊＊＊
DATA(n)
WA
0
RA
/ C
WK
S
T
O
P
DATA(n+7)
D0
D7
A
C
K
D0
A
C
K
A
C
K
VCLK
*:Don’t care
Fig.11 Page Write Cycle Timing
○Current Read
The BR24C21/F/FJ/FV contains an internal address counter which maintains the address of the last word accessed,
incremented by one. If the last accessed address is address “n” in a Read operation, the next Read operation will
access data from address “n+1” and increment the current address counter. If the last accessed address is address
”n” in a Write operation, the next Read operation will access data from address “n”. If the Master does not transfer an
Acknowledge, but does generate a STOP condition, the current address read operation will only provide a single byte of
data. At this point, the device discontinues transmission.
(See Fig.14 Sequential Read Cycle Timing)
S
T
A
R
T
SDA
LINE
R
E
A
D
SLAVE
ADRESS
1 0 1 0 ＊ ＊ ＊
DATA
D7
R A
/ C
W K
S
T
O
P
D0
*:Don’t care
A
C
K
Fig.12 Current Read Cycle Timing
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© 2009 ROHM Co., Ltd. All rights reserved.
6/22
2009.04 - Rev.A
BR24C21,BR24C21F,BR24C21FJ,BR24C21FV,
BU9882-W,BU9882F-W,BU9882FV-W
Technical Note
○Random Read
The Random read operation allows the Master to access any memory location. This operation involves a two-step
process. First, the Master issues a Write command that includes the START condition and the Slave address field
(with R/W set to “0”) followed by the word address of the word to be read. This procedure sets the internal address
counter of the BR24C21/F/FJ/FV to the desired address. After the word address Acknowledge is received by the
Master, the Master immediately re-issues a START condition followed by the Slave address field with R/W set to “1.”
The device will respond with an Acknowledge and then transmit the 8-data bits stored at the addressed location. If the
Master does not acknowledge the transmission but does generate the STOP condition, the IC will discontinue
transmission.
S
T
A
R
T
SDA
LINE
SLAVE
ADDRESS
W
R
I
T
E
S
T
A
R
T
WORD
ADDRESS（ｎ）
WA
0
WA
* 6
1 0 1 0 * * *
R A
/ C
W K
SLAVE
ADDRESS
R
E
A
D
DATA(n)
1 0 1 0 * * *
A
C
K
S
T
O
P
D7
D0
A
C
K
R A
/ C
W K
*:Don’t care
Fig.13 Random Read Cycle Timing
○Sequential Read
･If the Master does not transfer an Acknowledge and does not generate a STOP condition during the current Read
operation, the BR24C21/F/FJ/FV continues to output the next address data in sequence. For Read operations, all bits
in the address counter are incremented, allowing the entire array to be read during a single operation. When the
counter reaches the top of the array, it will “roll over” to the bottom of the array and continue to transmit data.
･If the Master does not acknowledge the transmission but does generate a STOP condition, at this point the device
discontinues transmission.
･The sequential Read operation can be performed with both Current Read and Random Read.
S
T
A
R
T
SDA
LINE
R
E
A
D
SLAVE
ADDRESS
1 0 1 0 * * *
DATA(n)
D7
R A
/ C
W K
S
T
O
P
DATA(n+x)
D0
D7
A
C
K
A
C
K
D0
*:Don’t care
A
C
K
Fig.14 Sequential Read Cycle Timing
(Current Read)
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© 2009 ROHM Co., Ltd. All rights reserved.
7/22
2009.04 - Rev.A
BR24C21,BR24C21F,BR24C21FJ,BR24C21FV,
BU9882-W,BU9882F-W,BU9882FV-W
Technical Note
BU9882-W,BU9882F-W,BU9882FV-W
●Description
BU9882F-W,BU9882FV-W are dual port EEPROMs compatible with the DDC2TM. 2 independent ports allow
2 EDID channels to be read simultaneously.
●Features
TM
1) Designed for use with DDC2
2) 2-port simultaneous read function
3) Operating voltage range: 2.5V-5.5V
4) Page write function: 8bytes
5) Low power consumption:
Active (at 5V) : 1.5mA(typ)
Stand-by (at 5V) : 0.1µA(typ)
6) Data security
Write protection with WP
Write protection at low power supply voltage
7) Various package types available: DIP14(BU9882-W) / SOP14(BU9882F-W) / SSOP14(BU9882FV-W)
8) Initial data: FFh
9) Data retention: 10years
10) Rewriting possible up to 100,000 times
●Absolute maximum ratings
Parameter
Supply Voltage
Power Dissipation
Storage Temperature
Operating
Temperature
Terminal Voltage
Symbol
VCC
Tstg
Rating
-0.3～+6.5
(DIP14)
(SOP14)
(SSOP14)
-65～+125
Topr
-40～+85
Pd
950
450
350
Unit
V
*1
*2
mW
*3
℃
℃
*4
-0.3～VCC+1.0
* Reduce by 9.5 mW/C over 25C (*1), 4.5mW/℃(*2), 3.5mW/℃(*3).
*4 6.8V (Max.)
V
●Recommended operating conditions
Parameter
Symbol
Rating
Unit
Supply Voltage
VCC
2.5～5.5
V
Input Voltage
VIN
0～VCC+1.0
V
●Memory cell characteristics
Write/Erase Cycle
Min.
100,000
Limits
Typ.
-
Max.
-
Cycle
Data Retention
10
-
-
Year
Parameter
www.rohm.com
© 2009 ROHM Co., Ltd. All rights reserved.
8/22
Unit
2009.04 - Rev.A
BR24C21,BR24C21F,BR24C21FJ,BR24C21FV,
BU9882-W,BU9882F-W,BU9882FV-W
Technical Note
●Electrical characteristics – DC (Unless otherwise specified, Ta=-40℃～+85℃,VCC=2.5V～5.5V)
Limits
Parameter
Symbol
Unit
Condition
Min.
Typ.
Max.
“H” Input Voltage 1
VIH1
2.0
-
-
V
“L” Input Voltage 1
“L” Input Voltage 2
“L” output Voltage
VIL1
-
VIL2
VOL1
-
-
0.8
V
VCC≧4.0V
-
0.2VCC
0.4
V
V
-1
-
1
µA
VCC＜4.0V
SDA_PC0/1, IOL=3.0mA *１
SCL_PC0/1,DDCENA, BANKSEL,
VIN=0V～VCC+1.0
Input Leakage Current 1
ILI1
Input Leakage Current 2
ILI2
-1
-
50
µA
Output Leakage Current
ILO
-1
-
1
µA
Operating Current
ICC
-
1.5
3.0
mA
Standby Current
ISB
-
0.1
5
µA
___
WP
SDA_PC0/1,SCL/SDA_MON(DDCENA=GND),
VOUT=0V～VCC+1.0
fSCL=400kHz, VCC=5.5V
tWR=10ms
SCL/SDA_PC0/1=VCC
SCL/SDA_MON=H-Z
DDCENA=WPB=BANKSEL=GND
DUALPCB=VCC
Note: This IC is not designed to be radiation-resistant
*1 IOL at monitor mode (DDCENA＝HIGH) is the sum of current flowing from the pull up resistor at the SDA_MON side to the pull up resistance
at SDA_PC0/PC1
●Electrical characteristics – AC (Unless otherwise specified, Ta=-40℃～+85℃､VCC=2.5V～5.5V)
Standard-mode
Fast-mode
VCC=2.5V～5.5V
VCC=2.5V～5.5V
Parameter
Symbol
Min.
Typ.
Max.
Min.
Typ.
Max.
Clock Frequency
fSCL
400
100
Data Clock High Period
tHIGH
0.6
4.0
Data Clock Low Period
tLOW
1.3
4.7
SDA and SCL Rise Time
tR
0.3
1.0
SDA and SCL Fall Time
Unit
Typ.
kHz
µs
µs
µs
tF
-
-
0.3
-
-
0.3
µs
Start Condition Hold Time
Start Condition Setup Time
tHD:STA
tSU:STA
0.6
0.6
-
-
4.0
4.7
-
-
µs
µs
Input Data Hold Time
tHD:DAT
0
-
-
0
-
-
ns
Input Data Setup Time
Output Data Delay Time(SCL)
Stop Condition Setup Time
Bus Free Time
Write Cycle Time
Noise Spike Width (SDA and SCL)
tSU:DAT
tPD
tSU:STO
tBUF
tWR
tI
100
0.6
1.3
-
-
0.9
10
0.1
250
4.0
4.7
-
-
3.5
10
0.1
ns
µs
µs
µs
ms
µs
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© 2009 ROHM Co., Ltd. All rights reserved.
9/22
2009.04 - Rev.A
BR24C21,BR24C21F,BR24C21FJ,BR24C21FV,
BU9882-W,BU9882F-W,BU9882FV-W
Technical Note
●Block diagram
1Kbit
Fig.15 Block Diagram
●Pin layout diagram
VCC
WP
DUALPCB BANKSEL DDCENA SCL_MON SDA_MON
BU9882-W
BU9882F-W
BU9882FV-W
SCL_PC0 SDA_PC0
●Pin description
Pin Name
N.C.
SCL_PC1 SDA_PC1
N.C.
GND
Fig.16 Pin Layout
I/O
Functions
VCC
-
Power Supply
GND
-
Ground (0V)
N.C.
-
No Connection
SCL_PC0
IN
SDA_PC0
IN/OUT
SCL_PC1
IN
SDA_PC1
IN/OUT
SCL_MON
OUT
SDA_MON
OUT
DDCENA
IN
Control of SCL_MON, SDA_MON
BANKSEL
IN
Select a SCL/SDA_MON Connected Port at DUAL PORT mode
Selected a BANK at SINGLE PORT mode
DUALPCB
IN
Control of DUAL PORT/SINGLE PORT mode
IN
Write Protect Control
―――
wp
Serial Clock Input, Access to BANK0 at DUAL PORT mode
Access to BANK0 or to BANK1 at SINGLE PORT mode
Slave and Word Address Serial Data Input, Serial Data Output
Access to BANK0 at DUAL PORT mode, Access to BANK0 or to BANK1 at SINGLE PORT mode
Serial Clock Input
Access to BANK1 at DUAL PORT mode, Don't Care at SINGLE PORT mode
Slave and Word Address Serial Data Input, Serial Data Output
Access to BANK1 at DUAL PORT mode, Don't Care at SINGLE PORT mode
Serial Clock Output
Connected to SCL_PC0/1 at DDCENA="High", "Hi-Z" output at DDCENA="Low"
Slave and Word Address Serial Data Output
Connected to SCL_PC0/1 DDCENA="High", "Hi-Z" output at DDCENA="Low"
An open drain output requires a pull-up resistor.
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© 2009 ROHM Co., Ltd. All rights reserved.
10/22
2009.04 - Rev.A
BR24C21,BR24C21F,BR24C21FJ,BR24C21FV,
BU9882-W,BU9882F-W,BU9882FV-W
Technical Note
●Synchronous data timing
tF
tR
tHIGH
SCL
SCL
tHD:STA
tSU:DAT
tHD:DAT
tLOW
SDA
(IN)
tBUF
tSU:STA
tHD:STA
tSU:STO
SDA
tPD
SDA
(OUT)
START BIT
STOP BIT
Fig.17 Synchronous Data Timing
・SDA data is latched into the chip at the rising edge of the SCL clock.
・The output date toggles at the falling edge of the SCL clock.
●Write cycle timing
SCL
SDA
D0
ACK
tWR
WRITE DATA (n)
STOP CONDITION
START CONDITION
Fig.18 Write Cycle Timing
●Operation notes
○DDCENA Operation
When DDCENA is set to High, SCL_PC0/1 and SDA_PC0/1 will be connected to SCL_MON and SDA_MON,
respectively. Therefore, monitoring of the communications between the PC and EEPROM, and the communications of
the MONITOR and PC, is possible.
Selection of PC0/PC1 is determined according to the state of the DUALPCB and BANKSEL inputs.
When DDCENA is Low, the SCL/SDA_MON output is set to "Hi-Z".
SCL_MON,SDA_MON
DUALPCB
BANKSEL
(CONNECTION PORT)
Low
PC0 PORT
Low (DUAL PORT)
High
PC1 PORT
Low
High (SINGLE PORT)
PC0 PORT
High
○BANKSEL
BANKSEL serves as an input for connection port of SCL/SDA_MON during DUAL PORT mode.
It turns into the BANK selection terminal of internal memory in SINGLE PORT mode.
Only the PC0 port can access the memory in SINGLE PORT mode.
DUALPCB
Low (DUAL PORT)
High (SINGL PORT)
BANKSEL
Low
High
Low
High
CONNECTION BANK
PC0 PORT：BANK0
PC1 PORT：BANK1
BANK0
BANK1
○WP
When WP=Low, all data at all addresses are write-protected. The terminal has a built-in pull down resister. Make sure
that WP=High when writing data.
Utilize this function in order to prevent incorrect write command input from the PC, as well as incorrect input during
communication between the PC and monitor.
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© 2009 ROHM Co., Ltd. All rights reserved.
11/22
2009.04 - Rev.A
BR24C21,BR24C21F,BR24C21FJ,BR24C21FV,
BU9882-W,BU9882F-W,BU9882FV-W
Technical Note
○Data Read
The data read function allows simultaneous read from SCL_PC0/1, SDA_PC0/1 in DUAL PORT mode.
○Data Write
Write operation is performed using either PC0/1 (SCL or SDA) even when accessed simultaneously in DUAL PORT mode.
Port selection is made by detecting the data D0 of the first byte of the WRITE command input.
After this, the other port is made unavailable for both READ and WRITE commands until the write operation is completed.
S
T
A
R
T
SDA_PC
W
R
I
T
E
SLAVE
ADDRESS
1 0 1 0 0 0
*:Don’t care
WORD
ADDRESS
0
*
WA
6
WA
0
R A
/ C
W K
S
T
O
P
DATA
D7
D0
A
C
K
A
C
K
D0 detected first write operation
performed through the port
During other port is write command.
this ack is no output.
Fig.19 Write Cycle Timing
○START Condition
All commands are preceeded by the START condition, which is a High to Low transition of SDA when SCL is High. This
IC continuously monitors the SDA and SCL lines for the START condition and will not respond to any commands until
this condition has been met.
○STOP Condition
All commands must be terminated by a STOP condition, which is a Low to High transition of SDA when SCL is HIGH.
(See Fig.17)
○WRITE Command
Unless a STOP condition is executed, the data will not be written into the memory array.
○DEVICE ADDRESSING
Following a START condition, the Master outputs the device address of the slave to be accessed.
The most significant four bits of the Slave address are the "device type indentifier".
For the IC this is fixed as "1010".
The next three bits are "000".
The last bit of the stream determines the operation to be performed.
When set to "1", Read operation is selected ; when set to "0", Write operation is selected.
R/W set to "0" ・ ・ ・ ・ ・ ・ ・ ・ WRITE
R/W set to "1" ・ ・ ・ ・ ・ ・ ・ ・ READ
1010
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© 2009 ROHM Co., Ltd. All rights reserved.
0
0
―
0
R/W
12/22
2009.04 - Rev.A
BR24C21,BR24C21F,BR24C21FJ,BR24C21FV,
BU9882-W,BU9882F-W,BU9882FV-W
Technical Note
●Commands
○Byte Write
When the Master generates a STOP condition, the IC begins an internal write cycle to the nonvolatile array.
S
T
A
R
T
W
R
I
T
E
SLAVE
ADDRESS
SDA
LINE
1 0 1 0 0 0
WORD
ADDRESS
0
*
WA
0
WA
6
R A
/ C
W K
S
T
O
P
DATA
D7
D0
A
C
K
A
C
K
*:Don’t care
Fig.20 Byte Write Cycle Timing
○Page Write
After the receipt of each word, the three low order address bits are internally increased by one. The four higher order
bits of the address(WA6～WA3) remain constant. This IC is capable of eight byte page write operation.
If the master transnmits more than eight words, prior to generating the STOP condition, the address counter will "roll
over", and the previous transmitted data will be overwritten.
S
T
A
R
T
SDA
LINE
W
R
I
T
E
SLAVE
ADDRESS
WORD
ADDRESS
（ ）
WA
* 6
1 0 1 0 0 0 0
R
/
W
WA
0
D7
D0
A
C
K
A
C
K
S
T
O
P
DATA(n+7)
DATA(n)
D0
A
C
K
A
C
K
*:Don’t care
Fig.21 Page Write Cycle Timing
○Current Read
In case the previous operation is random or current read (which includes sequential read), the internal address counter
is increased by one from the last acceseed address (n). Thus current read outputs the data of the next word address
(n+1).
If the last command is byte or page write, the internal address stays at the last address(n). Thus current read outputs
the data of the word address (n).
If the master does not transfer the Acknowledge, but does generate a stop condition, the current address read operation
only provides a single byte of data.
At this point, the BU9882/F/FV-W discontinues transmission.
S
T
A
R
T
SLAVE
ADRESS
SDA
LINE
R
E
A
D
S
T
O
P
DATA
1 0 1 0 0 0 0
D7
D0
R A
/ C
W K
A
C
K
Fig.22 Current Read Cycle Timing
○Random Read
Random read operation allows the master to access any location.If the master does not transfer the Acknowledge but
does generate a stop condition, the current address read operation only provides a single byte of data. (At 1Kbit all
address read possible).This communication must be terminated by a stop condition, which is a Low to High transition of
SDA when SCL is High
S
T
A
R
T
SDA
LINE
SLAVE
ADDRESS
W
R
I
T
E
WORD
ADDRESS
（ ）
WA
* 6
1 0 1 0 0 0 0
R A
/ C
W K
S
T
A
R
T
WA
0
SLAVE
ADDRESS
R
E
A
D
1 0 1 0 0 0 0
A
C
K
DATA(n)
D7
R A
/ C
W K
S
T
O
P
D0
A
C
K
*:Don’t care
Fig.23 Random Read Cycle Timing
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© 2009 ROHM Co., Ltd. All rights reserved.
13/22
2009.04 - Rev.A
BR24C21,BR24C21F,BR24C21FJ,BR24C21FV,
BU9882-W,BU9882F-W,BU9882FV-W
Technical Note
○Sequential Read
During the Current read operation, if an Acknowledge is detected, and no STOP condition is generated by the
master(µ-COM), the device will continue to transmit the data. (It can transmit all data(1Kbit 128word)). If an
Acknowledge is not detected, the devive will terminate further data transmissions and await a STOP condition before
returning to the standby mode. The Sequential Read operation can be performed with both
Current Read and
Random Read.
S
T
A
R
T
SDA
LINE
R
E
A
D
SLAVE
ADDRESS
DATA(n)
1 0 1 0 0 0 0
D7
S
T
O
P
DATA(n+x)
D0
R A
/ C
W K
D7
A
C
K
D0
A
C
K
A
C
K
Fig.24 Sequential Read Cycle Timing
●Peripheral Circuits
○DUAL PORT
DUAL PORTs are used to connect two PCs to one monitor. PC0 is connected to BANK0 and PC1 to BANK1. Each bank
operates as 1Kbit EEPROM.
○ To Use DUAL PORT
Start the operation of the DUAL PORT by following the instructions below:
1. Set the DUAL PCB to LOW with neither of the ports being operated by commands.
2. Input the command from PC0 or PC1.
○ Simultaneous Access
<READ OPERATION>
EEPROM data read allows simultaneous access from PC0, PC1 ports.
<WRITE OPERATION>
Write operation is performed for either of PC0/1 even when accessed simultaneously from both.
Port selection is made by detecting the data D0 of the first byte of the WRITE command input.
Write operation is performed only for the port where D0 of the first byte of the write data is detected first.
PC 0
MONITOR
ＶCC
SCL
SDA
VCC
SCL_PC0
BANK0
(1kbit)
SDA_PC0
DUALPCB
NC
BANKSEL
SCL_PC1
BANK1
(1kbit)
SDA_PC1
PC 1
WP
WPB
CPU
DDCENA
NC
SCL_MON
GND
SDA_MON
SCL
SDA
Fig.25 Example of Peripheral Circuit with Dual Port
S
T
A
R
T
SDA-PC0
BUS
SLAVE
ADDRESS
1
1
R A
/ C
W K
Output Data from BANK0
D7
D0
Write operation performed
Through the port.
S
T
A
R
T
S
A T
C O
K P
SDA-PC0
BUS
SLAVE
ADDRESS
1
R
/
W
*WA6
*WA
6
1
S
T
O
P
BANK0 WORD
ADDRESS(W)
WA0
WA
0
D7
D0
S
T
O
P
Output Data from BANK1
SDA-PC1
BUS
SDA-PC1
BUS
BANK1 WORD
ADDRESS(W)
Output Data from BANK1
1
1
D7
D0
1
1
D7
D0
Fig.26 SIMULTANEOUS ACCESS
OF READ OPERATION
SDA-PC1
BUS
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1
*WA6
WA0
D7
Fig.27 Simultaneous Access
Fig.27
Simultaneous
Of Write
Operation Access
of White Operation
Fig.26 Simultaneous Access
of Read Operation
© 2009 ROHM Co., Ltd. All rights reserved.
1
14/22
D0
No ACK
*:Don’t care
2009.04 - Rev.A
BR24C21,BR24C21F,BR24C21FJ,BR24C21FV,
BU9882-W,BU9882F-W,BU9882FV-W
Technical Note
○MONITOR OUTPUT
BU9882F-W, BU9882FV-W has a monitor output terminal. This allows communication between the PC and monitor CPU.
The monitor output for the use of DUAL PORT can be switched with BANKSEL input, as shown in the table below.
BANKSEL input
Low
High
SCL_MON,SDA_MON connection port
PC0 PORT
PC1 PORT
○SINGLE PORT
SINGLE PORT is for connecting one PC to one monitor. In this case, it is accessible only from PC0. BANK selection is
made with BANKSEL.
Switching this BANKSEL allows access to the total of 2kbit EEPROM, with BANK0 and BANK1, from PC0.
○ To use SINGLE PORT
Start the SINGLE PORT operation by following the instructions below:
1. Set the DUAL PCB to High with neither of the ports being operated by commands.
2. Select the BANK with BANKSEL.
3. Input the command from PC0.
PC 0
MONITOR
ＶCC
SCL
SDA
VCC
SCL_PC0
SDA_PC0
BANK0
(1kbit)
NC
WP
DUALPCB
BANKSEL
SCL_PC1
SDA_PC1
BANK1
(1kbit)
DDCENA
CPU
SCL_MON
NC
SDA_MON
GND
Fig.28 Example of Peripheral Circuit with Single Port
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© 2009 ROHM Co., Ltd. All rights reserved.
15/22
2009.04 - Rev.A
BR24C21,BR24C21F,BR24C21FJ,BR24C21FV,
BU9882-W,BU9882F-W,BU9882FV-W
Technical Note
Common Application Note
●Software Reset
Execute software reset in case the device is at an unexpected state after power up and/or the command input needs to be
reset. The following figures (Fig.29-(a), Fig.29-(b), Fig.29-(c))
During dummy clock, please release SDA BUS (tied to Vcc by pull up resistor).
During that time, the device may pull the SDA line Low for acknowledge or outputting read data. If the master controls the
SDA line High, it will conflict with the device output Low then it makes a current overload. It may cause instantaneous
power down and may damage the device.
Start×2
Dummy Clock×14
SCL
2
1
13
14
COMMAND
SDA
COMMAND
Fig.29-(a) Dummy Clock×14＋Start＋Start
Start
Start
Dummy Clock×9
1
SCL
2
8
9
COMMAND
SDA
COMMAND
Fig.29-(b) Start＋Dummy Clock×9＋Start
Start×9
SCL
2
1
7
3
8
9
COMMAND
SDA
COMMAND
Fig.29-(c) Start×9
●Acknowledge Polling
Since the device ignores all input commands during the internal write cycle, no ACK will be returned. When the master sends
the next command following the write command, and the device returns the ACK, it means that the program is completed. If
no ACK is returned, it means that the device is still busy. By using Acknowledge polling, the waiting time is minimized to less
than tWR=5ms. To prevent operating Write or Current Read immediately after Write, first send the slave address (R/W is
"High" or "Low"). After the device returns the ACK, continue word address input or data output, respectively.
During the internal write cycle,
no ACK will be returned.
(ACK=High)
THE FIRST WRITE COMMAND
S
T
A WRITE COMMAND
R
T
S
T
O
P
S
T SLAVE
A
R ADDRESS
T
S
T SLAVE
A
R ADDRESS
T
A
C
K
H
A
C
K
H
…
tWR
THE SECOND WRITE COMMAND
…
S
A
T
SLAVE
C
A
R ADDRESS K
H
T
S
A
T SLAVE C
A
K
ADDRESS
R
L
T
tWR
WORD
ADDRESS
A
C
K
L
DATA
A
C
K
L
S
T
O
P
After the internal write cycle
is completed ACK will be returned
(ACK=Low). Then input next
Word Address and data.
Fig.30 Successive Write Operation By Acknowledge Polling
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© 2009 ROHM Co., Ltd. All rights reserved.
16/22
2009.04 - Rev.A
BR24C21,BR24C21F,BR24C21FJ,BR24C21FV,
BU9882-W,BU9882F-W,BU9882FV-W
Technical Note
●Command Cancellation By Start And Stop Condition
During a command input, command is canceled by the successive inputs of start condition and stop condition (Fig.31).
However, during ACK or data output, the device may output the SDA line Low. In such cases, operation of start and stop
condition is impossible, making the reset inoperable. Execute the software reset in the cases. (Fig.29)
Operating the command cancel by start and stop condition during the command of Random Read or Sequential Read or
Current Read, internal address counter is not confirmed. Therefore operation of Current Read after this is not valid.
Operate a Random Read in this case.
SCL
SDA
1
0
1
0
Start
Condition
Stop
Condition
Fig.31 Command Cancellation
●I/O Circuit
○SDA Pin Pull-up Resister
The pull up resister is needed because SDA is NMOS open drain. Choose the correct value of this resister(RPU), by
considering VIL, IL characteristics of a controller which control the device and VOH, IOL characteristics of the device. If
large RPU is chosen, clock frequency needs to be slow. In case of small RPU, the operating current increases.
○Maximum Rpu
Maximum value of RPU is determined by following factors:
①SDA rise time determined by RPU and the capacitance of bus line(CBUS) must be less than tR.
Other timing must keep the conditions of AC spec.
A of SDA bus determined by a total input leak(IL) of the all devices connected to
②When SDA bus is High, the voltage ○
the bus. RPU must be significantly higher than the High level input of a controller and the device, including a noise
margin 0.2VCC.
VCC-ILRPU-0.2 VCC ≧ VIH
MICRO
COMPUTER
0.8Vcc-VIH
∴
≦
RPU
RPU
IL
A
Examples: When VCC=3V IL=10µA VIH=0.7VCC
According to ②
0.8x3-0.7x3
≦
RPU
10x10-6
≦
300 [kΩ]
IL
SDA PIN
IL
THE CAPACITANCE OF
BUS LINE (CBUS)
Fig.32 I/O Circuits
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© 2009 ROHM Co., Ltd. All rights reserved.
17/22
2009.04 - Rev.A
BR24C21,BR24C21F,BR24C21FJ,BR24C21FV,
BU9882-W,BU9882F-W,BU9882FV-W
Technical Note
○Minimum RPU
The minimum value of RPU is determined by following factors:
①Meets the condition that VOLMAX=0.4V, IOLMAX=3mA when the output is Low.
VCC -VOL
≦ IOL
R PU
VCC -VOL
IOL
② VOLMAX=0.4V must be lower than the input Low level of the microcontroller and the EEPROM
including the recommended noise margin of 0.1VCC.
VOLMAX ≦ VIL-0.1 VCC
Examples: VCC=3V, VOL=0.4V, IOL=3mA, the VIL of the controller and
According to ①
∴
R PU
≧
RPU ≧
3-0.4
3×10 -3
≧ 867 ［Ω］
the EEPROM is VIL=0.3VCC,
VOL=0.4［V］
VIL=0.3×3
=0.9［V］
so that condition② is met
and
○SCL Pin Pull-up Resister
When SCL is controlled by the CMOS output the pull-up resistor at SCL is not required.
However, should SCL be set to Hi-Z, connection of a pull-up resistor between SCL and VCC is recommended.
Several kΩ are recommended for the pull-up resistor in order to drive the output port of the microcontroller.
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© 2009 ROHM Co., Ltd. All rights reserved.
18/22
2009.04 - Rev.A
BR24C21,BR24C21F,BR24C21FJ,BR24C21FV,
BU9882-W,BU9882F-W,BU9882FV-W
Technical Note
●Notes For Power Supply
VCC rises through the low voltage region in which the internal circuit of the IC and the controller are unstable. Therefore,
the device may not work properly due to an incomplete reset of the internal circuit. To prevent this, the device has a P.O.R.
and LVCC feature. At power up, maintain the following conditions to ensure functions of P.O.R and LVCC.
1. "SDA='H'" and "SCL='L' or 'H'".
2. Follow the recommended conditions of tR, tOFF, Vbot for the P.O.R. function during power up.
tR
VCC
Recommended conditions of tR, tOFF, Vbot
tOFF
tR
tOFF
Vbot
Below 10ms
Above 10ms
Below 0.3V
Below 100ms
Above 10ms
Below 0.2V
Vbot
0
Fig.33 Vcc rising wave from
3. Prevent SDA and SCL from being "Hi-Z".
In case conditions 1 and/or 2 cannot be met, take following actions:
A)If unable to keep condition 1 ( SDA is "Low" during power up):
→Control SDA ,SCL to be "High" as shown in figure below.
VCC
tLOW
SCL
SDA
After Vcc becoms stable
After Vcc becoms stable
tDH
tSU:DAT
tSU:DAT
Fig.34 SCL="H" and SDA="L"
Fig.35 SCL="L" and SDA="L"
B)If unable to keep condition 2.
→After power becomes stable, execute software reset. (See Fig.29)
C)If unable to keep both conditions 1 and 2.
→Follow the instruction A first, then the instruction B.
●LVCC Circuit
LVCC circuit inhibits write operation at low voltage, and prevents an inadvertent write. Write operation is inhibited below the
LVCC voltage (Typ.=1.2V).
●Vcc NOISE
○Bypass Condenser
Noise and surges on power line may cause abnormal function. It is recommended that the bypass condensers (0.1µF) are
attached on the Vcc and GND line beside the device. It is also recommended to attach bypass condensers on the board
close to the connector.
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© 2009 ROHM Co., Ltd. All rights reserved.
19/22
2009.04 - Rev.A
BR24C21,BR24C21F,BR24C21FJ,BR24C21FV,
BU9882-W,BU9882F-W,BU9882FV-W
Technical Note
●Notes for Use
1) Described numeric values and data are design representative values, and the values are not guaranteed.
2) We believe that application circuit examples are recommendable, however, in actual use, confirm characteristics further
sufficiently. In the case of use by changing the fixed number of external parts, make your decision with sufficient margin
in consideration of static characteristics and transition characteristics and fluctuations of external parts and our LSI.
3) Absolute maximum ratings
If the absolute maximum ratings such as impressed voltage and operating temperature range and so forth are
exceeded, LSI may be destructed. Do not impress voltage and temperature exceeding the absolute maximum ratings.
In the case of fear exceeding the absolute maximum ratings, take physical safety countermeasures such as fuses, and
see to it that conditions exceeding the absolute maximum ratings should not be impressed to LSI.
4) GND electric potential
Set the voltage of GND terminal lowest at any action condition. Make sure that each terminal voltages is lower than that
of GND terminal.
5) Heat design
In consideration of permissible dissipation in actual use condition, carry out heat design with sufficient margin.
6) Terminal to terminal shortcircuit and wrong packaging
When to package LSI onto a board, pay sufficient attention to LSI direction and displacement. Wrong packaging may
destruct LSI. And in the case of shortcircuit between LSI terminals and terminals and power source, terminal and GND
owing to foreign matter, LSI may be destructed.
7) Use in a strong electromagnetic field may cause malfunction, therefore, evaluated design sufficiently
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© 2009 ROHM Co., Ltd. All rights reserved.
20/22
2009.04 - Rev.A
BR24C21,BR24C21F,BR24C21FJ,BR24C21FV,
BU9882-W,BU9882F-W,BU9882FV-W
Technical Note
●Ordering part number
B
R
2
ROHM type
4
C
BUS type
2
Product type
24：I2C
1
F
Capacity
-
Package
21= 1K
F : SOP8
E
2
Packaging and forming specification
E2: Embossed tape and reel
FJ : SOP-J8
FV : SSOP-B8
SOP8
<Tape and Reel information>
5.0±0.2
(MAX 5.35 include BURR)
6
+6°
4° −4°
5
4.4±0.2
6.2±0.3
1 2
3
0.9±0.15
7
0.3MIN
8
Tape
Embossed carrier tape
Quantity
2500pcs
Direction
of feed
E2
The direction is the 1pin of product is at the upper left when you hold
( reel on the left hand and you pull out the tape on the right hand
)
4
0.595
1.5±0.1
+0.1
0.17 -0.05
0.11
S
1.27
0.42±0.1
1pin
Reel
(Unit : mm)
Direction of feed
∗ Order quantity needs to be multiple of the minimum quantity.
SOP-J8
<Tape and Reel information>
4.9±0.2
(MAX 5.25 include BURR)
+6°
4° −4°
6
5
0.45MIN
7
3.9±0.2
6.0±0.3
8
1
2
3
Tape
Embossed carrier tape
Quantity
2500pcs
Direction
of feed
E2
The direction is the 1pin of product is at the upper left when you hold
( reel on the left hand and you pull out the tape on the right hand
)
4
0.545
0.2±0.1
0.175
1.375±0.1
S
1.27
0.42±0.1
0.1 S
1pin
Reel
(Unit : mm)
Direction of feed
∗ Order quantity needs to be multiple of the minimum quantity.
SSOP-B8
<Tape and Reel information>
3.0 ± 0.2
(MAX 3.35 include BURR)
0.3MIN
4.4±0.2
6.4±0.3
8 76 5
Tape
Embossed carrier tape
Quantity
2500pcs
Direction
of feed
E2
The direction is the 1pin of product is at the upper left when you hold
( reel on the left hand and you pull out the tape on the right hand
)
1.15±0.1
1 23 4
0.15 ± 0.1
0.1
S
0.1
+0.06
0.22 -0.04
(0.52)
0.08
M
0.65
1pin
(Unit : mm)
Reel
Direction of feed
∗ Order quantity needs to be multiple of the minimum quantity.
.
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© 2009 ROHM Co., Ltd. All rights reserved.
21/22
2009.04 - Rev.A
BR24C21,BR24C21F,BR24C21FJ,BR24C21FV,
BU9882-W,BU9882F-W,BU9882FV-W
B
U
9
ROHM type
8
8
Technical Note
2
F
Part No.
V
-
W
E
2
W: Double cell
Packaging and forming specification
E2: Embossed tape and reel
Package
F : SOP14
FV : SSOP-B14
SOP14
<Tape and Reel information>
8.7 ± 0.2
(MAX 9.05 include BURR)
8
Tape
Embossed carrier tape
Quantity
2500pcs
Direction
of feed
0.3MIN
4.4±0.2
6.2±0.3
14
1
E2
The direction is the 1pin of product is at the upper left when you hold
( reel on the left hand and you pull out the tape on the right hand
)
7
1.5±0.1
0.15 ± 0.1
0.4 ± 0.1
0.11
1.27
0.1
1pin
Reel
(Unit : mm)
Direction of feed
∗ Order quantity needs to be multiple of the minimum quantity.
SSOP-B14
<Tape and Reel information>
5.0 ± 0.2
8
0.3Min.
4.4 ± 0.2
6.4 ± 0.3
14
1
Tape
Embossed carrier tape
Quantity
2500pcs
Direction
of feed
E2
The direction is the 1pin of product is at the upper left when you hold
( reel on the left hand and you pull out the tape on the right hand
)
7
0.10
1.15 ± 0.1
0.15 ± 0.1
0.65
0.1
0.22 ± 0.1
1pin
(Unit : mm)
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© 2009 ROHM Co., Ltd. All rights reserved.
Reel
22/22
Direction of feed
∗ Order quantity needs to be multiple of the minimum quantity.
2009.04 - Rev.A
Notice
Notes
No copying or reproduction of this document, in part or in whole, is permitted without the
consent of ROHM Co.,Ltd.
The content specified herein is subject to change for improvement without notice.
The content specified herein is for the purpose of introducing ROHM's products (hereinafter
"Products"). If you wish to use any such Product, please be sure to refer to the specifications,
which can be obtained from ROHM upon request.
Examples of application circuits, circuit constants and any other information contained herein
illustrate the standard usage and operations of the Products. The peripheral conditions must
be taken into account when designing circuits for mass production.
Great care was taken in ensuring the accuracy of the information specified in this document.
However, should you incur any damage arising from any inaccuracy or misprint of such
information, ROHM shall bear no responsibility for such damage.
The technical information specified herein is intended only to show the typical functions of and
examples of application circuits for the Products. ROHM does not grant you, explicitly or
implicitly, any license to use or exercise intellectual property or other rights held by ROHM and
other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the
use of such technical information.
The Products specified in this document are intended to be used with general-use electronic
equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices).
The Products specified in this document are not designed to be radiation tolerant.
While ROHM always makes efforts to enhance the quality and reliability of its Products, a
Product may fail or malfunction for a variety of reasons.
Please be sure to implement in your equipment using the Products safety measures to guard
against the possibility of physical injury, fire or any other damage caused in the event of the
failure of any Product, such as derating, redundancy, fire control and fail-safe designs. ROHM
shall bear no responsibility whatsoever for your use of any Product outside of the prescribed
scope or not in accordance with the instruction manual.
The Products are not designed or manufactured to be used with any equipment, device or
system which requires an extremely high level of reliability the failure or malfunction of which
may result in a direct threat to human life or create a risk of human injury (such as a medical
instrument, transportation equipment, aerospace machinery, nuclear-reactor controller,
fuel-controller or other safety device). ROHM shall bear no responsibility in any way for use of
any of the Products for the above special purposes. If a Product is intended to be used for any
such special purpose, please contact a ROHM sales representative before purchasing.
If you intend to export or ship overseas any Product or technology specified herein that may
be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to
obtain a license or permit under the Law.
Thank you for your accessing to ROHM product informations.
More detail product informations and catalogs are available, please contact us.
ROHM Customer Support System
http://www.rohm.com/contact/
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© 2009 ROHM Co., Ltd. All rights reserved.
R0039A