PHILIPS BUK542-100A Powermos transistor logic level fet Datasheet

Philips Semiconductors
Product Specification
PowerMOS transistor
Logic level FET
GENERAL DESCRIPTION
N-channel enhancement mode
logic level field-effect power
transistor in a plastic full-pack
envelope.
The device is intended for use in
Switched Mode Power Supplies
(SMPS), motor control, welding,
DC/DC and AC/DC converters, and
in automotive and general purpose
switching applications.
PINNING - SOT186
PIN
BUK542-100A/B
QUICK REFERENCE DATA
SYMBOL
PARAMETER
MAX.
MAX.
UNIT
VDS
ID
Ptot
RDS(ON)
BUK542
Drain-source voltage
Drain current (DC)
Total power dissipation
Drain-source on-state
resistance;
VGS = 5 V
-100A
100
6.3
22
0.28
-100B
100
5.6
22
0.35
V
A
W
Ω
PIN CONFIGURATION
SYMBOL
DESCRIPTION
d
case
1
gate
2
drain
3
source
g
case isolated
s
1 2 3
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VDS
VDGR
±VGS
±VGSM
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Non-repetitive gate-source voltage
RGS = 20 kΩ
tp ≤ 50 µs
-
100
100
15
20
V
V
V
V
ID
ID
IDM
Drain current (DC)
Drain current (DC)
Drain current (pulse peak value)
Ths = 25 ˚C
Ths = 100 ˚C
Ths = 25 ˚C
-
Ptot
Tstg
Tj
Total power dissipation
Storage temperature
Junction Temperature
Ths = 25 ˚C
-
- 55
-
-100A
6.3
4
25
-100B
5.6
3.5
22
A
A
A
22
150
150
W
˚C
˚C
THERMAL RESISTANCES
SYMBOL
PARAMETER
CONDITIONS
Rth j-hs
Thermal resistance junction to
heatsink
Thermal resistance junction to
ambient
with heatsink compound
Rth j-a
April 1993
1
MIN.
TYP.
MAX.
UNIT
-
-
5.68
K/W
-
55
-
K/W
Rev 1.100
Philips Semiconductors
Product Specification
PowerMOS transistor
Logic level FET
BUK542-100A/B
STATIC CHARACTERISTICS
Ths = 25 ˚C unless otherwise specified
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
V(BR)DSS
Drain-source breakdown
voltage
Gate threshold voltage
Zero gate voltage drain current
Zero gate voltage drain current
Gate source leakage current
Drain-source on-state
resistance
VGS = 0 V; ID = 0.25 mA
100
-
-
V
VDS = VGS; ID = 1 mA
VDS = 100 V; VGS = 0 V; Tj = 25 ˚C
VDS = 100 V; VGS = 0 V; Tj =125 ˚C
VGS = ±15 V; VDS = 0 V
VGS = 5 V;
BUK542-100A
BUK542-100B
ID = 5.5 A
1.0
-
1.5
1
0.1
10
0.25
0.3
2.0
10
1.0
100
0.28
0.35
V
µA
mA
nA
Ω
Ω
MIN.
TYP.
MAX.
UNIT
VGS(TO)
IDSS
IDSS
IGSS
RDS(ON)
DYNAMIC CHARACTERISTICS
Ths = 25 ˚C unless otherwise specified
SYMBOL
PARAMETER
CONDITIONS
gfs
Forward transconductance
VDS = 25 V; ID = 5.5 A
4.5
6
-
S
Ciss
Coss
Crss
Input capacitance
Output capacitance
Feedback capacitance
VGS = 0 V; VDS = 25 V; f = 1 MHz
-
400
90
35
600
120
50
pF
pF
pF
td on
tr
td off
tf
Turn-on delay time
Turn-on rise time
Turn-off delay time
Turn-off fall time
VDD = 30 V; ID = 3 A;
VGS = 5 V; RGS = 50 Ω;
Rgen = 50 Ω
-
12
45
50
30
18
70
70
45
ns
ns
ns
ns
Ld
Internal drain inductance
-
4.5
-
nH
Ls
Internal source inductance
Measured from drain lead 6 mm
from package to centre of die
Measured from source lead 6 mm
from package to source bond pad
-
7.5
-
nH
MIN.
TYP.
MAX.
UNIT
1500
V
ISOLATION LIMITING VALUE & CHARACTERISTIC
Ths = 25 ˚C unless otherwise specified
SYMBOL
PARAMETER
CONDITIONS
Visol
Repetitive peak voltage from all
three terminals to external
heatsink
R.H. ≤ 65% ; clean and dustfree
Cisol
Capacitance from T2 to external f = 1 MHz
heatsink
-
-
12
-
pF
MIN.
TYP.
MAX.
UNIT
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
Ths = 25 ˚C unless otherwise specified
SYMBOL
PARAMETER
CONDITIONS
IDR
-
-
-
6.3
A
IDRM
VSD
Continuous reverse drain
current
Pulsed reverse drain current
Diode forward voltage
IF = 6.3 A ; VGS = 0 V
-
1.2
25
1.5
A
V
trr
Qrr
Reverse recovery time
Reverse recovery charge
IF = 6.3 A; -dIF/dt = 100 A/µs;
VGS = 0 V; VR = 30 V
-
80
0.30
-
ns
µC
April 1993
2
Rev 1.100
Philips Semiconductors
Product Specification
PowerMOS transistor
Logic level FET
BUK542-100A/B
AVALANCHE LIMITING VALUE
Ths = 25 ˚C unless otherwise specified
SYMBOL
PARAMETER
CONDITIONS
WDSS
Drain-source non-repetitive
unclamped inductive turn-off
energy
ID = 10 A ; VDD ≤ 50 V ;
VGS = 5 V ; RGS = 50 Ω
Normalised Power Derating
PD%
120
100
with heatsink compound
110
MIN.
TYP.
MAX.
UNIT
-
-
30
mJ
ID / A
BUK542-100
100
90
ID
S/
80
70
N)
10
=
VD
A
B
tp = 10 us
(O
S
RD
100 us
60
50
1 ms
40
1
DC
10 ms
30
100 ms
20
10
0
0
20
40
60
80
Ths / C
100
120
0.1
140
1
VDS / V
Fig.1. Normalised power dissipation.
PD% = 100⋅PD/PD 25 ˚C = f(Ths)
120
Fig.3. Safe operating area. Ths = 25 ˚C
ID & IDM = f(VDS); IDM single pulse; parameter tp
Normalised Current Derating
ID%
1E+01
with heatsink compound
110
100
10
100
90
Zth j-hs / (K/W)
ZTHX42
0.5
80
70
1E+00
60
50
1E-01
40
0.2
0.1
0.05
0.02
PD
30
10
1E-02
1E-07
0
0
20
40
60
80
Ths / C
100
120
140
Fig.2. Normalised continuous drain current.
ID% = 100⋅ID/ID 25 ˚C = f(Ths); conditions: VGS ≥ 5 V
April 1993
tp
D=
tp
T
0
20
T
1E-05
1E-03
t/s
1E-01
t
1E+01
Fig.4. Transient thermal impedance.
Zth j-hs = f(t); parameter D = tp/T
3
Rev 1.100
Philips Semiconductors
Product Specification
PowerMOS transistor
Logic level FET
20
BUK542-100A/B
BUK552-100A
ID / A
VGS / V =
10
7
gfs / S
6
5
BUK 552-100A
5
15
4
10
4
5
3
3
2
1
0
0
0
2
4
6
8
10
0
2
4
6
8
VDS / V
Fig.5. Typical output characteristics, Tj = 25 ˚C.
ID = f(VDS); parameter VGS
1.0
3
14
16
18
20
Fig.8. Typical transconductance, Tj = 25 ˚C.
gfs = f(ID); conditions: VDS = 25 V
BUK552-100A
RDS(ON) / Ohm
10 12
ID / A
2.0
Normalised RDS(ON) = f(Tj)
a
4
3.5
VGS / V =
0.8
1.5
4.5
0.6
5
1.0
7
0.4
10
0.5
0.2
0
0
0
2
4
6
8
10 12
ID / A
14
16
18
-60 -40 -20
20
Fig.6. Typical on-state resistance, Tj = 25 ˚C.
RDS(ON) = f(ID); parameter VGS
20
ID / A
25
20
40 60
Tj / C
80
100 120 140
Fig.9. Normalised drain-source on-state resistance.
a = RDS(ON)/RDS(ON)25 ˚C = f(Tj); ID = 5.5 A; VGS = 5 V
VGS(TO) / V
BUK552-100A
Tj / C =
0
max.
150
2
15
typ.
10
min.
1
5
0
0
0
2
4
VGS / V
6
-60
8
-20
0
20
40
60
Tj / C
80
100
120
140
Fig.10. Gate threshold voltage.
VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS
Fig.7. Typical transfer characteristics.
ID = f(VGS) ; conditions: VDS = 25 V; parameter Tj
April 1993
-40
4
Rev 1.100
Philips Semiconductors
Product Specification
PowerMOS transistor
Logic level FET
SUB-THRESHOLD CONDUCTION
ID / A
1E-01
BUK542-100A/B
IF / A
20
BUK552-100A
1E-02
15
2%
1E-03
98 %
typ
10
1E-04
Tj / C = 150
5
1E-05
1E-06
0
0
0.4
0.8
1.2
VGS / V
1.6
2
0
2.4
Fig.11. Sub-threshold drain current.
ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS
10000
25
C / pF
1
VSDS / V
2
Fig.14. Typical reverse diode current.
IF = f(VSDS); conditions: VGS = 0 V; parameter Tj
BUK5y2-100
120
110
WDSS%
100
90
80
1000
70
Ciss
60
50
40
100
Coss
30
20
Crss
10
0
10
0
20
20
40
40
VDS / V
Fig.12. Typical capacitances, Ciss, Coss, Crss.
C = f(VDS); conditions: VGS = 0 V; f = 1 MHz
12
60
80
100
Ths / C
120
140
Fig.15. Normalised avalanche energy rating.
WDSS% = f(Ths); conditions: ID = 10 A
BUK552-100
VGS / V
VDD
+
VDS / V =20
10
L
8
VDS
80
-
VGS
6
-ID/100
T.U.T.
0
4
2
RGS
R 01
shunt
0
0
2
4
6
8
10
QG / nC
12
14
16
Fig.16. Avalanche energy test circuit.
WDSS = 0.5 ⋅ LID2 ⋅ BVDSS /(BVDSS − VDD )
Fig.13. Typical turn-on gate-charge characteristics.
VGS = f(QG); conditions: ID = 10 A; parameter VDS
April 1993
5
Rev 1.100
Philips Semiconductors
Product Specification
PowerMOS transistor
Logic level FET
BUK542-100A/B
MECHANICAL DATA
Dimensions in mm
10.2
max
5.7
max
3.2
3.0
Net Mass: 2 g
4.4
max
0.9
0.5
2.9 max
4.4
4.0
7.9
7.5
17
max
seating
plane
3.5 max
not tinned
4.4
13.5
min
1
0.4
2
3
0.9
0.7
M
0.55 max
2.54
1.3
5.08
top view
Fig.17. SOT186; The seating plane is electrically isolated from all terminals.
Notes
1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent
damage to MOS gate oxide.
2. Refer to mounting instructions for F-pack envelopes.
3. Epoxy meets UL94 V0 at 1/8".
April 1993
6
Rev 1.100
Philips Semiconductors
Product Specification
PowerMOS transistor
Logic level FET
BUK542-100A/B
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
 Philips Electronics N.V. 1996
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.
The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.
April 1993
7
Rev 1.100
Error Log
542-100.A&B
1) Level: Format Error
Message: Page break required with Keep enabled
Location: Document Body
Page E1
96-11-11 04:03 pm
Similar pages