PHILIPS BUK553-60A Powermos transistor logic level fet Datasheet

Philips Semiconductors
Product Specification
PowerMOS transistor
Logic level FET
GENERAL DESCRIPTION
N-channel enhancement mode
logic level field-effect power
transistor in a plastic envelope.
The device is intended for use in
Switched Mode Power Supplies
(SMPS), motor control, welding,
DC/DC and AC/DC converters, and
in automotive and general purpose
switching applications.
PINNING - TO220AB
PIN
QUICK REFERENCE DATA
SYMBOL
PARAMETER
MAX.
MAX.
UNIT
VDS
ID
Ptot
Tj
RDS(ON)
BUK553
Drain-source voltage
Drain current (DC)
Total power dissipation
Junction temperature
Drain-source on-state
resistance;
VGS = 5 V
-60A
60
21
75
175
0.085
-60B
60
20
75
175
0.10
V
A
W
˚C
Ω
PIN CONFIGURATION
DESCRIPTION
1
gate
2
drain
3
source
tab
BUK553-60A/B
SYMBOL
d
tab
g
drain
s
1 23
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VDS
VDGR
±VGS
±VGSM
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Non-repetitive gate-source voltage
RGS = 20 kΩ
tp ≤ 50 µs
-
60
60
15
20
V
V
V
V
ID
ID
IDM
Drain current (DC)
Drain current (DC)
Drain current (pulse peak value)
Tmb = 25 ˚C
Tmb = 100 ˚C
Tmb = 25 ˚C
-
Ptot
Tstg
Tj
Total power dissipation
Storage temperature
Junction Temperature
Tmb = 25 ˚C
-
- 55
-
-60A
21
15
84
-60B
20
14
80
A
A
A
75
175
175
W
˚C
˚C
THERMAL RESISTANCES
SYMBOL
PARAMETER
Rth j-mb
Thermal resistance junction to
mounting base
Thermal resistance junction to
ambient
Rth j-a
April 1993
CONDITIONS
1
MIN.
TYP.
MAX.
UNIT
-
-
2.0
K/W
-
60
-
K/W
Rev 1.100
Philips Semiconductors
Product Specification
PowerMOS transistor
Logic level FET
BUK553-60A/B
STATIC CHARACTERISTICS
Tmb = 25 ˚C unless otherwise specified
SYMBOL
PARAMETER
CONDITIONS
V(BR)DSS
Drain-source breakdown
voltage
Gate threshold voltage
Zero gate voltage drain current
Zero gate voltage drain current
Gate source leakage current
Drain-source on-state
resistance
VGS(TO)
IDSS
IDSS
IGSS
RDS(ON)
MIN.
TYP.
MAX.
UNIT
VGS = 0 V; ID = 0.25 mA
60
-
-
V
VDS = VGS; ID = 1 mA
VDS = 60 V; VGS = 0 V; Tj = 25 ˚C
VDS = 60 V; VGS = 0 V; Tj =125 ˚C
VGS = ±15 V; VDS = 0 V
VGS = 5 V;
BUK553-60A
BUK553-60B
ID = 10 A
1.0
-
1.5
1
0.1
10
0.075
0.08
2.0
10
1.0
100
0.085
0.10
V
µA
mA
nA
Ω
Ω
MIN.
TYP.
MAX.
UNIT
DYNAMIC CHARACTERISTICS
Tmb = 25 ˚C unless otherwise specified
SYMBOL
PARAMETER
CONDITIONS
gfs
Forward transconductance
VDS = 25 V; ID = 10 A
7
10
-
S
Ciss
Coss
Crss
Input capacitance
Output capacitance
Feedback capacitance
VGS = 0 V; VDS = 25 V; f = 1 MHz
-
700
240
130
825
350
160
pF
pF
pF
td on
tr
td off
tf
Turn-on delay time
Turn-on rise time
Turn-off delay time
Turn-off fall time
VDD = 30 V; ID = 3 A;
VGS = 5 V; RGS = 50 Ω;
Rgen = 50 Ω
-
20
95
80
65
30
120
110
85
ns
ns
ns
ns
Ld
Internal drain inductance
-
3.5
-
nH
Ld
Internal drain inductance
-
4.5
-
nH
Ls
Internal source inductance
Measured from contact screw on
tab to centre of die
Measured from drain lead 6 mm
from package to centre of die
Measured from source lead 6 mm
from package to source bond pad
-
7.5
-
nH
MIN.
TYP.
MAX.
UNIT
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
Tmb = 25 ˚C unless otherwise specified
SYMBOL
PARAMETER
CONDITIONS
IDR
-
-
-
21
A
IDRM
VSD
Continuous reverse drain
current
Pulsed reverse drain current
Diode forward voltage
IF = 21 A ; VGS = 0 V
-
1.3
84
1.7
A
V
trr
Qrr
Reverse recovery time
Reverse recovery charge
IF = 21 A; -dIF/dt = 100 A/µs;
VGS = 0 V; VR = 30 V
-
60
0.25
-
ns
µC
MIN.
TYP.
MAX.
UNIT
-
-
45
mJ
AVALANCHE LIMITING VALUE
Tmb = 25 ˚C unless otherwise specified
SYMBOL
PARAMETER
CONDITIONS
WDSS
Drain-source non-repetitive
unclamped inductive turn-off
energy
ID = 20 A ; VDD ≤ 25 V ;
VGS = 5 V ; RGS = 50 Ω
April 1993
2
Rev 1.100
Philips Semiconductors
Product Specification
PowerMOS transistor
Logic level FET
Normalised Power Derating
PD%
120
BUK553-60A/B
1E+01
ZTHX53
Zth j-mb / (K/W)
110
100
90
80
1E+00
0.5
70
0.2
60
50
0.1
40
0.05
1E-01
30
tp
PD
0.02
D=
20
10
0
0
0
20
40
60
80 100
Tmb / C
120
140
160
180
Fig.1. Normalised power dissipation.
PD% = 100⋅PD/PD 25 ˚C = f(Tmb)
120
1E-05
1E-03
t/s
1E-01
1E+01
Fig.4. Transient thermal impedance.
Zth j-mb = f(t); parameter D = tp/T
Normalised Current Derating
ID%
t
T
1E-02
1E-07
tp
T
40
BUK553-50A
ID / A
10
110
7
100
VGS / V =
90
30
5
80
70
60
20
4
50
40
30
10
3
20
10
0
0
20
40
60
80 100
Tmb / C
120
140
160
0
180
2
4
6
8
10
VDS / V
Fig.2. Normalised continuous drain current.
ID% = 100⋅ID/ID 25 ˚C = f(Tmb); conditions: VGS ≥ 5 V
1000
0
Fig.5. Typical output characteristics, Tj = 25 ˚C.
ID = f(VDS); parameter VGS
BUK553-60
ID / A
0.5
RDS(ON) / Ohm
BUK553-50A
VGS / V =
2.5
0.4
ID
S/
100
=
N)
VD
3.5
4
A
4.5
5
0.3
B
tp = 10 us
O
S(
3
RD
10
DC
100 us
0.2
1 ms
0.1
7
10 ms
100 ms
1
1
10
0
10
100
VDS / V
Fig.3. Safe operating area. Tmb = 25 ˚C
ID & IDM = f(VDS); IDM single pulse; parameter tp
April 1993
0
10
20
ID / A
30
40
Fig.6. Typical on-state resistance, Tj = 25 ˚C.
RDS(ON) = f(ID); parameter VGS
3
Rev 1.100
Philips Semiconductors
Product Specification
PowerMOS transistor
Logic level FET
40
BUK553-60A/B
ID / A
VGS(TO) / V
BUK553-50A
Tj / C =
max.
2
150
25
30
typ.
20
min.
1
10
0
0
0
2
4
VGS / V
6
8
-60
gfs / S
20
60
Tj / C
100
140
180
Fig.10. Gate threshold voltage.
VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS
Fig.7. Typical transfer characteristics.
ID = f(VGS) ; conditions: VDS = 25 V; parameter Tj
10
-20
BUK 553-50A
SUB-THRESHOLD CONDUCTION
ID / A
1E-01
9
1E-02
8
7
2%
1E-03
6
98 %
typ
5
1E-04
4
3
1E-05
2
1
0
1E-06
0
10
20
ID / A
30
40
0
Fig.8. Typical transconductance, Tj = 25 ˚C.
gfs = f(ID); conditions: VDS = 25 V
2.0
a
0.4
0.8
1.2
VGS / V
1.6
2
2.4
Fig.11. Sub-threshold drain current.
ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS
Normalised RDS(ON) = f(Tj)
10000
C / pF
BUK5y3-50
1.5
1000
Ciss
1.0
Coss
100
Crss
0.5
10
0
-60
-20
20
60
Tj / C
100
140
180
20
40
VDS / V
Fig.9. Normalised drain-source on-state resistance.
a = RDS(ON)/RDS(ON)25 ˚C = f(Tj); ID = 10 A; VGS = 5 V
April 1993
0
Fig.12. Typical capacitances, Ciss, Coss, Crss.
C = f(VDS); conditions: VGS = 0 V; f = 1 MHz
4
Rev 1.100
Philips Semiconductors
Product Specification
PowerMOS transistor
Logic level FET
12
BUK553-60A/B
BUK553-50
VGS / V
120
WDSS%
110
100
10
90
VDS / V =10
8
80
40
70
60
6
50
40
4
30
20
2
10
0
0
0
2
4
6
8
10 12
QG / nC
14
16
18
20
20
Fig.13. Typical turn-on gate-charge characteristics.
VGS = f(QG); conditions: ID = 20 A; parameter VDS
50
IF / A
40
60
80
100
120
Tmb / C
140
160
180
Fig.15. Normalised avalanche energy rating.
WDSS% = f(Tmb); conditions: ID = 20 A
BUK553-50A
VDD
+
L
40
VDS
30
-
VGS
-ID/100
20
Tj / C = 150
T.U.T.
0
25
10
RGS
R 01
shunt
0
0
1
VSDS / V
2
Fig.16. Avalanche energy test circuit.
WDSS = 0.5 ⋅ LID2 ⋅ BVDSS /(BVDSS − VDD )
Fig.14. Typical reverse diode current.
IF = f(VSDS); conditions: VGS = 0 V; parameter Tj
April 1993
5
Rev 1.100
Philips Semiconductors
Product Specification
PowerMOS transistor
Logic level FET
BUK553-60A/B
MECHANICAL DATA
Dimensions in mm
4,5
max
Net Mass: 2 g
10,3
max
1,3
3,7
2,8
5,9
min
15,8
max
3,0 max
not tinned
3,0
13,5
min
1,3
max 1 2 3
(2x)
0,9 max (3x)
2,54 2,54
0,6
2,4
Fig.17. TO220AB; pin 2 connected to mounting base.
Notes
1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent
damage to MOS gate oxide.
2. Refer to mounting instructions for TO220 envelopes.
3. Epoxy meets UL94 V0 at 1/8".
April 1993
6
Rev 1.100
Philips Semiconductors
Product Specification
PowerMOS transistor
Logic level FET
BUK553-60A/B
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
 Philips Electronics N.V. 1996
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.
The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.
April 1993
7
Rev 1.100
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