TI1 CAHCT125QPWRG4Q1 Quadruple bus buffer gate with 3-state output Datasheet

SN74AHCT125-Q1
QUADRUPLE BUS BUFFER GATE
WITH 3-STATE OUTPUTS
SCLS508A − JUNE 2003 − REVISED FEBRUARY 2008
D Qualified for Automotive Applications
D ESD Protection Exceeds 2000 V Per
D
D OR PW PACKAGE
(TOP VIEW)
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Inputs Are TTL-Voltage Compatible
1OE
1A
1Y
2OE
2A
2Y
GND
description/ordering information
The SN74AHCT125 is a quadruple bus buffer gate
featuring independent line drivers with 3-state
outputs. Each output is disabled when the associated
output-enable (OE) input is high. When OE is low, the
respective gate passes the data from the A input to
its Y output.
1
14
2
13
3
12
4
11
5
10
6
9
7
8
VCC
4OE
4A
4Y
3OE
3A
3Y
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION†
−40°C
40°C to 125°C
ORDERABLE
PART NUMBER
PACKAGE‡
TA
TOP-SIDE
MARKING
SOIC − D
Tape and reel
SN74AHCT125QDRQ1
AHCT125Q
TSSOP − PW
Tape and reel
SN74AHCT125QPWRQ1
HB125Q
†
For the most current package and ordering information, see the Package Option Addendum at the end of this
document, or see the TI web site at http://www.ti.com.
‡ Package drawings, thermal data, and symbolization are available at http://www.ti.com/packaging.
FUNCTION TABLE
(each buffer)
INPUTS
OE
A
OUTPUT
Y
L
H
H
L
L
L
H
X
Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright © 2008, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
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1
SN74AHCT125-Q1
QUADRUPLE BUS BUFFER GATE
WITH 3-STATE OUTPUTS
SCLS508A − JUNE 2003 − REVISED FEBRUARY 2008
logic diagram (positive logic)
1
1OE
1A
2OE
2A
2
3
1Y
4
5
6
2Y
10
3OE
3A
8
9
3Y
13
4OE
4A
12
11
4Y
Pin numbers shown are for the D and PW packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AHCT125-Q1
QUADRUPLE BUS BUFFER GATE
WITH 3-STATE OUTPUTS
SCLS508A − JUNE 2003 − REVISED FEBRUARY 2008
recommended operating conditions (see Note 3)
MIN
MAX
4.5
5.5
UNIT
VCC
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
VI
Input voltage
VO
Output voltage
IOH
High-level output current
−8
IOL
Low-level output current
8
mA
Δt/Δv
Input transition rise or fall rate
20
ns/V
TA
Operating free-air temperature
125
°C
2
V
V
0.8
V
0
5.5
V
0
VCC
V
−40
mA
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VOH
VOL
†
TEST CONDITIONS
VCC
IOH = −50 mA
45V
4.5
IOH = −8 mA
IOL = 50 mA
TA = 25°C
MIN
TYP
4.4
4.5
MIN
MAX
UNIT
4.4
3.94
V
3.8
45V
4.5
IOL = 8 mA
MAX
0.1
0.1
0.36
0.44
V
II
VI = 5.5 V or GND
0 V to 5.5 V
±0.1
±1
mA
IOZ
VO = VCC or GND
5.5 V
±0.25
±2.5
mA
ICC
VI = VCC or GND,
5.5 V
2
20
mA
ΔICC†
One input at 3.4 V,
Other inputs at VCC or GND
5.5 V
1.35
1.5
mA
Ci
VI = VCC or GND
5V
4
10
10
pF
Co
VO = VCC or GND
5V
15
IO = 0
pF
This is the increase in supply current for each input at one of the specified TTL voltage levels rather than 0 V or VCC.
POST OFFICE BOX 655303
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3
SN74AHCT125-Q1
QUADRUPLE BUS BUFFER GATE
WITH 3-STATE OUTPUTS
SCLS508A − JUNE 2003 − REVISED FEBRUARY 2008
switching characteristics over recommended operating free-air temperature range,
VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
A
Y
CL = 15 pF
OE
Y
CL = 15 pF
OE
Y
CL = 15 pF
A
Y
CL = 50 pF
OE
Y
CL = 50 pF
OE
Y
CL = 50 pF
tsk(o)
TA = 25°C
MIN
MIN
MAX
5.5
1
6.5
5.5
1
6.5
3.6
5.1
1
6
3.6
5.1
1
6
4.6
6.8
1
8
4.6
6.8
1
8
5.3
7.5
1
8.5
5.3
7.5
1
8.5
5.1
7.1
1
8
5.1
7.1
1
8
6.1
8.8
1
10
6.1
8.8
1
10
TYP
MAX
3.8
3.8
CL = 50 pF
1
1
UNIT
ns
ns
ns
ns
ns
ns
ns
noise characteristics, VCC = 5 V, CL = 50 pF, TA = 25°C (see Note 4)
PARAMETER
VOL(P)
Quiet output, maximum dynamic VOL
VOL(V)
Quiet output, minimum dynamic VOL
VOH(V)
Quiet output, minimum dynamic VOH
VIH(D)
High-level dynamic input voltage
VIL(D)
Low-level dynamic input voltage
MIN
MAX
UNIT
0.8
V
−0.8
V
4.4
V
2
V
0.8
V
TYP
UNIT
NOTE 4: Characteristics are for surface-mount packages only.
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER
Cpd
4
TEST CONDITIONS
Power dissipation capacitance
No load,
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
f = 1 MHz
14
pF
SN74AHCT125-Q1
QUADRUPLE BUS BUFFER GATE
WITH 3-STATE OUTPUTS
SCLS508A − JUNE 2003 − REVISED FEBRUARY 2008
PARAMETER MEASUREMENT INFORMATION
VCC
From Output
Under Test
RL = 1 kΩ
From Output
Under Test
Test
Point
S1
Open
TEST
GND
CL
(see Note A)
CL
(see Note A)
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain
Open
VCC
GND
VCC
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
3V
1.5 V
Timing Input
0V
tw
3V
1.5 V
Input
1.5 V
th
tsu
3V
1.5 V
Data Input
1.5 V
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3V
1.5 V
Input
1.5 V
0V
tPLH
tPHL
VOH
In-Phase
Output
50% VCC
tPHL
Out-of-Phase
Output
50% VCC
VOL
3V
Output
Control
Output
Waveform 1
S1 at VCC
(see Note B)
1.5 V
0V
tPZL
50% VCC
tPLZ
≈VCC
50% VCC
tPZH
tPLH
VOH
50% VCC
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
1.5 V
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.3 V
VOL
tPHZ
50% VCC
VOH − 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
E. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
PACKAGE OPTION ADDENDUM
www.ti.com
17-Aug-2011
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
CAHCT125QPWRG4Q1
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
SN74AHCT125QDRG4Q1
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
SN74AHCT125QDRQ1
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
SN74AHCT125QPWRQ1
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
(3)
Samples
(Requires Login)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74AHCT125-Q1 :
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
17-Aug-2011
• Catalog: SN74AHCT125
• Enhanced Product: SN74AHCT125-EP
• Military: SN54AHCT125
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Enhanced Product - Supports Defense, Aerospace and Medical Applications
• Military - QML certified for Military and Defense Applications
Addendum-Page 2
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