Catalyst CAT1024WI-30TE13 Supervisory circuits with i2c serial 2k-bit cmos eeprom and manual reset Datasheet

Preliminary Information
H
EE
GEN FR
ALO
CAT1024, CAT1025
Supervisory Circuits with I2C Serial 2k-bit CMOS EEPROM and Manual Reset
FEATURES
LE
A D F R E ETM
■ 16-Byte page write buffer
■ Precision power supply voltage monitor
■ Built-in inadvertent write protection
— 5V, 3.3V and 3V systems
— WP pin (CAT1025)
— Five threshold voltage options
■ 1,000,000 Program/Erase cycles
■ Active high or low reset
■ Manual reset input
— Valid reset guaranteed at VCC = 1V
■ 100 year data retention
■ 400kHz I2C bus
■ 8-pin DIP, SOIC, TSSOP, MSOP &
■ 3.0V to 5.5V operation
TDFN (3x3mm foot print) packages
■ Low power CMOS technology
■ Industrial and extended temperature ranges
DESCRIPTION
voltages support 5V, 3.3V and 3V systems. If power supply
voltages are out of tolerance reset signals become active,
preventing the system microcontroller, ASIC or peripherals
from operating. Reset signals become inactive typically 200
ms after the supply voltage exceeds the reset threshold
level. With both active high and low reset signals, interface
to microcontrollers and other ICs is simple. In addition, the
The CAT1025 provides a precision VCC sense circuit RESET pin or a separate input, MR, can be used as an input
and two open drain outputs: one (RESET) drives high for push-button manual reset capability.
and the other (RESET) drives low whenever VCC falls
below the reset threshold voltage. The CAT1025 also The CAT1024/25 memory features a 16-byte page. In
has a Write Protect input (WP). Write operations are addition, hardware data protection is provided by a VCC
sense circuit that prevents writes to memory whenever VCC
disabled if WP is connected to a logic high.
falls below the reset threshold or until VCC reaches the reset
The CAT1024 also provides a precision VCC sense threshold during power up.
circuit, but has only a RESET output and does not have
Available packages include an 8-pin DIP, 8-pin SOIC, 8-pin
a Write Protect input.
TSSOP, 8-pin TDFN and 8-pin MSOP. The TDFN package
The power supply monitor and reset circuit protect thickness is 0.8mm maximum. TDFN footprint is 3x3mm.
memory and system controllers during power up/down
and against brownout conditions. Five reset threshold
The CAT1024 and CAT1025 are complete memory and
supervisory solutions for microcontroller-based systems.
A 2k-bit serial EEPROM memory and a system power
supervisor with brown-out protection are integrated
together in low power CMOS technology. Memory
interface is via a 400kHz I2C bus.
PIN CONFIGURATION
DIP Package (P, L)
SOIC Package (J, W)
TSSOP Package (U, Y)
MSOP Package (R, Z)
(Bottom View)
TDFN Package: 3mm x 3mm
0.8mm maximum height - (RD4, ZD4)
8 VCC
7 NC
VCC
8
1
MR
NC
7
2
RESET
6 SCL
SCL
6
3
NC
VSS 4
5 SDA
SDA
5
4
VSS
MR 1
8 VCC
7 WP
VCC 8
6 SCL
SCL 6
5 SDA
SDA 5
MR 1
RESET 2
CAT1024
NC 3
RESET 2
RESET 3
VSS 4
CAT1025
© 2004 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT1024
1 MR
WP 7
2 RESET
CAT1025
3 RESET
4 V
SS
Doc No. 3008, Rev. M
CAT1024, CAT1025
Threshold Voltage Options
BLOCK DIAGRAM — CAT1024, CAT1025
Part Dash Minimum
Number Threshold
EXTERNAL LOAD
SENSE AMPS
SHIFT REGISTERS
DOUT
ACK
VCC
WORD ADDRESS
BUFFERS
VSS
SDA
COLUMN
DECODERS
START/STOP
LOGIC
-45
4.50
4.75
-42
4.25
4.50
-30
3.00
3.15
-28
2.85
3.00
-25
2.55
2.70
2kbit
EEPROM
XDEC
WP*
Maximum
Threshold
CONTROL
LOGIC
DATA IN STORAGE
HIGH VOLTAGE/
TIMING CONTROL
RESET Controller
Precision
MR
Vcc Monitor
* RESET
STATE COUNTERS
SCL
SLAVE
ADDRESS
COMPARATORS
RESET
*CAT1025 Only
PIN FUNCTIONS
OPERATING TEMPERATURE RANGE
Pin Name
Function
Industrial
-40˚C to 85˚C
NC
No Connect
Extended
-40˚C to 125˚C
RESET
Active Low Reset Input/Output
VSS
Ground
SDA
Serial Data/Address
SCL
Clock Input
RESET
Active High Reset Output (CAT1025 only)
VCC
Power Supply
WP
Write Protect (CAT1025 only)
MR
Manual Reset Input
Doc. No. 3008, Rev. M
2
CAT1024, CAT1025
PIN DESCRIPTION
RESET/RESET
RESET: RESET OUTPUTS
RESET
(RESET CAT1025 Only)
These are open drain pins and RESET can be used as a
manual reset trigger input. By forcing a reset condition on
the pin the device will initiate and maintain a reset condition.
The RESET pin must be connected through a pull-down
resistor, and the RESET pin must be connected through a
pull-up resistor.
SDA: SERIAL DATA ADDRESS
The bidirectional serial data/address pin is used to transfer
all data into and out of the device. The SDA pin is an open
drain output and can be wire-ORed with other open drain
or open collector outputs.
MR:
MANUAL RESET INPUT
Manual Reset input is a debounced input that can be
connected to an external source for Manual Reset.
Pulling the MR input low will generate a Reset condition.
Reset outputs are active while MR input is low and for
the reset timeout period after MR returns to high. The
input has an internal pull-up resistor.
WP (CAT1025 Only): WRITE PROTECT INPUT
When tied to VSS or left unconnected write operations
to the entire array are allowed. When tied to VCC, the
entire array is protected. This input has an internal pull
down resistor.
SCL: SERIAL CLOCK
Serial clock input.
CAT10XX FAMILY OVERVIEW
Device
Manual
Reset
Input Pin
Watchdog
Watchdog
Monitor
Pin
Write
Protection
Pin
Independent
Auxiliary
Voltage Sense
RESET: Active
High and LOW
EEPROM
CAT1021
SDA
2k
CAT1022
SDA
2k
CAT1023
WDI
2k
CAT1024
2k
CAT1025
2k
CAT1026
2k
CAT1027
WDI
2k
For supervisory circuits with embedded 16k EEPROM, please refer to the CAT1161, CAT1162 and CAT1163
data sheets.
3
Doc No. 3008, Rev. M
CAT1024, CAT1025
ABSOLUTE MAXIMUM RATINGS
Stresses above those listed under “Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions
outside of those listed in the operational sections of this specification
is not implied. Exposure to any absolute maximum rating for extended
periods may affect device performance and reliability.
Temperature Under Bias ................. –55°C to +125°C
Storage Temperature ....................... –65°C to +150°C
Voltage on any Pin with
Respect to Ground(1) ............ –2.0V to +VCC +2.0V
Note:
(1) The minimum DC input voltage is –0.5V. During transitions,
inputs may undershoot to –2.0V for periods of less than 20 ns.
Maximum DC voltage on output pins is VCC +0.5V, which may
overshoot to VCC +2.0V for periods of less than 20 ns.
(2) Output shorted for no more than one second. No more than
one output shorted at a time.
VCC with Respect to Ground ............... –2.0V to +7.0V
Package Power Dissipation
Capability (TA = 25°C) ................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(2) ........................ 100 mA
D.C. OPERATING CHARACTERISTICS
VCC = +3.0V to +5.5V and over the recommended temperature conditions unless otherwise specified.
Symbol
Parameter
Test Conditions
Min
ILI
Input Leakage Current
VIN = GND to Vcc
ILO
Output Leakage Current
VIN = GND to Vcc
ICC1
Power Supply Current (Write)
ICC2
Max
Units
-2
10
µA
-10
10
µA
fSCL = 400kHz
VCC = 5.5V
3
mA
Power Supply Current (Read)
fSCL = 400kHz
VCC = 5.5V
1
mA
ISB
Standby Current
Vcc = 5.5V,
VIN = GND or Vcc
40
µA
VIL(1)
Input Low Voltage
-0.5
0.3 x Vcc
V
VIH(1)
Input High Voltage
0.7 x Vcc
Vcc + 0.5
V
VOL
Output Low Voltage
(SDA, RESET)
IOL = 3mA
VCC = 2.7V
0.4
V
VOH
Output High Voltage
(RESET)
IOH = -0.4mA
VCC = 2.7V
Vcc 0.75
CAT102x-45
(VCC = 5V)
4.50
4.75
CAT102x-42
(VCC = 5V)
4.25
4.50
CAT102x-30
(VCC = 3.3V)
3.00
3.15
CAT102x-28
(VCC = 3.3V)
2.85
3.00
CAT102x-25
(VCC = 3V)
2.55
2.70
Reset Threshold
VTH
Typ
V
V
VRVALID
Reset Output Valid VCC Voltage
1.00
V
VRT(2)
Reset Threshold Hysteresis
15
mV
Notes:
1. VIL min and VIH max are reference values only and are not tested.
2. This parameter is tested initially and after a design or process change that affects the parameter. Not 100% tested.
Doc. No. 3008, Rev. M
4
CAT1024, CAT1025
CAPACITANCE
TA = 25°C, f = 1.0 MHz, VCC = 5V
Symbol
COUT
(1)
Test
Test Conditions
Max
Units
VOUT = 0V
8
pF
VIN = 0V
6
pF
Output Capacitance
CIN(1)
Input Capacitance
AC CHARACTERISTICS
VCC = 3.0V to 5.5V and over the recommended temperature conditions, unless otherwise specified.
Memory Read & Write Cycle2
Symbol
Parameter
fSCL
Max
Units
Clock Frequency
400
kHz
tSP
Input Filter Spike
Suppression (SDA, SCL)
100
ns
tLOW
Clock Low Period
1.3
µs
tHIGH
Clock High Period
0.6
µs
tR(1)
SDA and SCL Rise Time
300
ns
SDA and SCL Fall Time
300
ns
(1)
tF
Min
tHD;STA
Start Condition Hold Time
0.6
µs
tSU;STA
Start Condition Setup Time
(for a Repeated Start)
0.6
µs
tHD;DAT
Data Input Hold Time
0
ns
tSU;DAT
Data Input Setup Time
100
ns
tSU;STO
Stop Condition Setup Time
0.6
µs
tAA
SCL Low to Data Out Valid
tDH
Data Out Hold Time
50
ns
tBUF(1)
Time the Bus must be Free Before a
New Transmission Can Start
1.3
µs
tWC(3)
Write Cycle Time (Byte or Page)
900
5
ns
ms
Notes:
1. This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.
2. Test Conditions according to “AC Test Conditions” table.
3. The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write
cycle, the bus interface circuits are disabled, SDA is allowed to remain high and the device does not respond to its slave address.
5
Doc No. 3008, Rev. M
CAT1024, CAT1025
RESET CIRCUIT AC CHARACTERISTICS
Symbol
Parameter
Test
Conditions
Min
Typ
Max
Units
tPURST
Reset Timeout
Note 2
130
200
270
ms
tRPD
VTH to RESET Output Delay
Note 3
5
µs
tGLITCH
VCC Glitch Reject Pulse Width
Note 4, 5
30
ns
MR Glitch
Manual Reset Glitch Immunity
Note 1
100
ns
tMRW
MR Pulse Width
Note 1
tMRD
MR Input to RESET Output Delay
Note 1
5
µs
1
µs
Max
Units
POWER-UP TIMING5,6
Test
Conditions
Symbol
Parameter
Min
Typ
tPUR
Power-Up to Read Operation
270
ms
tPUW
Power-Up to Write Operation
270
ms
AC TEST CONDITIONS
Parameter
Test Conditions
Input Pulse Voltages
0.2VCC to 0.8VCC
Input Rise and Fall Times
10 ns
Input Reference Voltages
0.3VCC, 0.7VCC
Output Reference Voltages
0.5VCC
Output Load
Current Source: IOL = 3mA;
CL = 100pF
RELIABILITY CHARACTERISTICS
Symbol
Parameter
NEND(5)
Endurance
MIL-STD-883, Test Method 1033 1,000,000
Data Retention
MIL-STD-883, Test Method 1008
100
Years
VZAP(5)
ESD Susceptibility
MIL-STD-883, Test Method 3015
2000
Volts
ILTH(5)(7)
Latch-Up
JEDEC Standard 17
100
mA
TDR
(5)
Reference Test Method
Min
Max
Units
Cycles/Byte
Notes:
1. Test Conditions according to “AC Test Conditions” table.
2. Power-up, Input Reference Voltage VCC = VTH, Reset Output Reference Voltage and Load according to “AC Test Conditions” Table
3. Power-Down, Input Reference Voltage VCC = VTH, Reset Output Reference Voltage and Load according to “AC Test Conditions” Table
4. VCC Glitch Reference Voltage = VTHmin; Based on characterization data
5. This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.
6. tPUR and tPUW are the delays required from the time VCC is stable until the specified memory operation can be initiated.
7. Latch-up protection is provided for stresses up to 100mA on input and output pins from -1V to VCC + 1V.
Doc. No. 3008, Rev. M
6
CAT1024, CAT1025
DEVICE OPERATION
Reset Controller Description
The CAT1024/25 precision RESET controllers ensure
correct system operation during brownout and power
up/down conditions. They are configured with open
drain RESET outputs.
including write operations. If the Reset output(s) are
active, in progress communications to the EEPROM are
aborted and no new communications are allowed. In this
condition an internal write cycle to the memory can not be
started, but an in progress internal non-volatile memory
write cycle can not be aborted. An internal write cycle
initiated before the Reset condition can be successfully
finished if there is enough time (5ms) before VCC reaches
the minimum value of 2V.
During power-up, the RESET outputs remain active
until VCC reaches the VTH threshold and will continue
driving the outputs for approximately 200ms (tPURST)
after reaching VTH. After the tPURST timeout interval, the
device will cease to drive the reset outputs. At this point
the reset outputs will be pulled up or down by their
respective pull up/down resistors.
In addition, the CAT1025 includes a Write Protection Input
which when tied to VCC will disable any write operations
to the device.
During power-down, the RESET outputs will be active
when VCC falls below VTH. The RESET output will be
valid so long as VCC is >1.0V (VRVALID). The device is
designed to ignore the fast negative going VCC transient
pulses (glitches).
Reset output timing is shown in Figure 1.
Manual Reset Operation
The RESET pin can operate as reset output and manual
reset input. The input is edge triggered; that is, the
RESET input will initiate a reset timeout after detecting
a high to low transition.
When RESET I/O is driven to the active state, the 200
msec timer will begin to time the reset interval. If external
reset is shorter than 200 ms, Reset outputs will remain
active at least 200 ms.
CAT1024/25 also have a separate manual reset input.
Driving the MR input low by connecting a pushbutton
(normally open) from MR pin to GND will generate a
reset condition. The input has a internal pull up resistor.
Reset remains asserted while MR is low and for the
Reset Timeout period after MR input has gone high.
Glitches shorter than 100 ns on MR input will not
generate a reset pulse. No external debouncing circuits
are required. Manual reset operation using MR input is
shown in Figure 2.
Hardware Data Protection
The CAT1024/25 family has been designed to solve
many of the data corruption issues that have long been
associated with serial EEPROMs. Data corruption occurs
when incorrect data is stored in a memory location which
is assumed to hold correct data.
Whenever the device is in a Reset condition, the
embedded EEPROM is disabled for all operations,
7
Doc No. 3008, Rev. M
CAT1024, CAT1025
t
Figure 1. RESET Output Timing
GLITCH
VTH
VRVALID
t PURST
VCC
t RPD
t PURST
RESET
RESET
Figure 2. MR Operation and Timing
t MRW
MR
t MRD
t PURST
RESET
RESET
Doc. No. 3008, Rev. M
8
t RPD
CAT1024, CAT1025
EMBEDDED EEPROM OPERATION
SDA when SCL is HIGH. The CAT1024/25 monitors the
SDA and SCL lines and will not respond until this
condition is met.
The CAT1024 and CAT1025 feature a 2kbit embedded
serial EEPROM that supports the I 2C Bus data
transmission protocol. This Inter-Integrated Circuit Bus
protocol defines any device that sends data to the bus to
be a transmitter and any device receiving data to be a
receiver. The transfer is controlled by the Master device
which generates the serial clock and all START and
STOP conditions for bus access. Both the Master device
and Slave device can operate as either transmitter or
receiver, but the Master device controls which mode is
activated.
STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must end
with a STOP condition.
DEVICE ADDRESSING
The Master begins a transmission by sending a START
condition. The Master sends the address of the particular
slave device it is requesting. The four most significant
bits of the 8-bit slave address are programmable in metal
and the default is 1010.
I2C Bus Protocol
The features of the I2C bus protocol are defined as
follows:
(1) Data transfer may be initiated only when the bus is
not busy.
The last bit of the slave address specifies whether a
Read or Write operation is to be performed. When this bit
is set to 1, a Read operation is selected, and when set
to 0, a Write operation is selected.
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any changes in
the data line while the clock line is high will be interpreted
as a START or STOP condition.
After the Master sends a START condition and the slave
address byte, the CAT1024/25 monitors the bus and
responds with an acknowledge (on the SDA line) when
its address matches the transmitted slave address. The
CAT1024/25 then performs a Read or Write operation
depending on the R/W bit.
START Condition
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
Figure 3. Bus Timing
tF
tHIGH
tLOW
tR
tLOW
SCL
tSU:STA
tHD:STA
tHD:DAT
tSU:DAT
tSU:STO
SDA IN
tAA
tBUF
tDH
SDA OUT
Figure 4. Write Cycle Timing
SCL
SDA
8TH BIT
BYTE n
ACK
tWR
STOP
CONDITION
9
START
CONDITION
ADDRESS
Doc No. 3008, Rev. M
CAT1024, CAT1025
ACKNOWLEDGE
WRITE OPERATIONS
After a successful data transfer, each receiving device
is required to generate an acknowledge. The
acknowledging device pulls down the SDA line during
the ninth clock cycle, signaling that it received the 8 bits
of data.
Byte Write
In the Byte Write mode, the Master device sends the
START condition and the slave address information (with
the R/W bit set to zero) to the Slave device. After the Slave
generates an acknowledge, the Master sends a 8-bit
address that is to be written into the address pointers of
the device. After receiving another acknowledge from the
Slave, the Master device transmits the data to be written
into the addressed memory location. The CAT1024/25
acknowledges once more and the Master generates the
STOP condition. At this time, the device begins an
internal programming cycle to non-volatile memory. While
the cycle is in progress, the device will not respond to any
request from the Master device.
The CAT1024/25 responds with an acknowledge after
receiving a START condition and its slave address. If the
device has been selected along with a write operation,
it responds with an acknowledge after receiving each 8bit byte.
When the CAT1024/25 begins a READ mode it transmits
8 bits of data, releases the SDA line and monitors the
line for an acknowledge. Once it receives this
acknowledge, the CAT1024/25 will continue to transmit
data. If no acknowledge is sent by the Master, the device
terminates data transmission and waits for a STOP
condition.
Figure 5. Start/Stop Timing
SDA
SCL
START BIT
STOP BIT
Figure 6. Acknowledge Timing
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
ACKNOWLEDGE
START
Figure 7. Slave Address Bits
Default Configuration
CAT
Doc. No. 3008, Rev. M
1
0
1
0
0
0
10
0
R/W
CAT1024, CAT1025
Page Write
The CAT1024/25 writes up to 16 bytes of data in a single
write cycle, using the Page Write operation. The page
write operation is initiated in the same manner as the byte
write operation, however instead of terminating after the
initial byte is transmitted, the Master is allowed to send up
to 15 additional bytes. After each byte has been
transmitted, the CAT1024/25 will respond with an
acknowledge and internally increment the lower order
address bits by one. The high order bits remain
unchanged.
If the Master transmits more than 16 bytes before sending
the STOP condition, the address counter ‘wraps around,’
and previously transmitted data will be overwritten.
When all 16 bytes are received, and the STOP condition
has been sent by the Master, the internal programming
cycle begins. At this point, all received data is written to
the CAT1024/25 in a single write cycle.
Figure 8. Byte Write Timing
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
SLAVE
ADDRESS
BYTE
ADDRESS
S
T
O
P
DATA
P
S
A
C
K
A
C
K
A
C
K
Figure 9. Page Write Timing
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
SLAVE
ADDRESS
BYTE
ADDRESS (n)
DATA n
S
T
DATA n+15 O
P
DATA n+1
S
P
A
C
K
A
C
K
A
C
K
11
A
C
K
A
C
K
Doc No. 3008, Rev. M
CAT1024, CAT1025
Acknowledge Polling
memory array is protected and becomes read only. The
CAT1025 will accept both slave and byte addresses,
but the memory location accessed is protected from
programming by the device’s failure to send an
acknowledge after the first byte of data is received.
Disabling of the inputs can be used to take advantage of
the typical write cycle time. Once the stop condition is
issued to indicate the end of the host’s write opration, the
CAT1024/25 initiates the internal write cycle. ACK polling
can be initiated immediately. This involves issuing the
start condition followed by the slave address for a write
operation. If the device is still busy with the write operation,
no ACK will be returned. If a write operation has
completed, an ACK will be returned and the host can
then proceed with the next read or write operation.
Read Operations
The READ operation for the CAT1024/25 is initiated in
the same manner as the write operation with one
exception, that R/W bit is set to one. Three different
READ operations are possible: Immediate/Current
Address READ, Selective/Random READ and
Sequential READ.
WRITE PROTECTION
The Write Protection feature (CAT1025 only) allows the
user to protect against inadvertent memory array
programming. If the WP pin is tied to VCC, the entire
Figure 10. Immediate Address Read Timing
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
S
T
O
P
SLAVE
ADDRESS
S
P
A
C
K
DATA
N
O
A
C
K
SCL
SDA
8
9
8TH BIT
DATA OUT
Doc. No. 3008, Rev. M
NO ACK
12
STOP
CAT1024, CAT1025
Immediate/Current Address Read
Sequential Read
The CAT1024 and CAT1025 address counter contains
the address of the last byte accessed, incremented by
one. In other words, if the last READ or WRITE access
was to address N, the READ immediately following
would access data from address N+1. For N=E=255, the
counter will wrap around to zero and continue to clock
out valid data. After the CAT1024 and CAT1025 receives
its slave address information (with the R/W bit set to
one), it issues an acknowledge, then transmits the 8-bit
byte requested. The master device does not send an
acknowledge, but will generate a STOP condition.
The Sequential READ operation can be initiated by
either the Immediate Address READ or Selective READ
operations. After the CAT1024 and CAT1025 sends the
inital 8-bit byte requested, the Master will responds with
an acknowledge which tells the device it requires more
data. The CAT1024 and CAT1025 will continue to output
an 8-bit byte for each acknowledge, thus sending the
STOP condition.
The data being transmitted from the CAT1024 and
CAT1025 is sent sequentially with the data from address
N followed by data from address N+1. The READ
operation address counter increments all of the CAT1024
and CAT1025 address bits so that the entire memory
array can be read during one operation.
Selective/Random Read
Selective/Random READ operations allow the Master
device to select at random any memory location for a
READ operation. The Master device first performs a
‘dummy’ write operation by sending the START condition,
slave address and byte addresses of the location it
wishes to read. After the CAT1024 and CAT1025
acknowledges, the Master device sends the START
condition and the slave address again, this time with the
R/W bit set to one. The CAT1024 and CAT1025 then
responds with its acknowledge and sends the 8-bit byte
requested. The master device does not send an
acknowledge but will generate a STOP condition.
Figure 11. Selective Read Timing
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
SLAVE
ADDRESS
S
T
A
R
T
BYTE
ADDRESS (n)
S
T
O
P
SLAVE
ADDRESS
S
S
P
A
C
K
A
C
K
A
C
K
DATA n
N
O
A
C
K
Figure 12. Sequential Read Timing
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
DATA n
DATA n+1
DATA n+2
S
T
O
P
DATA n+x
SDA LINE
P
A
C
K
A
C
K
A
C
K
A
C
K
N
O
A
C
K
13
Doc No. 3008, Rev. M
CAT1024, CAT1025
PACKAGE OUTLINES
8-LEAD 300 MIL WIDE PLASTIC DIP (P, L)
0.245 (6.17)
0.295 (7.49)
0.300 (7.62)
0.325 (8.26)
D
0.120 (3.05)
0.150 (3.81) 0.180 (4.57) MAX
0.015 (0.38)
—
0.110 (2.79)
0.150 (3.81)
0.100 (2.54)
BSC
0.310 (7.87)
0.380 (9.65)
0.045 (1.14)
0.060 (1.52)
0.014 (0.36)
0.022 (0.56)
Dimension D
Pkg
Min
Max
8L
0.355 (9.02)
0.400 (10.16)
Notes:
1. Complies with JEDEC Publication 95 MS001 dimensions; however, some of the dimensions may be more stringent.
2. All linear dimensions are in inches and parenthetically in millimeters.
Doc. No. 3008, Rev. M
14
CAT1024, CAT1025
8-LEAD 150 MIL WIDE SOIC (J, W)
0.1497 (3.80)
0.1574 (4.00)
0.2284 (5.80)
0.2440 (6.20)
D
0.0532 (1.35)
0.0688 (1.75)
0.050 (1.27) BSC
0.0040 (0.10)
0.0098 (0.25)
0.013 (0.33)
0.020 (0.51)
0.0099 (0.25)
X 45°
0.0196 (0.50)
0.0075 (0.19)
0.0098 (0.25)
0°–8°
0.016 (0.40)
0.050 (1.27)
Dimension D
Pkg
Min
Max
8L
0.1890(4.80)
0.1968(5.00)
Notes:
1. Complies with JEDEC publication 95 MS-012 dimensions; however, some dimensions may be more stringent.
2. All linear dimensions are in inches and parenthetically in millimeters.
3. Lead coplanarity is 0.004" (0.102mm) maximum.
15
Doc No. 3008, Rev. M
CAT1024, CAT1025
8-LEAD TSSOP (U, Y)
Doc. No. 3008, Rev. M
16
CAT1024, CAT1025
8 LEAD MSOP (R, Z)
0.38
0.28
0.0150
0.0110
0.1970
0.1890
5.00
4.80
S
0.0256 [0.65] BSC
0.1220
0.1142
3.10
2.90
0.0374
0.0295
0.0433 [1.10] MAX.
0.039 [0.10] MAX.
S
0.0059
0.0020
0.15
0.05
0.95
0.75
S
0.0150
0.0110
0.38
0.28
WITH PLATING
0.0276
0.0157
0.70
0.40
0.1220
0.1142
3.10
2.90
0.0091
0.0051
0.23
0.13
0.0050 [0.127]
0˚ - 6˚
WITH
PLATING
BASE METAL
0.0118 [0.30] REF.
SECTION A - A
Notes:
(1) All dimensions are in mm Angles in degrees.
2 Does not include Mold Flash, Protrusion or Gate Burrs. Mold Flash, Protrusions or Gate Burrs shall not exceed 0.15 mm. per side.
3 Does not include Interlead Flash orProtrusion. Interlead Flash or Protrusion shall not exceed 0.25 mm per side.
4 Does not include Dambar Protrusion, allowable Dambar Protrusion shall be 0.08 mm.
(5) This part is compliant with JEDEC Specification MO-187 Variations AA.
(6) Lead span/stand off height/coplanarity are considered as special characteristics. (S)
(7) Controlling dimensions in inches. [mm]
17
Doc No. 3008, Rev. M
CAT1024, CAT1025
TDFN 3X3 PACKAGE (RD4, ZD4)
5
0.75 + 0.05
A
B
3.00 + 0.10
(S)
8
2X
1
3.00 + 0.10
(S)
4
0.15 C
2X
0.0 - 0.05
0.15 C
PIN 1 INDEX AREA
5
8
1.50 + 0.10
0.75 + 0.05
C
2.30 + 0.10
C0.35
0.25 min.
PIN 1 ID
1
0.30 + 0.07 (8x)
1.95 REF. (2x)
NOTE:
1. ALL DIMENSION ARE IN mm. ANGLES IN DEGREES.
2. COPLANARITY SHALL NOT EXCEED 0.08 mm.
3. WARPAGE SHALL NOT EXCEED 0.10 mm.
4. PACKAGE LENGTH / PACKAGE WIDTH ARE CONSIDERED AS SPECIAL CHARACTERISTIC(S)
5. REFER JEDEC MO-229 / WEEC
Doc. No. 3008, Rev. M
18
0.30 + 0.10 (8x)
0.65 TYP. (6x)
CAT1024, CAT1025
Ordering Information
Prefix
CAT
Optional
Company ID
Device #
Suffix
1024
Product
Number
1024: 2K
1025: 2K
J
I
Temperature Range
I = Industrial (-40˚C to 85˚C)
E = Extended Automotive
(-40˚C to +125˚C)
Package
P: PDIP
J: SOIC (JEDEC)
R: MSOP
U: TSSOP
RD4: 8-pad TDFN (3x3mm)
L: PDIP (Lead free, Halogen free)
W: SOIC (JEDEC, Lead free, Halogen free)
Z: MSOP Lead free, Halogen free)
Y: TSSOP (Lead free, Halogen free)
ZD4: 3x3mm TDFN (Lead free, Halogen free)
-30
TE13
Tape & Reel
SOIC: 2000/Reel
TSSOP: 2000/Reel
MSOP: 2500/Reel
TDFN: 2000/Reel
Reset Threshold
Voltage
45: 4.5-4.75V
42: 4.25-4.5V
30: 3.0-3.15V
28: 2.85-3.0V
25: 2.55-2.7V
Note:
(1) The device used in the above example is a CAT1024JI-30TE13 (Supervisory circuit with I2C serial 2k CMOS EEPROM, SOIC, Industrial
Temperature, 3.0-3.15V Reset Threshold Voltage, Tape and Reel).
19
Doc No. 3008, Rev. M
REVISION HISTORY
Date
Rev.
Reason
11/7/03
I
Eliminated Automotive temperature range
4/12/2004
J
Eliminated data sheet designation
Updated Reel Ordering Information
11/1/2004
K
Changed SOIC package designators
Eliminated 8-pad TDFN (3x4.9mm) package
Added package outlines
11/04/04
L
Update Pin Configuration
11/11/04
M
Update Features
Update Description
Updae DC Operating Characteristic
Update AC Characteristics
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Publication #:
Revison:
Issue date:
3008
M
11/11/04
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