Catalyst CAT24C018JI-TE13 1k-bit serial eeprom Datasheet

CAT24C01B
1K-Bit Serial EEPROM
FEATURES
■ 2-Wire Serial Interface
■ 1,000,000 Program/Erase Cycles
■ 1.8 to 6.0Volt Operation
■ 100 Year Data Retention
■ Low Power CMOS Technology
■ 8-pin DIP, 8-pin SOIC, 8 pin TSSOP or 8-pin MSOP
■ 4-Byte Page Write Buffer
■ Commercial, Industrial and Automotive
Temperature Ranges
■ Self-Timed Write Cycle with Auto-Clear
DESCRIPTION
The CAT24C01B is a 1K-bit Serial CMOS EEPROM
internally organized as 128 words of 8 bits each. Catalyst’s
advanced CMOS technology substantially reduces device power requirements. The CAT24C01B features a
4-byte page write buffer. The device operates via a 2wire serial interface and is available in 8-pin DIP, 8-pin
SOIC, 8-pin TSSOP or 8-pin MSOP.
PIN CONFIGURATION
BLOCK DIAGRAM
SOIC Package (J)
DIP Package (P)
1
2
3
4
NC
NC
NC
VSS
8
7
6
5
VCC
TEST
SCL
SDA
1
2
3
4
NC
NC
NC
VSS
8
7
6
5
EXTERNAL LOAD
VCC
TEST
SCL
SDA
VCC
VSS
5020 FHD F01
MSOP Package (R)
1
2
3
4
NC
NC
NC
VSS
8
7
6
5
SDA
TSSOP Package (U)
VCC
TEST
SCL
SDA
NC
NC
NC
VSS
1
2
3
4
8
7
6
5
VCC
TEST
SCL
SDA
WORD ADDRESS
BUFFERS
COLUMN
DECODERS
START/STOP
LOGIC
XDEC
E2PROM
EEPROM
CONTROL
LOGIC
DATA IN STORAGE
PIN FUNCTIONS
Pin Name
SENSE AMPS
SHIFT REGISTERS
DOUT
ACK
Function
NC
No Connect
SDA
Serial Data/Address
SCL
Serial Clock
VCC
+1.8V to +6.0V Power Supply
VSS
Ground
TEST
Test Input (GND, VCC or
Floating)
© 1999 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
HIGH VOLTAGE/
TIMING CONTROL
SCL
1
STATE COUNTERS
Doc. No. 25085-00 7/99 S-1
CAT24C01B
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Temperature Under Bias ................. –55°C to +125°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of
the device at these or any other conditions outside of those
listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for
extended periods may affect device performance and
reliability.
Storage Temperature ....................... –65°C to +150°C
Voltage on Any Pin with
Respect to Ground(1) ........... –2.0V to +VCC + 2.0V
VCC with Respect to Ground ............... –2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25°C) .................................. 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(2) ........................ 100mA
RELIABILITY CHARACTERISTICS
Symbol
Units
Reference Test Method
1,000,000
Cycles/Byte
MIL-STD-883, Test Method 1033
Data Retention
100
Years
MIL-STD-883, Test Method 1008
VZAP(3)
ESD Susceptibility
2000
Volts
MIL-STD-883, Test Method 3015
ILTH(3)(4)
Latch-up
100
mA
NEND(3)
TDR
(3)
Parameter
Min.
Endurance
Max.
JEDEC Standard 17
D.C. OPERATING CHARACTERISTICS
VCC = +1.8V to +6.0V, unless otherwise specified.
Limits
Symbol
Max.
Units
Test Conditions
Power Supply Current
3
mA
fSCL = 100 KHz
Standby Current (VCC = 5.0V)
0
µA
VIN = GND or VCC
ILI
Input Leakage Current
10
µA
VIN = GND to VCC
ILO
Output Leakage Current
10
µA
VOUT = GND to VCC
VIL
Input Low Voltage
–1
VCC x 0.3
V
VIH
Input High Voltage
VCC x 0.7
VCC + 0.5
V
ICC
ISB
(5)
Parameter
Min.
Typ.
VOL1
Output Low Voltage (VCC = 3.0V)
0.4
V
IOL = 3 mA
VOL2
Output Low Voltage (VCC = 1.8V)
0.5
V
IOL = 1.5 mA
CAPACITANCE TA = 25°C, f = 1.0 MHz, VCC = 5V
Symbol
Test
Max.
Units
Conditions
CI/O(3)
Input/Output Capacitance (SDA)
8
pF
VI/O = 0V
CIN(3)
Input Capacitance (A0, A1, A2, SCL, WP)
6
pF
VIN = 0V
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is VCC +0.5V, which may overshoot to VCC + 2.0V for periods of less than 20ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V.
(5) Standby Current (ISB) = 0µA (<900nA).
Doc. No. 25085-00 7/99 S-1
2
CAT24C01B
A.C. CHARACTERISTICS
VCC = +1.8V to +6.0V, CL=1TTL Gate and 100pF (unless otherwise specified).
Read & Write Cycle Limits
Symbol
Parameter
1.8V, 2.5V
Min.
Max.
4.5V-5.5V
Min.
Max.
Units
FSCL
Clock Frequency
100
400
kHz
TI(1)
Noise Suppression Time
Constant at SCL, SDA Inputs
100
100
ns
tAA
SCL Low to SDA Data Out
and ACK Out
3.5
1
µs
tBUF(1)
Time the Bus Must be Free Before
a New Transmission Can Start
tHD:STA
Start Condition Hold Time
tLOW
4.7
1.2
µs
4
0.6
µs
Clock Low Period
4.7
1.2
µs
tHIGH
Clock High Period
4
0.6
µs
tSU:STA
Start Condition Setup Time
(for a Repeated Start Condition)
4.7
0.6
µs
tHD:DAT
Data In Hold Time
0
0
ns
tSU:DAT
Data In Setup Time
250
100
ns
tR(1)
SDA and SCL Rise Time
1
0.3
µs
SDA and SCL Fall Time
300
300
ns
tF
(1)
tSU:STO
Stop Condition Setup Time
4.7
0.6
µs
tDH
Data Out Hold Time
100
100
ns
Power-Up Timing(1)(2)
Symbol
Parameter
Max.
Units
tPUR
Power-up to Read Operation
1
ms
tPUW
Power-up to Write Operation
1
ms
Write Cycle Limits
Symbol
Parameter
tWR
Write Cycle Time
Min.
Typ.
Max
Units
10
ms
interface circuits are disabled, SDA is allowed to remain
high, and the device does not respond to its input.
The write cycle time is the time from a valid stop
condition of a write sequence to the end of the internal
program/erase cycle. During the write cycle, the bus
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
3
Doc. No. 25085-00 7/99 S-1
CAT24C01B
FUNCTIONAL DESCRIPTION
SDA: Serial Data/Address
The CAT24C01B bidirectional serial data/address pin is
used to transfer data into and out of the device. The SDA
pin is an open drain output and can be wired with other
open drain or open collector outputs.
The CAT24C01B uses a 2-wire data transmission protocol. The protocol defines any device that sends data to
the bus to be a transmitter and any device receiving data
to be a receiver. Data transfer is controlled by the Master
device which generates the serial clock and all START
and STOP conditions for bus access. The CAT24C01B
operates as a Slave device. Both the Master and Slave
devices can operate as either transmitter or receiver, but
the Master device controls which mode is activated.
2-WIRE BUS PROTOCOL
The following defines the features of the 2-wire bus
protocol:
(1) Data transfer may be initiated only when the bus is
not busy.
PIN DESCRIPTIONS
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any changes
in the data line while the clock line is high will be
interpreted as a START or STOP condition.
SCL: Serial Clock
The CAT24C01B serial clock input pin is used to clock
all data transfers into or out of the device. This is an input
pin.
Figure 1. Bus Timing tF
tHIGH
tLOW
tR
tLOW
SCL
tSU:STA
tHD:STA
tHD:DAT
tSU:DAT
tSU:STO
SDA IN
tAA
tBUF
tDH
SDA OUT
5020 FHD F03
Figure 2. Write Cycle Timing
SCL
SDA
8TH BIT
BYTE n
ACK
tWR
STOP
CONDITION
START
CONDITION
ADDRESS
5020 FHD F04
Figure 3. Start/Stop Timing
SDA
SCL
5020 FHD F05
START BIT
Doc. No. 25085-00 7/99 S-1
STOP BIT
4
CAT24C01B
START Condition
(with the R/W bit set to zero) to the Slave device. After the
Slave generates an acknowledge, the Master device
transmits the data byte to be written into the addressed
memory location. The CAT24C01B acknowledge once
more and the Master generates the STOP condition, at
which time the device begins its internal programming
cycle to nonvolatile memory. While this internal cycle is
in progress, the device will not respond to any request
from the Master device.
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The CAT24C01B monitors the
SDA and SCL lines and will not respond until this
condition is met.
STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must end
with a STOP condition.
Page Write
Acknowledge
The CAT24C01B writes up to 4 bytes of data in a single
write cycle, using the Page Write operation. The Page
Write operation is initiated in the same manner as the
Byte Write operation, however instead of terminating
after the initial word is transmitted, the Master is allowed
to send up to 3 additional bytes. After each byte has been
transmitted the CAT24C01B will respond with an acknowledge, and internally increment the low order address bits by one. The high order bits remain unchanged.
After a successful data transfer, each receiving device is
required to generate an acknowledge. The Acknowledging device pulls down the SDA line during the ninth clock
cycle, signaling that it received the 8 bits of data.
The CAT24C01B responds with an acknowledge after
receiving a START condition and its word address. If the
device has been selected along with a write operation,
it responds with an acknowledge after receiving each 8bit byte.
If the Master transmits more than 4 bytes prior to sending
the STOP condition, the address counter ‘wraps around,’
and previously transmitted data will be overwritten.
When the CAT24C01B is in a READ mode it transmits
8 bits of data, releases the SDA line, and monitors the
line for an acknowledge. Once it receives this acknowledge, the CAT24C01B will continue to transmit data. If
no acknowledge is sent by the Master, the device
terminates data transmission and waits for a STOP
condition.
Once all 4 bytes are received and the STOP condition
has been sent by the Master, the internal programming
cycle begins. At this point all received data is written to
the CAT24C01B in a single write cycle.
Acknowledge Polling
WRITE OPERATIONS
The disabling of the inputs can be used to take advan-
Byte Write
In the Byte Write mode, the Master device sends the
START condition and the word address information
Figure 4. Acknowledge Timing
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
5020 FHD F06
5
Doc. No. 25085-00 7/99 S-1
CAT24C01B
Sequential Read
tage of the typical write cycle time. Once the stop
condition is issued to indicate the end of the host’s write
operation, the CAT24C01B initiates the internal write
cycle. ACK polling can be initiated immediately. This
involves issuing the start condition followed by the byte
address for a write operation. If the CAT24C01B is still
busy with the write operation, no ACK will be returned.
If the CAT24C01B has completed the write operation, an
ACK will be returned and the host can then proceed with
the next read or write operation.
The Sequential READ operation can be initiated after
the 24C01B sends the initial 8-bit byte requested, the
Master will respond with an acknowledge which tells the
device it requires more data. The CAT24C01B will
continue to output an 8-bit byte for each acknowledge
sent by the Master. The operation is terminated when
the Master fails to respond with an acknowledge, thus
sending the STOP condition.
The data being transmitted from the CAT24C01B is
output sequentially with data from address N followed by
data from address N+1. The READ operation address
counter increments all of the CAT24C01B address bits
so that the entire memory array can be read during one
operation. If more than bytes are read out, the counter
will “wrap around” and continue to clock out data bytes.
READ OPERATIONS
The READ operation for the CAT24C01B is initiated in
the same manner as the write operation with the one
exception that the R/W bit is set to a one. Two different
READ operations are possible: Byte READ and Sequential READ.
It should be noted that the ninth clock cycle of the read
operation is not a "don't care." To terminate a read
operation, the master must either issure a stop condition
during the ninth cycle or hold SDA HIGH during the ninth
clock cycle and then issue a stop condition.
Byte Read
To initiate a read operation, the master sends a start
condition followed by a seven bit word address and a
read bit. The CAT24C01B responds with an acknowledge and then transmits the eight bits of data. The read
operation is terminated by the master; by not responding with an acknowledge and by issuing a stop condition.
Refer to Figure 7 for the start word address, read bit,
acknowledge and data transfer sequence.
Figure5. Byte Write Timing
BUS ACTIVITY:
SDA LINE
S
T
A
WORD
R ADDRESS(n)
T
S
T
O
P
S
P
BUS ACTIVITY:
M
S
B
LRA
S / C
BW K
DATA n
A
C
K
Figure 6. Page Write Timing
BUS ACTIVITY:
SDA LINE
BUS ACTIVITY:
Doc. No. 25085-00 7/99 S-1
S
T
A
R
T
WORD
ADDRESS(n)
DATA n
S
T
O
P
DATA n+3
DATA n+1
P
S
M
S
B
LRA
S / C
BW K
A
C
K
6
A
C
K
A
C
K
CAT24C01B
Figure 7. Byte Read Timing
BUS ACTIVITY
MASTER
SDA LINE
S
T
A
WORD
R ADDRESS(n)
T
S
T
O
P
DATA n
P
S
BUS ACTIVITY
CAT24C01B
LRA
S / C
BW K
M
S
B
A
C
K
Figure 8. Sequential Read Timing
A
C
K
A
C
K
BUS ACTIVITY
MASTER ADDRESS
S
T
O
P
A
C
K
SDA LINE
BUS ACTIVITY
CAT24C01B
P
R A
/ C
WK
DATA n
DATA n+1
DATA n+x
DATA n+2
ORDERING INFORMATION
Prefix
CAT
Optional
Company ID
Device #
24C01B
Product Number
24C01B: 1K
Suffix
J
I
-1.8
Temperature Range
Blank = Commercial (0˚ - 70˚C)
I = Industrial (-40˚ - 85˚C)
A = Automotive (-40˚ - 105˚C)*
Package
P: PDIP
J: SOIC (JEDEC)
U: TSSOP
R: MSOP
TE13
Tape & Reel
TE13: 2000/Reel
Operating Voltage
Blank: 2.5V - 6.0V
1.8: 1.8V - 6.0V
* -40˚ to +125˚C is available upon request
Notes:
(1) The device used in the above example is a 24C01BJI-1.8TE13 (SOIC, Industrial Temperature, 1.8 Volt to 6 Volt Operating
Voltage, Tape & Reel)
7
Doc. No. 25085-00 7/99 S-1
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