CAT34WC02 2-kb I2C Serial EEPROM, Serial Presence Detect FEATURES ■ 400 kHz (5 V) and 100 kHz (1.7 V) I2C bus ■ 1,000,000 program/erase cycles compatible ■ 8-pin TSSOP package ■ Low power CMOS technology - “Green” package option available ■ 16-byte page write buffer ■ Hardware write protect ■ Self-timed write cycle with auto-clear ■ Software write protection for lower 128 bytes DESCRIPTION The CAT34WC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each. Catalyst’s advanced CMOS technology substantially reduces device power requirements. The CAT34WC02 features PIN CONFIGURATION VSS 8 7 6 5 Pin Name VCC WP SCL SDA it n o c PIN FUNCTIONS Function s i D d e a 16-byte page write buffer. The device operates via the I2C bus serial interface and is available in an 8-pin TSSOP package. u n BLOCK DIAGRAM TSSOP Package (U, Y, GY) 1 2 3 4 a P ■ 256 x 8 memory organization ■ Industrial temperature range A0 A1 A2 t r ■ 100 year data retention ■ 1.7 to 5.5 volt operation A0, A1, A2 Device Address Inputs SDA Serial Data/Address SCL Serial Clock WP Write Protect VCC 1.7 V to 5.5 V Power Supply VSS Ground EXTERNAL LOAD SENSE AMPS SHIFT REGISTERS DOUT ACK VCC VSS SDA WORD ADDRESS BUFFERS START/STOP LOGIC XDEC WP COLUMN DECODERS E2PROM CONTROL LOGIC DATA IN STORAGE HIGH VOLTAGE/ TIMING CONTROL SCL A0 A1 A2 STATE COUNTERS SLAVE ADDRESS COMPARATORS 24CXX F03 * Catalyst Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol. © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 1 Doc. No. 1003, Rev. O CAT34WC02 ABSOLUTE MAXIMUM RATINGS* *COMMENT Temperature Under Bias Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. –55°C to +125°C Storage Temperature ....................... –65°C to +150°C Voltage on Any Pin with Respect to Ground(1) ............ –2.0 V to VCC + 2.0 V VCC with Respect to Ground ............. –2.0 V to +7.0 V Package Power Dissipation Capability (Ta = 25°C) .................................. 1.0 W t r Lead Soldering Temperature (10 seconds) ...... 300°C Output Short Circuit Current(2) ....................... 100 mA RELIABILITY CHARACTERISTICS Symbol Parameter Min. NEND(3) Endurance TDR(3) Data Retention 100 VZAP(3)(6) ESD Susceptibility 2000 ILTH(3)(4) Latch-up 100 Max. 1,000,000 D.C. OPERATING CHARACTERISTICS VCC = + 1.7 V to + 5.5 V, unless otherwise specified. it n Symbol Parameter ICC Power Supply Current (Read) ICC Cycles/Byte d e u n mA fSCL = 100 kHz 1 mA Power Supply Current (Write) fSCL = 100 kHz 3 mA Standby Current (VCC = 5.0 V) VIN = GND or VCC 1 µA ILI Input Leakage Current VIN = GND to VCC 1 µA ILO Output Leakage Current VOUT = GND to VCC 1 µA VIL Input Low Voltage –1 VCC x 0.3 V VCC x 0.7 VCC + 1.0 V VIH o c s i D Input High Voltage Typ Volts Units ISB Min Years Max (5) Test Conditions a P Units VOL1 Output Low Voltage (VCC = 3.0 V) IOL = 3 mA 0.4 V VOL2 Output Low Voltage (VCC = 1.7 V) IOL = 1.5 mA 0.5 V CAPACITANCE TA = 25°C, f = 1.0 MHz, VCC = 5.0 V Symbol Test Conditions CI/O(3) Input/Output Capacitance (SDA) Input Capacitance (A0, A1, A2, SCL) CIN (3) Min Typ Max Units VI/O = 0 V 8 pF VIN = 0 V 6 pF Note: (1) The minimum DC input voltage is - 0.5 V. During transitions, inputs may undershoot to - 2.0 V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC + 0.5 V, which may overshoot to VCC + 2.0 V for periods of less than 20 ns. (2) Output shorted for no more than one second. No more than one output shorted at a time. (3) This parameter is tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100 and JEDEC test methods. (4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1 V to VCC + 1 V. (5) Maximum standby current (ISB ) = 10µA for the Automotive and Extended Automotive temperature range. Doc. No. 1003, Rev. O 2 © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT34WC02 A.C. CHARACTERISTICS VCC = 1.7 V to 5.5 V, unless otherwise specified. Read & Write Cycle Limits Die Revision A, C, E 1.7V-5.5V Symbol Parameter FSCL Clock Frequency 100 400 TI Noise Suppression Time Constant at SCL, SDA Inputs 200 200 tAA SCL Low to SDA Data Out and ACK Out 3.5 tBUF(1) Time the Bus Must be Free Before a New Transmission Can Start tHD:STA Start Condition Hold Time tLOW Clock Low Period 4.7 tHIGH Clock High Period 4 tSU:STA Start Condition Setup Time (for a Repeated Start Condition) tHD:DAT Data In Hold Time tSU:DAT Data In Setup Time (1) Min. 4.5V-5.5V (1) SDA and SCL Rise Time tF (1) SDA and SCL Fall Time tSU:STO Stop Condition Setup Time tDH Data Out Hold Time tR o c Power-Up Timing(1)(2) s i D Symbol Parameter Min. 1.2 4 0.6 4.7 d e 1.2 0.6 u n 50 0.6 t r Max. Units kHz a P 1 4.7 0 it n Max. ns µs µs µs µs µs µs 0 ns 50 ns 1 0.3 µs 300 300 ns 4 0.6 µs 100 100 ns Min Typ Max Units tPUR Power-up to Read Operation 1 ms tPUW Power-up to Write Operation 1 ms Typ Max Units 4 10 ms Write Cycle Limits Symbol Parameter tWR Write Cycle Time Min interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address. The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write cycle, the bus Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 3 Doc No. 1003, Rev. O CAT34WC02 FUNCTIONAL DESCRIPTION all data transfers into or out of the device. This is an input pin. The CAT34WC02 supports the I2C Bus data transmission protocol. This Inter-Integrated Circuit Bus protocol defines any device that sends data to the bus to be a transmitter and any device receiving data to be a receiver. Data transfer is controlled by the Master device which generates the serial clock and all START and STOP conditions for bus access. The CAT34WC02 operates as a Slave device. Both the Master and Slave devices can operate as either transmitter or receiver, but the Master device controls which mode is activated. A maximum of 8 devices may be connected to the bus as determined by the device address inputs A0, A1, and A2. SDA: Serial Data/Address The CAT34WC02 bidirectional serial data/address pin is used to transfer data into and out of the device. The SDA pin is an open drain output and can be wire-ORed with other open drain or open collector outputs. WP: Write Protect SCL: Serial Clock The CAT34WC02 serial clock input pin is used to clock tHIGH tF tLOW tLOW tHD:DAT tHD:STA it n SDA IN tAA SDA OUT o c Figure 2. Write Cycle Timing SCL SDA is D 8TH BIT BYTE n d e tR SCL tSU:STA a P This input, when tied to GND, allows write operations to the entire memory. For CAT34WC02 when this pin is tied to VCC, the entire array of memory is write protected. When left floating, memory is unprotected. PIN DESCRIPTIONS Figure 1. Bus Timing t r A0, A1, A2: Device Address Inputs These inputs set device address when cascading multiple devices. A maximum of eight devices can be cascaded when using the device. u n tSU:DAT tSU:STO tBUF tDH 5020 FHD F03 ACK tWR STOP CONDITION START CONDITION ADDRESS 5020 FHD F04 Figure 3. Start/Stop Timing SDA SCL START BIT Doc. No. 1003, Rev. O STOP BIT 4 5020 FHD F05 © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT34WC02 I2C BUS PROTOCOL and define which device the Master is accessing. Up to eight CAT34WC02 may be individually addressed by the system. The last bit of the slave address specifies whether a Read or Write operation is to be performed. When this bit is set to 1, a Read operation is selected, and when set to 0, a Write operation is selected. The following defines the features of the I2C bus protocol: (1) Data transfer may be initiated only when the bus is not busy. After the Master sends a START condition and the slave address byte, the CAT34WC02 monitors the bus and responds with an acknowledge (on the SDA line) when its address matches the transmitted slave address. The CAT34WC02 then performs a Read or a Write operation depending on the state of the R/W bit. (2) During a data transfer, the data line must remain stable whenever the clock line is high. Any changes in the data line while the clock line is high will be interpreted as a START or STOP condition. START Condition The START Condition precedes all commands to the device, and is defined as a HIGH to LOW transition of SDA when SCL is HIGH. The CAT34WC02 monitor the SDA and SCL lines and will not respond until this condition is met. Acknowledge DEVICE ADDRESSING it n The Master begins a transmission by sending a START condition. The Master then sends the address of the particular slave device it is requesting. The four most significant bits of the 8-bit slave address are fixed (except when accessing the Write Protect Register) as 1010 for the CAT34WC02 (see Fig. 5). The next three significant bits (A2, A1, A0) are the device address bits o c Figure 4. Acknowledge Timing s i D SCL FROM MASTER a P After a successful data transfer, each receiving device is required to generate an acknowledge. The Acknowledging device pulls down the SDA line during the ninth clock cycle, signaling that it received the 8 bits of data. d e STOP Condition A LOW to HIGH transition of SDA when SCL is HIGH determines the STOP condition. All operations must end with a STOP condition. t r The CAT34WC02 responds with an acknowledge after receiving a START condition and its slave address. If the device has been selected along with a write operation, it responds with an acknowledge after receiving each byte. u n When the CAT34WC02 begins a READ mode, it transmits 8 bits of data, releases the SDA line, and monitors the line for an acknowledge. Once it receives this acknowledge, the CAT34WC02 will continue to transmit data. If no acknowledge is sent by the Master, the device terminates data transmission and waits for a STOP condition. 1 8 9 DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER START ACKNOWLEDGE 5020 FHD F06 Figure 5. Slave Address Bits 1 0 1 0 A2 A1 A0 R/W Normal Read and Write R/W Programming the Write Protect Register DEVICE ADDRESS 0 © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 1 1 0 A2 A1 5 A0 34WC02 F07 Doc No. 1003, Rev. O CAT34WC02 Once all 16 bytes are received and the STOP condition has been sent by the Master, the internal programming cycle begins. At this point all received data is written to the CAT34WC02 in a single write cycle. WRITE OPERATIONS Byte Write In the Byte Write mode, the Master device sends the START condition and the slave address information (with the R/W bit set to zero) to the Slave device. After the Slave generates an acknowledge, the Master sends the byte address that is to be written into the address pointer of the CAT34WC02. After receiving another acknowledge from the Slave, the Master device transmits the data byte to be written into the addressed memory location. The CAT34WC02 acknowledges once more and the Master generates the STOP condition, at which time the device begins its internal programming to nonvolatile memory. While this internal cycle is in progress, the device will not respond to any request from the Master device. Acknowledge Polling The disabling of the inputs can be used to take advantage of the typical write cycle time. Once the stop condition is issued to indicate the end of the host’s write operation, the CAT34WC02 initiates the internal write cycle. ACK polling can be initiated immediately. This involves issuing the start condition followed by the slave address for a write operation. If the CAT34WC02 is still busy with the write operation, no ACK will be returned. If the CAT34WC02 has completed the write operation, an ACK will be returned and the host can then proceed with the next read or write operation. WRITE PROTECTION The CAT34WC02 writes up to 16 bytes of data in a single write cycle, using the Page Write operation. The Page Write operation is initiated in the same manner as the Byte Write operation, however instead of terminating after the initial word is transmitted, the Master is allowed to send up to 15 additional bytes. After each byte has been transmitted the CAT34WC02 will respond with an acknowledge, and internally increment the low order address bits by one. The high order bits remain unchanged. it n If the Master transmits more than 16 bytes prior to sending the STOP condition, the address counter ‘wraps around’, and previously transmitted data will be overwritten. o c is BUS ACTIVITY: MASTER D SDA LINE S T A R T a P d e Page Write Figure 6. Byte Write Timing t r The CAT34WC02 is designed with a hardware protect pin that enables the user to protect the entire memory. The CAT34WC02 also has a software write protection feature. By programming the software write protection register, the first 128 bytes are write protected. The software and hardware protection features of the CAT34WC02 are designed into the part to provide added flexibility to the design engineers. u n Hardware The write protection feature of CAT34WC02 allows the user to protect against inadvertent programming of the memory array. If the WP pin is tied to Vcc, the entire SLAVE ADDRESS BYTE ADDRESS S T O P DATA S P A C K A C K A C K 5020 FHD F08 Figure 7. Page Write Timing BUS ACTIVITY: MASTER SDA LINE S T A R T SLAVE ADDRESS BYTE ADDRESS (n) S DATA n DATA n+1 DATA n+P P * A C K A C K A C K NOTE: IN THIS EXAMPLE n = XXXX 0000(B); X = 1 or 0 Doc. No. 1003, Rev. O S T O P 6 A C K A C K 5020 FHD F09 © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT34WC02 memory array is protected and becomes read only. The entire memory becomes write protected regardless of whether the write protect register has been written or not. When WP pin is tied to Vcc, the user cannot program the write protect register. If the WP pin is left floating or tied to Vss, the device can be written into (except the first 128 bytes if the write protect register is programmed). ceives its slave address information (with the R/W bit set to one), it issues an acknowledge, then transmits the 8bit byte requested. The master device does not send an acknowledge but will generate a STOP condition. Selective Read Selective READ operations allow the Master device to select at random any memory location for a READ operation. The Master device first performs a ‘dummy’ write operation by sending the START condition, slave address and byte address of the location it wishes to read. After the CAT34WC02 acknowledge the word address, the Master device resends the START condition and the slave address, this time with the R/W bit set to one. The CAT34WC02 then responds with its acknowledge and sends the 8-bit byte requested. The master device does not send an acknowledge but will generate a STOP condition. Software The software protection on the CAT34WC02 protects the first 128 bytes of the memory array permanently. Software write protect is implemented by programming the write protect register. A user can write only once to the write protect register and once written it is irreversible (even if you reset the CAT34WC02). The write protection register is written by sending a regular byte write command with the slave address set to 0110 instead of 1010. After the initial access to the register, the device will not acknowledge any further access to this register. READ OPERATIONS The READ operation for the CAT34WC02 is initiated in the same manner as the write operation with the one exception that the R/W bit is set to a one. Three different READ operations are possible: Immediate Address READ, Selective READ and Sequential READ. it n Immediate Address Read The CAT34WC02’s address counter contains the address of the last byte accessed, incremented by one. In other words, if the last READ or WRITE access was to address N, the READ immediately following would access data from address N + 1. If N = 255 for 34WC02, then the counter will ‘wrap around’ to address 0 and continue to clock out data. After the CAT34WC02 re- o c is D Figure 8. Immediate Address Read Timing SCL SDA BUS ACTIVITY: MASTER SDA LINE d e Sequential Read a P The Sequential READ operation can be initiated by either the Immediate Address READ or Selective READ operations. After the CAT34WC02 sends the initial 8-bit data requested, the Master will respond with an acknowledge which tells the device it requires more data. The CAT34WC02 will continue to output a byte for each acknowledge sent by the Master. The operation will terminate operation when the Master fails to respond with an acknowledge, thus sending the STOP condition. u n The data being transmitted from the CAT34WC02 is outputted sequentially with data from address N followed by data from address N + 1. The READ operation address counter increments all of the CAT34WC02 address bits so that the entire memory array can be read during one operation. If more than the 256 bytes are read out, the counter will “wrap around” and continue to clock out data bytes. S T A R T S T O P SLAVE ADDRESS S P A C K N O DATA K 8 A C K 9 8TH BIT DATA OUT © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice t r NO ACK 7 STOP 5020 FHD F10 Doc No. 1003, Rev. O CAT34WC02 Figure 9. Memory Array FFH Hardware Write Protectable (by connecting WP pin to Vcc) 7FH Software Write Protectable (by programming the write protect register) 00H Figure 10. Software Write Protect BUS ACTIVITY: MASTER SDA LINE S T A R T SLAVE ADDRESS BYTE ADDRESS S A C K it n Figure 11. Selective Read Timing o c BUS ACTIVITY: MASTER is SDA LINE D S T A R T SLAVE ADDRESS S d e u n XXXXXXXX X = Don't Care S T A R T BYTE ADDRESS (n) a P S T O P DATA P XXXXXXXX A C K t r A C K S T O P SLAVE ADDRESS S * A C K P A C K A C K DATA n N O A C K 5020 FHD F11 Figure 12. Sequential Read Timing BUS ACTIVITY: MASTER SLAVE ADDRESS DATA n DATA n+1 DATA n+2 S T O P DATA n+x SDA LINE P A C K A C K A C K A C K N O A C K Doc. No. 1003, Rev. O 8 5020 FHD F12 © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT34WC02 ORDERING INFORMATION Prefix Device # Suffix CAT 34WC02 Company ID Product Number U Rev E TE13 I t r Tape & Reel Temperature Range I = Industrial (-40˚C to +85˚C) Package U: TSSOP Y: TSSOP (Lead-free, Halogen-free) GY: TSSOP (Lead-free, Halogen-free, NiPdAu lead plating) Die Revision 34WC02: A, C, E a P Notes: (1) The device used in the above example is a CAT34WC02UI-TE13 REV E (TSSOP, Industrial Temperature, 1.7 Volt to 5.5 Volt Operating Voltage, Tape & Reel) o c it n s i D © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice d e u n 9 Doc No. 1003, Rev. O REVISION HISTORY Date 9/22/2003 Rev. H 12/9/2003 8/3/2004 I J 11/29/2004 12/21/2004 1/10/2005 05/19/2005 K L M N 08/03/2005 O Reason Eliminated commercial temperature range Updated marking Changed Industrial Temp to “I” from “Blank” in ordering information Updated Features Updated DC Operating Characteristics table & notes Added Die Revision E to Ordering Information Updated ordering information (added die revision A) Deleted DIP and SOIC packages in all areas Update Reliability Characteristics Update A.C. Characteristics Update Pin Configuration Update Ordering Information DPP ™ AE2 ™ it n MiniPot™ d e u n Copyrights, Trademarks and Patents Trademarks and registered trademarks of Catalyst Semiconductor include each of the following: t r a P Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000. CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES. o c Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a situation where personal injury or death may occur. s i D Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale. Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications and may not be complete. Catalyst Semiconductor, Inc. Corporate Headquarters 1250 Borregas Avenue Sunnyvale, CA 94089 Phone: 408.542.1000 Fax: 408.542.1200 www.caalyst-semiconductor.com Publication #: Revison: Issue date: 1003 O 08/03/05