Catalyst CAT523JI-TE10 Configured digitally programmable potentiometer Datasheet

H
CAT523
EE
GEN FR
ALO
Configured Digitally Programmable Potentiometer (DPP™):
Programmable Voltage Applications
LE
FEATURES
APPLICATIONS
■ Two 8-bit DPPs configured as programmable
■ Automated product calibration.
voltage sources in DAC-like applications
A D F R E ETM
■ Remote control adjustment of equipment
■ Common reference inputs
■ Offset, gain and zero adjustments in self-
■ Non-volatile NVRAM memory wiper storage
calibrating and adaptive control systems.
■ Output voltage range includes both supply rails
■ Tamper-proof calibrations.
■ 2 independently addressable buffered
■ DAC (with memory) substitute
output wipers
■ 1 LSB accuracy, high resolution
■ Serial microwire-like interface
■ Single supply operation: 2.7V - 5.5V
■ Setting read-back without effecting outputs
DESCRIPTION
values without effecting the stored settings and stored
settings can be read back without disturbing the
DPP’s output.
The CAT523 is a dual, 8-bit digitally-programmable
potentiometer (DPP™) configured for programmable
voltage and DAC-like applications. Intended for final
calibration of products such as camcorders, fax
machines and cellular telephones on automated high
volume production lines, it is also well suited for systems
capable of self calibration, and applications where
equipment which is either difficult to access or in a
hazardous environment, requires periodic adjustment.
Control of the CAT523 is accomplished with a simple 3wire, Microwire-like serial interface. A Chip Select pin
allows several CAT523's to share a common serial
interface and communication back to the host controller
is via a single serial data line thanks to the CAT523’s TriStated Data Output pin. A RDY/BSY output working in
concert with an internal low voltage detector signals
proper operation of non-volatile NVRAM memory Erase/
Write cycle.
The two independently programmable DPPs have a
common output voltage range which includes both
supply rails. The wipers are buffered by rail to rail op
amps. Wiper settings, stored in non-volatile NVRAM
memory, are not lost when the device is powered down
and are automatically reinstated when power is
returned. Each wiper can be dithered to test new output
The CAT523 is available in the 0°C to 70°C Commercial
and -40°C to + 85°C Industrial operating temperature
ranges and offered in 14-pin plastic DIP and SOIC
mount packages.
PIN CONFIGURATION
FUNCTIONAL DIAGRAM
RDY/BSY
3
PROG
DI
CLK
CS
7
V
DD
VREFH
DIP Package (P, L)
14
1
PROGRAM
CONTROL
1
14
CLK
2
13
RDY/BSY
3
CS
5
2
VDD
SERIAL
CONTROL
WIPER
CONTROL
REGISTER
AND
NVRAM
+
13
+
12
V
OUT1
DI
DO
PROG
4
SERIAL
DATA
OUTPUT
REGISTER
12
CAT
4
11
523
5
10
6
9
7
8
SOIC Package (J, W)
VREFH
VOUT1
VDD
CLK
1
14
2
13
VOUT2
NC
RDY/BSY
3
NC
VREFL
GND
CS
DI
DO
PROG
VREFH
VOUT1
12
4 CAT 11
523
5
10
6
9
VOUT2
7
GND
8
NC
NC
VREFL
V
OUT2
6
DO
CAT523
8
GND
© 2004 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
9
V
REFL
1
Doc. No. 2005, Rev. E
CAT523
Operating Ambient Temperature
Commercial (‘C’ or Blank suffix)
0°C to +70°C
Industrial (‘I’ suffix)
-40°C to +85°C
Junction Temperature
+150°C
Storage Temperature
-65°C to +150°C
Lead Soldering (10 sec max)
+300°C
ABSOLUTE MAXIMUM RATINGS
Supply Voltage*
VDD to GND
Inputs
CLK to GND
CS to GND
DI to GND
RDY/BSY to GND
PROG to GND
VREFH to GND
VREFL to GND
Outputs
D0 to GND
VOUT 1– 4 to GND
-0.5V to +7V
-0.5V to VDD +0.5V
-0.5V to VDD +0.5V
-0.5V to VDD +0.5V
-0.5V to VDD +0.5V
-0.5V to VDD +0.5V
-0.5V to VDD +0.5V
-0.5V to VDD +0.5V
* Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Absolute
Maximum Ratings are limited values applied individually while
other parameters are within specified operating conditions,
and functional operation at any of these conditions is NOT
implied. Device performance and reliability may be impaired by
exposure to absolute rating conditions for extended periods of
time.
-0.5V to VDD +0.5V
-0.5V to VDD +0.5V
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Min
VZAP(1)
ILTH(1)(2)
ESD Susceptibility
Latch-Up
2000
100
Max
Units
Test Method
Volts
mA
MIL-STD-883, Test Method 3015
JEDEC Standard 17
NOTES: 1. This parameter is tested initially and after a design or process change that affects the parameter.
2. Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to VCC + 1V.
POWER SUPPLY
Symbol Parameter
Conditions
IDD1
Supply Current (Read)
IDD2
Supply Current (Write)
VDD
Min
Typ
Max
Units
Normal Operating
—
400
600
µA
Programming, VDD = 5V
—
1600
2500
µA
VDD = 3V
—
1000
1600
µA
2.7
—
5.5
V
Min
Typ
Max
Units
Operating Voltage Range
LOGIC INPUTS
Symbol
Parameter
Conditions
IIH
Input Leakage Current
VIN = VDD
—
—
10
µA
IIL
Input Leakage Current
VIN = 0V
—
—
-10
µA
VIH
High Level Input Voltage
2
—
VDD
V
VIL
Low Level Input Voltage
0
—
0.8
V
Min
Typ
Max
Units
VDD -0.3
—
—
V
LOGIC OUTPUTS
Symbol Parameter
Conditions
VOH
High Level Output Voltage
IOH = -40µA
VIL
Low Level Output Voltage
IOL = 1 mA, VDD = +5V
—
—
0.4
V
IOL = 0.4 mA, VDD = +3V
—
—
0.4
V
Doc. No. 2005, Rev. E
2
CAT523
POTENTIOMETER CHARACTERISTICS
VDD = +2.7V to +5.5V, VREFH = VDD, VREFL = 0V, unless otherwise specified
Symbol
Parameter
Conditions
RPOT
Potentiometer Resistance
See Note 3
Min
Typ
Max
Units
24
RPOT to RPOT Match
—
+0.5
Pot Resistance Tolerance
kΩ
+1
%
+20
%
Voltage on VREFH pin
2.7
VDD
V
Voltage on VREFL pin
0V
VDD - 2.7
V
Resolution
0.4
%
INL
Integral Linearity Error
0.5
1
LSB
DNL
Differential Linearity Error
0.25
0.5
LSB
ROUT
Buffer Output Resistance
10
Ω
IOUT
Buffer Output Current
3
mA
TCRPOT
TC of Pot Resistance
300
ppm/˚C
CH/CL
Potentiometer Capacitances
8/8
pF
AC ELECTRICAL CHARACTERISTICS:
VDD = +2.7V to +5.5V, VREFH = VDD, VREFL = 0V, unless otherwise specified
Symbol
Parameter
Conditions
Min
Typ
Max
Units
150
100
0
50
50
—
—
—
—
—
150
700
500
300
DC
—
—
—
—
—
—
—
400
400
4
—
—
—
—
—
—
—
—
—
—
150
150
—
—
5
—
—
—
—
1
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ns
MHz
—
—
3
6
10
10
µs
µs
Digital
tCSMIN
tCSS
tCSH
tDIS
tDIH
tDO1
tDO0
tHZ
tLZ
tBUSY
tPS
tPROG
tCLKH
tCLKL
fC
Minimum CS Low Time
CS Setup Time
CS Hold Time
DI Setup Time
DI Hold Time
Output Delay to 1
Output Delay to 0
Output Delay to High-Z
Output Delay to Low-Z
Erase/Write Cycle Time
PROG Setup Time
Minimum Pulse Width
Minimum CLK High Time
Minimum CLK Low Time
Clock Frequency
CL=100pF,
see note 1
Analog
tDS
DPP Settling Time to 1 LSB
CLOAD = 10 pF, VDD = +5V
CLOAD = 10 pF, VDD = +3V
NOTES: 1. All timing measurements are defined at the point of signal crossing VDD / 2.
2. These parameters are periodically sampled and are not 100% tested.
3. The 24kΩ +20% resistors are configured as 4 resistors in parallel which would provide a measured value between VREFH and
VREFL of 6kΩ +20%. The individual 24kΩ resistors are not measurable but guaranteed by design and verification of the 6kΩ
+20% value.
3
Doc. No. 2005, Rev. E
CAT523
A. C. TIMING DIAGRAM
to
1
2
3
4
5
t CLK H
CLK
t CSS
t CLK L
t CSH
CS
t CSMIN
t DIS
DI
t DIH
t DO0
t LZ
DO
t HZ
t DO1
PROG
t PS
t PROG
RDY/BSY
t
to
Doc. No. 2005, Rev. E
1
2
3
4
BUSY
4
5
CAT523
PIN DESCRIPTION
Pin
Name
1
2
3
4
5
6
7
VDD
CLK
RDY/BSY
CS
DI
DO
PROG
8
9
10
11
12
13
14
GND
VREFL
NC
NC
VOUT2
VOUT1
VREFH
DPP addressing is as follows:
Function
Power supply positive.
Clock input pin.Clock input pin.
Ready/Busy Output
Chip Select
Serial data input pin.
Serial data output pin.
EEPROM Programming Enable
Input
Power supply ground.
Minimum DPP output voltage.
No Connect.
No Connect.
DPP output channel 2.
DPP output channel 1.
Maximum DPP output voltage.
DEVICE OPERATION
DPP OUTPUT
A0
A1
VOUT1
0
0
VOUT2
1
0
read and write operations. When CS is high data may be
read to or from the chip, and the Data Output (DO) pin is
active. Data loaded into the DPP control registers will
remain in effect until CS goes low. Bringing CS to a logic
low returns all DPP outputs to the settings stored in nonvolatile memory and switches DO to its high impedance
Tri-State mode.
The CAT523 is a dual 8-bit configured digitally
programmable potentiometer (DPP) whose outputs can
be programmed to any one of 256 individual voltage
steps. Once programmed, these output settings are
retained in non-volatile memory and will not be lost
when power is removed from the chip. Upon power up
the DPPs return to the settings stored in non-volatile
memory. Each DPP can be written to and read from
independently without effecting the output voltage during
the read or write cycle. Each output can also be
temporarily adjusted without changing the stored output
setting, which is useful for testing new output settings
before storing them in memory.
Because CS functions like a reset the CS pin has been
equipped with a 30 ns to 90 ns filter circuit to prevent
noise spikes from causing unwanted resets and the loss
of volatile data.
CLOCK
The CAT523’s clock controls both data flow in and out of
the IC and non-volatile memory cell programming. Serial
data is shifted into the DI pin and out of the DO pin on the
clock’s rising edge. While it is not necessary for the clock
to be running between data transfers, the clock must be
operating in order to write to non-volatile memory, even
though the data being saved may already be resident in
the DPP wiper control register.
DIGITAL INTERFACE
The CAT523 employs a 3 wire, Microwire-like, serial
control interface consisting of Clock (CLK), Chip Select
(CS) and Data In (DI) inputs. For all operations, address
and data are shifted in LSB first. In addition, all digital
data must be preceded by a logic “1” as a start bit. The
DPP address and data are clocked into the DI pin on the
clock’s rising edge. When sending multiple blocks of
information a minimum of two clock cycles is required
between the last block sent and the next start bit.
No clock is necessary upon system power-up. The
CAT523’s internal power-on reset circuitry loads data
from non-volatile memory to the DPPs without using the
external clock.
Multiple devices may share a common input data line by
selectively activating the CS control of the desired IC.
Data Outputs (DO) can also share a common line
because the DO pin is Tri-Stated and returns to a high
impedance when not in use.
As data transfers are edge triggered clean clock
transitions are necessary to avoid falsely clocking data
into the control registers. Standard CMOS and TTL logic
families work well in this regard and it is recommended
that any mechanical switches used for breadboarding or
device evaluation purposes be debounced by a flip-flop
or other suitable debouncing circuit.
CHIP SELECT
Chip Select (CS) enables and disables the CAT523’s
5
Doc. No. 2005, Rev. E
CAT523
VREF
followed by a two bit DPP address and eight data bits are
clocked into the DPP control register via the DI pin. Data
enters on the clock’s rising edge. The DPP output
changes to its new setting on the clock cycle following
D7, the last data bit.
VREF, the voltage applied between pins VREFH andVREFL,
sets the DPP’s Zero to Full Scale output range where
VREFL = Zero and VREFH = Full Scale. VREF can span the
full power supply range or just a fraction of it. In typical
applications VREFH andVREFL are connected across the
power supply rails. When using less than the full supply
voltage VREFH is restricted to voltages between VDD and
VDD/2 and VREFL to voltages between GND and VDD/2.
Programming is achieved by bringing PROG high for a
minimum of 3 ms. PROG must be brought high sometime after the start bit and at least 150 ns prior to the
rising edge of the clock cycle immediately following the
D7 bit. Two clock cycles after the D7 bit the DAC control
register will be ready to receive the next set of address
and data bits. The clock must be kept running throughout the programming cycle. Internal control circuitry
takes care of ramping the programming voltage for data
transfer to the non-volatile memory cells. The CAT523’s
non-volatile memory cells will endure over 100,000 write
cycles and will retain data for a minimum of 100 years
without being refreshed.
/BUSY
READY/BUSY
When saving data to non-volatile memory, the Ready/
Busy output (RDY/BSY) signals the start and duration of
the non-volatile erase/write cycle. Upon receiving a
command to store data (PROG goes high) RDY/BSY
goes low and remains low until the programming cycle
is complete. During this time the CAT523 will ignore any
data appearing at DI and no data will be output on DO.
RDY/BSY is internally ANDed with a low voltage detector
circuit monitoring VDD. If VDD is below the minimum value
required for non-volatile programming, RDY/BSY will
remain high following the program command indicating
a failure to record the desired data in non-volatile memory.
READING DATA
Each time data is transferred into a DPP wiper control
register currently held data is shifted out via the D0 pin,
thus in every data transaction a read cycle occurs. Note,
however, that the reading process is destructive. Data
must be removed from the register in order to be read.
Figure 2 depicts a Read Only cycle in which no change
occurs in the DPP’s output. This feature allows µPs to
poll DPPs for their current setting without disturbing the
output voltage but it assumes that the setting being read
is also stored in non-volatile memory so that it can be
restored at the end of the read cycle. In Figure 2 CS
returns low before the 13th clock cycle completes. In
doing so the non-volatile memory setting is reloaded into
the DPP wiper control register.
DATA OUTPUT
Data is output serially by the CAT523, LSB first, via the
Data Out (DO) pin following the reception of a start bit
and two address bits by the Data Input (DI). DO
becomes active whenever CS goes high and resumes
its high impedance Tri-State mode when CS returns low.
Tri-Stating the DO pin allows several 523s to share a
single serial data line and simplifies interfacing multiple
523s to a microprocessor.
WRITING TO MEMORY
Programming the CAT523’s non-volatile memory is
accomplished through the control signals: Chip Select
(CS) and Program (PROG). With CS high, a start bit
Figure 1. Writing to Memory
Figure 2. Reading from Memory
to
1
2
3
4
5
6
7
8
9
10
11
12
CS
NEW DPP DATA
DI
1
A0
A1
CURRENT DPP DATA
CURRENT DPP DATA
DO
D0
D1
D2
D3
D4
D5
PROG
RDY/BSY
DPP
OUTPUT
Doc. No. 2005, Rev. E
DPP
OUTPUT
DPP VALUE
DPP VALUE
CURRENT
DPP VALUE
NON-VOLATILE
DPP VALUE
6
D6
D7
CAT523
Since this value is the same as that which had been there
previously no change in the DPP’s output is noticed.
Had the value held in the control register been different
from that stored in non-volatile memory then a change
would occur at the read cycle’s conclusion.
this feature, the new value must be reloaded into the
DPP wiper control register prior to programming. This is
because the CAT523’s internal control circuitry discards
the new data from the programming register two clock
cycles after receiving it (after reception is complete) if no
PROG signal is received.
TEMPORARILY CHANGE OUTPUT
Figure 3. Temporary Change in Output
The CAT523 allows temporary changes in DPP’s output
to be made without disturbing the settings retained in
non-volatile memory. This feature is particularly useful
when testing for a new output setting and allows for user
adjustment of preset or default values without losing the
original factory settings.
to
1
2
3
4
5
6
7
8
9
10
11
12
N
N+1 N+2
CS
NEW DPP DATA
1
DI
Figure 3 shows the control and data signals needed to
effect a temporary output change. DPP wiper settings
may be changed as many times as required and can be
made to any of the two DPPs in any order or sequence.
The temporary setting(s) remain in effect long as CS
remains high. When CS returns low all two DPPs will
return to the output values stored in non-volatile memory.
A0
A1
D0
D1
D2
D3
D4
D5
D6
D7
D6
D7
CURRENT DPP DATA
D0
DO
D1
D2
D3
D4
D5
PROG
DPP
OUTPUT
CURRENT
DPP VALUE
NON-VOLATILE
NEW
DPP VALUE
VOLATILE
CURRENT
DPP VALUE
NON-VOLATILE
When it is desired to save a new setting acquired using
APPLICATION CIRCUITS
DPP INPUT
DPP OUTPUT
ANALOG
OUTPUT
CODE (V - V
VDPP = ———
FS ZERO ) + V ZERO
255
MSB
LSB
1111 1111
1000 0000
0111 1111
0000 0001
0000 0000
+5V
VFS = 0.99 VREF
VZERO = 0.01 V REF
Vi
VREF = 5V
R I = RF
255 (.98 V
——
REF) + .01 VREF = .990 VREF
255
CONTROL
& DATA
V
0 (.98 V
——
) + .01 V
= .010 V
REF
REF
REF
255
V
V
V
OUT
OUT
OUT
OUT
RF
+15V
VDD
V OUT= +4.90V
128 (.98 V
——
) + .01 V
= .502 V
REF
REF
REF
255
127
—— (.98 V
) + .01 V
= .498 V
255
REF
REF
REF
1
—— (.98 V
) + .01 V
= .014 V
255
REF
REF
REF
Ri
VREFH
+
CAT523
= +0.02V
GND
VOUT
–
VREFL
= -0.02V
OP 07
-15V
VOUT = V DPP ( R i+ RF) -Vi R F
Ri
= -4.86V
For R i = RF
VOUT = 2VDPP -Vi
= -4.90V
Bipolar DPP Output
+5V
Ri
RF
+15V
VDD
CONTROL
& DATA
VREFH
–
+
CAT523
GND
VOUT
OP 07
-15V
VREFL
RF
VOUT = (1 + –––) V DPP
RI
Amplified DPP Output
7
Doc. No. 2005, Rev. E
CAT523
APPLICATION CIRCUITS (Cont.)
+5V
VREF
RC = —————
256 * 1 µA
+5V
VDD
VREF
FINE ADJUST
DPP
VDD
Fine adjust gives ± 1 LSB change in V OFFSET
VREF
when V OFFSET = ———
2
VREFH
+VREF
VREFH
127RC
FINE ADJUST
DPP
+
(+VREF ) - (VOFFSET )
RC = ———————————
1 µA
127RC
(-VREF ) + (VOFFSET+ )
Ro = ———————————
1 µA
RC
COARSE ADJUST
DPP
+V
RC
COARSE ADJUST
DPP
V OFFSET
GND
VREFL
Ro
VOFFSET
-VREF
–
GND
+V
+
+
–
VREFL
-V
Coarse-Fine Offset Control by Averaging DPP Outputs
for Single Power Supply Systems
Coarse-Fine Offset Control by Averaging DPP Outputs
for Dual Power Supply Systems
28 - 32V
V+
I > 2 mA
15K
10 µF
1N5231B
VDD
VREF = 5.000V
VREFH
VDD
VREFH
5.1V
10K
CONTROL
& DATA
CAT523
GND
CONTROL
& DATA
LT 1029
VREFL
CAT523
+
GND
–
VREFL
MPT3055EL
LM 324
OUTPUT
4.02 K
1.00K
Digitally Trimmed Voltage Reference
Doc. No. 2005, Rev. E
Digitally Controlled Voltage Reference
8
10 µF
35V
0 - 25V
@ 1A
CAT523
APPLICATION CIRCUITS (Cont.)
+5V
2.2K
VDD
VREFH
4.7 µA
LM385-2.5
ISINK = 2 - 255 mA
+15V
+
DPP
+5V
CONTROL
& DATA
10K
CAT523
1 mA steps
2N7000
–
10K
39Ω1W
39Ω 1W
+
DPP
5 µA steps
2N7000
–
VREFL
GND
5 meg
5 meg
3.9K
10K
10K
–
TIP 30
+
-15V
Current Sink with 4 Decades of Resolution
+15V
51K
+
TIP 29
–
10K
10K
+5V
VDD
VREFH
5 meg
5 meg
39 Ω 1W
DPP
39 Ω 1W
CONTROL
& DATA
–
CAT523
BS170P
+
5 meg
5 meg
1 mA steps
3.9K
DPP
GND
–
VREFL
BS170P
5 µA steps
+
LM385-2.5
-15V
ISOURCE = 2 - 255 mA
Current Source with 4 Decades of Resolution
9
Doc. No. 2005, Rev. E
CAT523
ORDERING INFORMATION
Prefix
Device #
Suffix
CAT
523
J
Optional
Company ID
Product
Number
I
Package
P: PDIP
J: SOIC
L: PDIP (Lead free, Halogen free)
W: SOIC (Lead free, Halogen free)
-TE13
Tape & Reel
TE13: 2000/Reel
Temperature Range
Blank = Commercial (0°C to +70°C)
I = Industrial (-40°C to +85°C)
Notes:
(1) The device used in the above example is a CAT523JI-TE13 (SOIC, Industrial Temperature, Tape & Reel)
Doc. No. 2005, Rev. E
10
CAT523
REVISION HISTORY
Date
Rev.
Reason
3/16/2004
D
Updated Potentiometer Characteristics
7/12/2004
E
Updated Functional Diagram
Updated Potentiometer Characteristics
Added Note 3 to Potentiometer/AC Characteristics tables
Copyrights, Trademarks and Patents
Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:
DPP ™
AE2 ™
Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents
issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000.
CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS
PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE
RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING
OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.
Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or
other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a
situation where personal injury or death may occur.
Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets
labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.
Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate
typical semiconductor applications and may not be complete.
Catalyst Semiconductor, Inc.
Corporate Headquarters
1250 Borregas Avenue
Sunnyvale, CA 94089
Phone: 408.542.1000
Fax: 408.542.1200
www.catsemi.com
Publication #:
Revison:
Issue date:
Type:
11
2005
E
7/12/04
Final
Doc. No. 2005, Rev. E
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