Advance Information CAT523 Configured Digitally Programmable Potentiometer (DPP): Programmable Voltage Applications FEATURES APPLICATIONS ■ Two 8-bit DPPS Configured as Programmable ■ Automated product calibration. Voltages in DAC-like Applications ■ Remote control adjustment of equipment ■ Buffered Wiper Outputs ■ Offset, gain and zero adjustments in Self- ■ Nonvolatile Wiper Storage Calibrating and Adaptive Control systems. ■ Output voltage range includes both supply rails ■ Tamper-proof calibrations. ■ 2 independently addressable output wipers ■ DAC (with memory) substitute ■ 1 LSB Accuracy, High Resolution ■ Serial µP interface ■ Single supply operation: 2.7V-5.5V ■ Setting read-back without effecting outputs DESCRIPTION The CAT523 is a dual, 8-bit digitally-programmable potentiometer configured for programmable voltage and DAC-like applications. Intended for final calibration of products such as camcorders, fax machines and cellular telephones on automated high volume production lines, it is also well suited for systems capable of self calibration, and applications where equipment which is either difficult to access or in a hazardous environment, requires periodic adjustment. effecting the stored settings and stored settings can be read back without disturbing the DAC’s output. Control of the CAT523 is accomplished with a simple 3 wire serial interface. A Chip Select pin allows several CAT523's to share a common serial interface and communication back to the host controller is via a single serial data line thanks to the CAT523’s Tri-Stated Data Output pin. A RDY/BSY output working in concert with an internal low voltage detector signals proper operation of non-volatile Erase/Write cycle. The 2 independently programmable DPPs have a common output voltage range which includes both supply rails. The wipers are buffered by rail to rail OP AMPS. Wiper settings, stored in non-volatile memory, are not lost when the device is powered down and are automatically reinstated when power is returned. Each wiper can be dithered to test new output values without The CAT523 is available in the 0 to 70° C Commercial and –40° C to + 85° C Industrial operating temperature ranges and offered in 14-pin plastic DIP and SOIC mount packages. PIN CONFIGURATION FUNCTIONAL DIAGRAM RDY/BSY 3 PROG 7 V DD VREF H DIP Package (P) 14 1 PROGRAM CONTROL VDD 1 14 CLK 2 13 RDY/BSY 3 CS DI 5 + DATA REGISTER CLK 2 SERIAL CONTROL 13 7KΩ V 1 OUT DI DO AND PROG NONVOLATILE 12 CAT 4 11 523 5 10 6 9 7 8 VREFH VOUT1 VOUT2 NC NC VREFL GND SOIC Package (J) VDD CLK 1 14 2 13 RDY/BSY 3 CS DI DO PROG 12 4 CAT 11 523 5 10 6 9 7 8 VREFH VOUT1 VOUT2 NC NC VREFL GND MEMORY CS 4 + 12 7KΩ SERIAL DATA OUTPUT REGISTER V 2 OUT 6 DO CAT523 8 GND © 2001 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 9 V L REF 1 Doc. No. 25076-00 2/98 M-1 CAT523 Advance Information ABSOLUTE MAXIMUM RATINGS* Junction Temperature ..................................... +150°C Storage Temperature ....................... –65°C to +150°C Lead Soldering (10 sec max) .......................... +300°C Supply Voltage VDD to GND ...................................... –0.5V to +7V Inputs CLK to GND ............................ –0.5V to VDD +0.5V CS to GND .............................. –0.5V to VDD +0.5V DI to GND ............................... –0.5V to VDD +0.5V PROG to GND ........................ –0.5V to VDD +0.5V VREFH to GND ........................ –0.5V to VDD +0.5V VREFL to GND ......................... –0.5V to VDD +0.5V Outputs D0 to GND ............................... –0.5V to VDD +0.5V VOUT 1– 4 to GND ................... –0.5V to VDD +0.5V Operating Ambient Temperature Commercial (‘C’ suffix) .................... 0°C to +70°C Industrial (‘I’ suffix) ...................... – 40°C to +85°C * Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Absolute Maximum Ratings are limited values applied individually while other parameters are within specified operating conditions, and functional operation at any of these conditions is NOT implied. Device performance and reliability may be impaired by exposure to absolute rating conditions for extended periods of time. RELIABILITY CHARACTERISTICS Symbol Parameter Min VZAP(1) ILTH(1)(2) ESD Susceptibility Latch-Up 2000 100 Max Units Test Method Volts mA MIL-STD-883, Test Method 3015 JEDEC Standard 17 NOTES: 1. This parameter is tested initially and after a design or process change that affects the parameter. 2. Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to VCC + 1V. DC ELECTRICAL CHARACTERISTICS: VDD = +2.7 to +5.5V, VREFH = VDD, VREFL = 0V, unless otherwise specified Symbol Parameter Conditions Min Typ Max 8 — — Bits ILOAD = 10 µA, TR = C TR = I ILOAD = 40 µA, TR = C TR = I ILOAD = 10 µA, TR = C TR = I ILOAD = 40 µA, TR = C TR = I — — — — — — — — — — — — — — — — ±1 ±1 ±2 ±2 ± 0.5 ± 0.5 ± 1.5 ± 1.5 LSB LSB LSB LSB LSB LSB LSB LSB VIN = VDD VIN = 0V — — 2 0 — — — — 10 –10 VDD 0.8 µA µA V V 2.7 GND — — — 7k VDD VDD -2.7 — V V Ω VDD –0.3 — — — — 0.4 V V — — 0.4 V Resolution Units Accuracy INL Integral Linearity Error DNL Differential Linearity Error Logic Inputs IIH IIL VIH VIL Input Leakage Current Input Leakage Current High Level Input Voltage Low Level Input Voltage References VRH VRL ZIN VREFH Input Voltage Range VREFL Input Voltage Range VREFH–VREFL Resistance Logic Outputs VOH VOL High Level Output Voltage Low Level Output Voltage IOH = – 40 µA IOL = 1 mA, VDD = +5V IOL = 0.4 mA, VDD = +3V 2 CAT523 Advance Information DC ELECTRICAL CHARACTERISTICS (Cont.): VDD = +2.7V to +5.5V , VREFH = +VDD, VREFL = 0V, unless otherwise specified Symbol Parameter Conditions Min Typ Max Units 0.99 VR — — — — — 0.995 VR 0.005 VR — — — — — 0.01 VR 1 100k 150k 1 V V µA Ω Ω LSB / V VREFH = +5V, VREFL = 0V — — 200 µV/ °C VDD = +5V, ILOAD = 250nA VREFH to VREFL — 700 — — — — 2.7 400 1600 1000 — 600 2500 1600 5.5 µA µA µA V Min Typ Max Units 150 100 0 50 50 — — — — — 700 150 500 300 DC — — — — — — — 400 4 400 — — — — — — — — — — 150 150 — 5 — — — — — 1 ns ns ns ns ns ns ns ns ms ns ns ns ns ns MHz CLOAD = 10 pF, VDD = +5V CLOAD = 10 pF, VDD = +3V — — 3 6 10 10 µs µs VIN = 0V, f = 1 MHz(2) VOUT = 0V, f = 1 MHz(2) — — 8 6 — — pF pF Analog Output FSO ZSO IL ROUT Full-Scale Output Voltage Zero-Scale Output Voltage DAC Output Load Current DAC Output Impedance PSSR Power Supply Rejection VR = VREFH–VREFL VR = VREFH–VREFL VDD = +5V VDD = +3V ILOAD = 250 nA Temperature TCO VOUT Temperature Coefficient TCREF Temperature Coefficient of VREF Resistance ppm / °C Power Supply IDD1 IDD2 Supply Current (Read) Supply Current (Write) VDD Operating Voltage Range Normal Operating VDD=5V VDD=3V AC ELECTRICAL CHARACTERISTICS: VDD = +2.7V to +5.5V, VREFH = +VDD, VREFL = 0V, unless otherwise specified Symbol Parameter Conditions Digital tCSMIN tCSS tCSH tDIS tDIH tDO1 tDO0 tHZ tBusy tLZ tPROG tPS tCLKH tCLKL fC Minimum CS Low Time CS Setup Time CS Hold Time DI Setup Time DI Hold Time Output Delay to 1 Output Delay to 0 Output Delay to High-Z Erase/Write Cycle Time Output Delay to Low-Z Erase/Write Pulse Width PROG Setup Time Minimum CLK High Time Minimum CLK Low Time Clock Frequency CL = 100 pF, see note 1 Analog tDS DAC Settling Time to 1/2 LSB Pin Capacitance CIN COUT Input Capacitance Output Capacitance NOTES: 1. All timing measurements are defined at the point of signal crossing VDD / 2. 2. These parameters are periodically sampled and are not 100% tested. 3 CAT523 Advance Information A. C. TIMING DIAGRAM to 1 2 3 4 5 t CLK H CLK t CSS t CLK L t CSH CS t CSMIN t DIS DI t DIH t DO0 t LZ DO t HZ t DO1 PROG t PS t PROG RDY/BSY t to 1 2 3 4 BUSY 4 5 CAT523 Advance Information PIN DESCRIPTION Pin Name 1 2 3 4 5 6 7 VDD CLK RDY/BSY CS DI DO PROG 8 9 10 11 12 13 14 GND VREFL NC NC VOUT2 VOUT1 VREFH DAC addressing is as follows: Function Power supply positive. Clock input pin.Clock input pin. Ready/Busy Output Chip Select Serial data input pin. Serial data output pin. EEPROM Programming Enable Input Power supply ground. Minimum DAC output voltage. No Connect. No Connect. DAC output channel 2. DAC output channel 1. Maximum DAC output voltage. DEVICE OPERATION DAC OUTPUT A0 A1 VOUT1 0 0 VOUT2 1 0 read to or from the chip, and the Data Output (DO) pin is active. Data loaded into the DAC control registers will remain in effect until CS goes low. Bringing CS to a logic low returns all DAC outputs to the settings stored in EEPROM memory and switches DO to its high impedance Tri-State mode. The CAT523 is a quad 8-bit Digital to Analog Converter (DAC) whose outputs can be programmed to any one of 256 individual voltage steps. Once programmed, these output settings are retained in non-volatile EEPROM memory and will not be lost when power is removed from the chip. Upon power up the DACs return to the settings stored in EEPROM memory. Each DAC can be written to and read from independently without effecting the output voltage during the read or write cycle. Each output can also be temporarily adjusted without changing the stored output setting, which is useful for testing new output settings before storing them in memory. Because CS functions like a reset the CS pin has been equipped with a 30 ns to 90 ns filter circuit to prevent noise spikes from causing unwanted resets and the loss of volatile data. CLOCK The CAT523’s clock controls both data flow in and out of the IC and EEPROM memory cell programming. Serial data is shifted into the DI pin and out of the DO pin on the clock’s rising edge. While it is not necessary for the clock to be running between data transfers, the clock must be operating in order to write to EEPROM memory, even though the data being saved may already be resident in the DAC control register. DIGITAL INTERFACE The CAT523 employs a standard 3 wire serial control interface consisting of Clock (CLK), Chip Select (CS) and Data In (DI) inputs. For all operations, address and data are shifted in LSB first. In addition, all digital data must be preceded by a logic “1” as a start bit. The DAC address and data are clocked into the DI pin on the clock’s rising edge. When sending multiple blocks of information a minimum of two clock cycles is required between the last block sent and the next start bit. No clock is necessary upon system power-up. The CAT523’s internal power-on reset circuitry loads data from EEPROM to the DACs without using the external clock. Multiple devices may share a common input data line by selectively activating the CS control of the desired IC. Data Outputs (DO) can also share a common line because the DO pin is Tri-Stated and returns to a high impedance when not in use. As data transfers are edge triggered clean clock transitions are necessary to avoid falsely clocking data into the control registers. Standard CMOS and TTL logic families work well in this regard and it is recommended that any mechanical switches used for breadboarding or device evaluation purposes be debounced by a flip-flop or other suitable debouncing circuit. CHIP SELECT Chip Select (CS) enables and disables the CAT523’s read and write operations. When CS is high data may be 5 CAT523 Advance Information complished through the control signals: Chip Select (CS) and Program (PROG). With CS high, a start bit followed by a two bit DAC address and eight data bits are clocked into the DAC control register via the DI pin. Data enters on the clock’s rising edge. The DAC output changes to its new setting on the clock cycle following D7, the last data bit. VREF VREF, the voltage applied between pins VREFH andVREFL, sets the DAC’s Zero to Full Scale output range where VREFL = Zero and VREFH = Full Scale. VREF can span the full power supply range or just a fraction of it. In typical applications VREFH andVREFL are connected across the power supply rails. When using less than the full supply voltage VREFH is restricted to voltages between VDD and VDD/2 and VREFL to voltages between GND and VDD/2. Programming is achieved by bringing PROG high for a minimum of 3 ms. PROG must be brought high sometime after the start bit and at least 150 ns prior to the rising edge of the clock cycle immediately following the D7 bit. Two clock cycles after the D7 bit the DAC control register will be ready to receive the next set of address and data bits. The clock must be kept running throughout the programming cycle. Internal control circuitry takes care of ramping the programming voltage for data transfer to the EEPROM cells. The CAT523’s EEPROM memory cells will endure over 100,000 write cycles and will retain data for a minimum of 100 years without being refreshed. /BUSY READY/BUSY When saving data to non-volatile EEPROM memory, the Ready/Busy ouput (RDY/BSY) signals the start and duration of the EEPROM erase/write cycle. Upon receiving a command to store data (PROG goes high) RDY/ BSY goes low and remains low until the programming cycle is complete. During this time the CAT523 will ignore any data appearing at DI and no data will be output on DO. RDY/BSY is internally ANDed with a low voltage detector circuit monitoring VDD. If VDD is below the minimum value required for EEPROM programming, RDY/BSY will remain high following the program command indicating a failure to record the desired data in non-volatile memory. READING DATA Each time data is transferred into a DAC control register currently held data is shifted out via the D0 pin, thus in every data transaction a read cycle occurs. Note, however, that the reading process is destructive. Data must be removed from the register in order to be read. Figure 2 depicts a Read Only cycle in which no change occurs in the DAC’s output. This feature allows µPs to poll DACs for their current setting without disturbing the output voltage but it assumes that the setting being read is also stored in EEPROM so that it can be restored at the end of the read cycle. In Figure 2 CS returns low before the 13th clock cycle completes. In doing so the EEPROM’s setting is reloaded into the DAC control register. Since DATA OUTPUT Data is output serially by the CAT523, LSB first, via the Data Out (DO) pin following the reception of a start bit and two address bits by the Data Input (DI). DO becomes active whenever CS goes high and resumes its high impedance Tri-State mode when CS returns low. Tri-Stating the DO pin allows several 523s to share a single serial data line and simplifies interfacing multiple 523s to a microprocessor. WRITING TO MEMORY Programming the CAT523’s EEPROM memory is acFigure 1. Writing to Memory to 1 2 3 4 5 6 7 8 9 Figure 2. Reading from Memory 10 11 12 N N+1 N+2 to 1 2 3 4 5 6 7 8 9 10 11 12 CS CS NEW DAC DATA DI 1 A0 A1 D0 D1 D0 D1 D2 D3 D4 D5 D6 D7 D6 D7 DI CURRENT DAC DATA DO D2 D3 D4 D5 1 A0 A1 CURRENT DAC DATA DO D0 D1 D2 D3 D4 D5 PROG PROG RDY/BSY DAC OUTPUT CURRENT DAC VALUE NON-VOLATILE NEW DAC VALUE VOLATILE DAC OUTPUT NEW DAC VALUE NON-VOLATILE 6 CURRENT DAC VALUE NON-VOLATILE D6 D7 CAT523 Advance Information this feature, the new value must be reloaded into the DAC control register prior to programming. This is because the CAT523’s internal control circuitry discards the new data from the programming register two clock cycles after receiving it (after reception is complete) if no PROG signal is received. this value is the same as that which had been there previously no change in the DAC’s output is noticed. Had the value held in the control register been different from that stored in EEPROM then a change would occur at the read cycle’s conclusion. TEMPORARILY CHANGE OUTPUT Figure 3. Temporary Change in Output The CAT523 allows temporary changes in DAC’s output to be made without disturbing the settings retained in EEPROM memory. This feature is particularly useful when testing for a new output setting and allows for user adjustment of preset or default values without losing the original factory settings. to 1 2 3 4 5 6 7 8 9 10 11 12 N N+1 N+2 CS NEW DAC DATA 1 DI Figure 3 shows the control and data signals needed to effect a temporary output change. DAC settings may be changed as many times as required and can be made to any of the four DACs in any order or sequence. The temporary setting(s) remain in effect long as CS remains high. When CS returns low all four DACs will return to the output values stored in EEPROM memory. A0 A1 D0 D1 D2 D3 D4 D5 D6 D7 D6 D7 CURRENT DAC DATA D0 DO D1 D2 D3 D4 D5 PROG CURRENT DAC VALUE NON-VOLATILE NEW DAC VALUE VOLATILE CURRENT DAC VALUE NON-VOLATILE DAC OUTPUT When it is desired to save a new setting acquired using APPLICATION CIRCUITS DAC INPUT DAC OUTPUT ANALOG OUTPUT +5V CODE (V - V VDAC = ——— FS ZERO ) + V ZERO 255 MSB LSB VFS = 0.99 VREF VZERO = 0.01 V REF Vi 1111 1111 255 (.98 V —— REF) + .01 VREF = .990 V REF 255 1000 0000 128 (.98 V —— ) + .01 V = .502 V REF REF REF 255 127 —— (.98 V ) + .01 V = .498 V 255 REF REF REF 1 (.98 V —— ) + .01 V = .014 V 255 REF REF REF V 0 (.98 V —— ) + .01 V = .010 V REF REF REF 255 0111 1111 0000 0001 0000 0000 Ri VREF = 5V R I = RF V OUT= +4.90V +15V VDD CONTROL & DATA = +0.02V OUT VREF H OPT 504 CAT523 GND VREF L VOUT – + OP 07 -15V V = -0.02V OUT V = -4.86V OUT VOUT = V DAC ( R i+ RF) -Vi R F Ri V = -4.90V OUT For R i = RF VOUT = 2VDAC -Vi Bipolar DAC Output +5V Ri RF +15V VDD CONTROL & DATA RF VREF H – CAT523 OPT 504 GND + VOUT OP 07 -15V VREF L RF VOUT = (1 + –––) V DAC RI Amplified DAC Output 7 CAT523 Advance Information APPLICATION CIRCUITS (Cont.) +5V VREF RC = ————— 256 * 1 µA +5V VDD VREF VREFH +VREF VDD Fine adjust gives ± 1 LSB change in V OFFSET VREF when VOFFSET = ——— 2 VREFH 127RC FINE ADJUST DAC + (+VREF ) - (VOFFSET ) RC = ——————————— 1 µA 127RC FINE ADJUST DAC (-VREF ) + (VOFFSET+ ) Ro = ——————————— 1 µA +V RC COARSE ADJUST DAC V OFFSET RC COARSE ADJUST DAC + GND VREF L +V Ro – GND VOFFSET -VREF VREF L + – -V Coarse-Fine Offset Control by Averaging DAC Outputs for Single Power Supply Systems Coarse-Fine Offset Control by Averaging DAC Outputs for Dual Power Supply Systems 28 - 32V V+ I > 2 mA 15K 10 µF VDD VREF H 1N5231B VREF = 5.000V VDD VREF H 5.1V 10K CONTROL & DATA CAT523 OPT 504 GND CONTROL & DATA LT 1029 CAT523 OPT 504 GND VREF L VREF L + – MPT3055EL LM 324 OUTPUT 4.02 K 1.00K Digitally Trimmed Voltage Reference Digitally Controlled Voltage Reference 8 10 µF 35V 0 - 25V @ 1A CAT523 Advance Information APPLICATION CIRCUITS (Cont.) +5V 2.2K VDD VREF 4.7 µA LM385-2.5 ISINK = 2 - 255 mA +15V DAC + +5V CONTROL & DATA 10K OPT 504 CAT523 1 mA steps 2N7000 – 10K 39Ω1W 39Ω 1W DAC + 5 µA steps 2N7000 – VREF L GND 5 meg 5 meg 3.9K 10K 10K – TIP 30 + -15V Current Sink with 4 Decades of Resolution +15V 51K + TIP 29 – 10K 10K +5V VDD VREF H 5 meg 5 meg 39Ω 1W DAC 39Ω 1W CONTROL & DATA – OPT 504 CAT523 5 meg DAC GND BS170P + 5 meg 1 mA steps 3.9K – VREF L BS170P 5 µA steps + LM385-2.5 -15V ISOURCE = 2 - 255 mA Current Source with 4 Decades of Resolution 9 CAT523 Advance Information ORDERING INFORMATION Prefix Device # Suffix CAT 523 J Optional Company ID Product Number Package P: PDIP J: SOIC I -TE13 Tape & Reel TE13: 2000/Reel Temperature Range Blank = Commercial (0˚C to +70˚C) I = Industrial (-40˚C to +85˚C) Notes: (1) The device used in the above example is a CAT523JI-TE13 (SOIC, Industrial Temperature, Tape & Reel) 10