CATALYST CAT5411YI-00

CAT5411
Dual Digitally Programmable Potentiometers (DPP™)
with 64 Taps and SPI Interface
FEATURES
DESCRIPTION
„ Two linear-taper digitally programmable
potentiometers
The CAT5411 is two Digitally Programmable
Potentiometers (DPPs™) integrated with control logic
and 16 bytes of NVRAM memory. Each DPP consists
of a series of 63 resistive elements connected
between two externally accessible end points. The tap
points between each resistive element are connected
to the wiper outputs with CMOS switches. A separate
6-bit control register (WCR) independently controls
the wiper tap switches for each DPP. Associated with
each wiper control register are four 6-bit non-volatile
memory data registers (DR) used for storing up to four
wiper settings. Writing to the wiper control register or
any of the non-volatile data registers is via a SPI serial
bus. On power-up, the contents of the first data
register (DR0) for each of the two potentiometers is
automatically loaded into its respective wiper control
register.
„ 64 resistor taps per potentiometer
„ End to end resistance 2.5kΩ, 10kΩ, 50kΩ or
100kΩ
„ Potentiometer control and memory access via
SPI interface: Mode (0, 0) and (1, 1)
„ Low wiper resistance, typically 80
„ Nonvolatile memory storage for up to four
wiper settings for each potentiometer
„ Automatic recall of saved wiper settings at
power up
„ 2.5 to 6.0 volt operation
„ Standby current less than 1µA
„ 24-lead SOIC and 24-lead TSSOP
„ Industrial temperature ranges
The CAT5411 can be used as a potentiometer or as a
two terminal, variable resistor. It is intended for circuit
level or system level adjustments in a wide variety of
applications.
PIN CONFIGURATION
FUNCTIONAL DIAGRAM
SOIC (W)
(top view)
TSSOP (Y)
(top view)
RH0
VCC
1
24
NC
SI
1
24
¯¯¯
WP
RL0
2
23
NC
A1
2
23
¯¯¯
CS
RH0
3
22
NC
RL1
3
22
RW0
RW0
4
21
NC
RH1
4
21
RH0
¯¯¯
CS
5
20
A0
RW1
5
20
RL0
¯¯¯
WP
6
SO
GND
6
7
¯¯¯¯¯
HOLD
NC
7
CAT 19
5411 18
VCC
SI
CAT 19
5411 18
A1
8
17
SCK
NC
8
17
NC
RL1
9
16
NC
NC
9
16
NC
RH1
10
15
NC
NC
10
15
NC
RW1
11
14
NC
SCK
11
14
A0
NC
¯¯¯¯¯
HOLD
12
13
SO
GND
12
13
CS
SCK
SI
SO
SPI BUS
INTERFACE
RH1
WIPER
CONTROL
REGISTERS
RW0
RW1
WP
A0
A1
NC
CONTROL
LOGIC
NONVOLATILE
DATA
REGISTERS
RL0
RL1
For Ordering Information details, see page 15.
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 2114 Rev. H
CAT5411
PIN DESCRIPTIONS
SI: Serial Input
Pin
SOIC
Pin
TSSOP
Name
1
19
VCC
2
20
RL0
SO: Serial Output
SO is the serial data output pin. This pin is used to transfer
data out of the CAT5411. During a read cycle, data is
shifted out on the falling edge of the serial clock.
3
21
RH0
4
22
RW0
5
23
SCK: Serial Clock
SCK is the serial clock pin. This pin is used to synchronize
the communication between the microcontroller and the
CAT5411. Opcodes, byte addresses or data present on
the SI pin are latched on the rising edge of the SCK. Data
on the SO pin is updated on the falling edge of the SCK.
6
24
¯¯¯
CS
¯¯¯
WP
A0, A1: Device Address Inputs
These inputs set the device address when addressing
multiple devices. A total of four devices can be addressed
on a single bus. A match in the slave address must be
made with the address input in order to initiate
communication with the CAT5411.
SI is the serial data input pin. This pin is used to input all
opcodes, byte addresses and data to be written to the
CAT5411. Input data is latched on the rising edge of the
serial clock.
RH, RL: Resistor End Points
The four sets of RH and RL pins are equivalent to the
terminal connections on a mechanical potentiometer.
RW: Wiper
The four RW pins are equivalent to the wiper terminal of a
mechanical potentiometer.
¯¯¯:
CS Chip Select
CAT5251 and ¯¯¯
CS high disables the CAT5411. ¯¯¯
CS high
takes the SO output pin to high impedance and forces the
devices into a Standby mode (unless an internal write
operation is underway). The CAT5411 draws ZERO
current in the Standby mode. A high to low transition on
¯¯¯
CS is required prior to any sequence being initiated. A low
to high transition on ¯¯¯
CS after a valid write sequence is
what initiates an internal write cycle.
Supply Voltage
Low Reference Terminal for
Potentiometer 0
High Reference Terminal for
Potentiometer 0
Wiper Terminal for
Potentiometer 0
Chip Select
Write Protection
7
1
SI
Serial Input
8
2
A1
Device Address
9
3
RL1
10
4
RH1
11
5
RW1
Wiper Terminal for
Potentiometer 1
12
6
GND
Ground
13
7
NC
No Connect
14
8
NC
No Connect
15
9
NC
No Connect
16
10
NC
No Connect
17
11
SCK
18
12
¯¯¯¯¯
HOLD
19
13
SO
Serial Data Output
20
14
A0
Device Address, LSB
21
15
NC
No Connect
22
16
NC
No Connect
23
17
NC
No Connect
24
18
NC
No Connect
Low Reference Terminal for
Potentiometer 1
High Reference Terminal for
Potentiometer 1
Bus Serial Clock
Hold
¯¯¯¯¯ : Hold
HOLD
¯¯¯¯¯ pin is used to pause transmission to the
The HOLD
CAT5411 while in the middle of a serial sequence without
having to re-transmit entire sequence at a later time. To
¯¯¯¯¯ must be brought low while SCK is low. The
pause, HOLD
SO pin is in a high impedance state during the time the part
is paused, and transitions on the SI pins will be ignored. To
¯¯¯¯¯ is brought high, while SCK
resume communication, HOLD
¯¯¯¯¯
is low. (HOLD should be held high any time this function is
¯¯¯¯¯ may be tied high directly to VCC or
not being used.) HOLD
tied to VCC through a resistor.
¯¯¯
WP: Write Protect
¯¯¯
WP is the Write Protect pin. The Write Protect pin will
allow normal read/write operations when held high.
When ¯¯¯
WP is tied low, all non-volatile write operations to
the Data registers are inhibited (change of wiper control
register is allowed). ¯¯¯
WP going low while ¯¯¯
CS is still low will
interrupt a write to the registers. If the internal write cycle
has already been initiated, ¯¯¯
WP going low will have no
effect on any write operation.
Doc. No. 2114 Rev. H
Function
2
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT5411
DEVICE OPERATION
SERIAL BUS PROTOCOL
The CAT5411 is two resistor arrays integrated with
SPI serial interface logic, four 6-bit wiper control
registers and eight 6-bit, non-volatile memory data
registers. Each resistor array contains 63 separate
resistive elements connected in series. The physical
ends of each array are equivalent to the fixed
terminals of a mechanical potentiometer (RH and RL).
RH and RL are symmetrical and may be interchanged.
The tap positions between and at the ends of the
series resistors are connected to the output wiper
terminals (RW) by a CMOS transistor switch. Only one
tap point for each potentiometer is connected to its
wiper terminal at a time and is determined by the
value of the wiper control register. Data can be read
or written to the wiper control registers or the nonvolatile memory data registers via the SPI bus.
Additional instructions allow data to be transferred
between the wiper control registers and each
respective potentiometer's non-volatile data registers.
Also, the device can be instructed to operate in an
"increment/decrement" mode.
The CAT5041 supports the SPI bus data transmission
protocol. The synchronous Serial Peripheral Interface
(SPI) helps the CAT5411 to interface directly with
many of today's popular microcontrollers. The
CAT5041 contains an 8-bit instruction register .The
instruction set and the operation codes are detailed in
the instruction set table 3.
After the device is selected with ¯¯¯
CS going low the first
byte will be received. The part is accessed via the SI
pin, with data being clocked in on the rising edge of
SCK. The first byte contains one of the six op-codes
that define the operation to be performed.
RELIABILITY CHARACTERISTICS
Over recommended operating conditions unless otherwise stated.
Symbol
Parameter
Reference Test Method
(1)
Endurance
MIL-STD-883, Test Method 1033
1,000,000
Cycles/Byte
(1)
Data Retention
MIL-STD-883, Test Method 1008
100
Years
ESD Susceptibility
MIL-STD-883, Test Method 3015
2000
Volts
Latch-Up
JEDEC Standard 17
100
mA
NEND
TDR
VZAP(1)
ILTH(1)
Min
Typ
Max
Units
Notes:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
3
Doc. No. 2114 Rev. H
CAT5411
ABSOLUTE MAXIMUM RATINGS(1)
RECOMMENDED OPERATING CONDITIONS
Parameters
Temperature Under Bias
Storage Temperature
R
Voltage to any Pins with
Ratings
-55 to +125
-65 to +150
Units
ºC
ºC
Respect to VSS (2) (3)
-2.0 to VCC
+2.0
V
VCC with Respect to GND
-2.0 to +7.0
V
Package Power Dissipation Capability (TA = 25°C)
1.0
W
Lead Soldering
Temperature (10s)
300
ºC
Wiper Current
±12
mA
Parameters
VCC
Industrial Temperature
Ratings
+2.5 to 6.0
-40 to +85
Units
V
ºC
Notes:
(1) Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. These
are stress ratings only, and functional operation of the device
at these or any other conditions outside of those listed in the
operational sections of this specification is not implied.
Exposure to any absolute maximum rating for extended
periods may affect device performance and reliability.
(2)
The minimum DC input voltage is –0.5V. During transitions,
inputs may undershoot to –2.0V for periods of less than 20 ns.
Maximum DC voltage on output pins is VCC +0.5V, which may
overshoot to VCC +2.0V for periods of less than 20 ns.
(3)
Latch-up protection is provided for stresses up to 100 mA on
address and data pins from –1V to VCC +1V.
POTENTIOMETER CHARACTERISTICS
Over recommended operating conditions unless otherwise stated.
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
RPOT
Potentiometer Resistance (-00)
100
kΩ
RPOT
Potentiometer Resistance (-50)
50
kΩ
RPOT
Potentiometer Resistance (-10)
10
kΩ
RPOT
Potentiometer Resistance (-2.5)
2.5
kΩ
Potentiometer Resistance
Tolerance
RPOT Matching
Power Rating
25°C, each pot
IW
Wiper Current
RW
Wiper Resistance
IW = +3mA @ VCC = 3V
RW
Wiper Resistance
IW = +3mA @ VCC = 5V
Voltage on any RH or RL Pin
VSS
(1)
VTERM
VN
Noise
= 0V
GND
TCRPOT
TCRATIO
CH/CL/CW
fc
%
1
%
50
mW
+6
mA
300
Ω
150
Ω
VCC
V
nV/√Hz
Resolution
Absolute Linearity
80
+20
1.6
(2)
RW(n)(actual)-R(n)(expected)
Relative Linearity (3)
RW(n+1)-[RW(n)+LSB](5)
Temperature Coefficient of RPOT
(1)
Ratiometric Temp. Coefficient
(1)
Potentiometer Capacitances
(1)
Frequency Response
(5)
%
+1
LSB (4)
+0.2
LSB (4)
+300
ppm/°C
20
(1)
RPOT = 50kΩ
ppm/°C
10/10/25
pF
0.4
MHz
Notes:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) Absolute linearity is utilitzed to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a
potentiometer.
(3) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a
potentiometer. It is a measure of the error in step size.
(4) LSB = RTOT / 63 or (RH - RL) / 63, single pot
(5) n = 0, 1, 2, ..., 63
Doc. No. 2114 Rev. H
4
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT5411
D.C. OPERATING CHARACTERISTICS
Over recommended operating conditions unless otherwise stated.
Symbol
Parameter
ICC
Power Supply Current
ISB
Standby Current (VCC = 5.0V)
Test Conditions
fSCK = 2MHz, SO
Open Inputs = GND
VIN = GND or VCC; SO Open
Min
ILI
Input Leakage Current
VIN = GND to VCC
10
µA
ILO
Output Leakage Current
VOUT = GND to VCC
10
µA
VIL
Input Low Voltage
-1
VCC x 0.3
V
VIH
Input High Voltage
VCC x 0.7
VCC + 1.0
V
VOL1
Output Low Voltage (VCC = 3.0V)
0.4
V
IOL = 3 mA
Max
Units
1
mA
1
µA
PIN CAPACITANCE (1)
Applicable over recommended operating range from TA = 25˚C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted).
Symbol
COUT
CIN
Test Conditions
Min
Typ
Max
Units
Conditions
Output Capacitance (SO)
8
pF
VOUT = 0V
¯¯¯¯¯)
Input Capacitance (¯¯¯
CS , SCK, SI, ¯¯¯
WP, HOLD
6
pF
VIN = 0V
Min
Typ
Max
Units
POWER UP TIMING (1)
Over recommended operating conditions unless otherwise stated.
Symbol
tPUR
Parameter
(2)
Power-up to Read Operation
1
ms
(2)
Power-up to Write Operation
1
ms
tPUW
Note:
(1)
This parameter is tested initially and after a design or process change that affects the parameter.
(2)
tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
5
Doc. No. 2114 Rev. H
CAT5411
ELECTRICAL CHARACTERISTICS
Over recommended operating conditions unless otherwise stated.
Symbol
Parameter
Min
Typ
Max
Units
tSU
Data Setup Time
50
ns
tH
Data Hold Time
50
ns
tWH
SCK High Time
125
ns
tWL
SCK Low Time
125
ns
fSCK
Clock Frequency
DC
tLZ
3
MHz
¯¯¯¯¯ to Output Low Z
HOLD
50
ns
tRI(1)
Input Rise Time
2
µs
tFI(1)
Input Fall Time
2
µs
tHD
¯¯¯¯¯ Setup Time
HOLD
100
ns
tCD
¯¯¯¯¯ Hold Time
HOLD
100
ns
tWC
Write Cycle Time
5
ms
250
ns
tV
Output Valid from Clock Low
tHO
Output Hold Time
tDIS
Output Disable Time
250
ns
tHZ
¯¯¯¯¯ to Output High Z
HOLD
100
ns
tCS
¯¯¯
CS High Time
250
ns
tCSS
¯¯¯
CS Setup Time
250
ns
tCSH
¯¯¯
CS Hold Time
250
ns
0
Test Conditions
CL = 50pF
ns
POTENTIOMETER AC CHARACTERISTICS
Symbol
Parameter
Max
Units
tWRL
Wiper response time after instruction issued (all load instructions)
10
µs
tWRID
Wiper response time from an active SCL/SCK edge (Increment/decrement instruction)
5
µs
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
Doc. No. 2114 Rev. H
6
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT5411
Figure 1: Synchronous Data Timing
tCS
VIH
CS
VIL
tCSH
tCSS
SCK
VIH
tWH
VIL
tH
tSU
VIH
tWL
VALID IN
SI
VIL
tRI
tFI
tV
SO
VOH
tHO
tDIS
HI-Z
HI-Z
VOL
¯¯¯¯¯ Timing
Figure 2: HOLD
CS
tCD
tCD
SCK
tHD
tHD
HOLD
tHZ
HIGH IMPEDANCE
SO
tLZ
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
7
Doc. No. 2114 Rev. H
CAT5411
INSTRUCTION AND REGISTER
DESCRIPTION
INSTRUCTION BYTE
The next byte sent to the CAT5411 contains the
instruction and register pointer information. The four
most significant bits used provide the instruction
opcode I [3:0]. The R1 and R0 bits point to one of the
four data registers of each associated potentiometer.
The least two significant bits point to one of two Wiper
Control Registers. The format is shown in Table 2.
DEVICE TYPE / ADDRESS BYTE
The first byte sent to the CAT5411 from the master/
processor is called the Device Address Byte. The
most significant four bits of the Device Type address
are a device type identifier. These bits for the
CAT5411 are fixed at 0101[B] (refer to Table 1).
Data Register Selection
The two least significant bits in the slave address
byte, A1 - A0, are the internal slave address and must
match the physical device address which is defined by
the state of the A1 - A0 input pins for the CAT5411 to
successfully continue the command sequence. Only
the device which slave address matches the incoming
device address sent by the master executes the
instruction. The A1 - A0 inputs can be actively driven
by CMOS input signals or tied to VCC or VSS. The
remaining two bits in the device address byte must be
set to 0.
Data Register Selected
R1
R0
DR0
0
0
DR1
0
1
DR2
1
0
DR3
1
1
Table 1. Identification Byte Format 0 1 0 Device Type Identifier (MSB)
Device Type
Identifier
ID3
0
ID2
1
ID1
0
Slave Address
ID0
1
0
0
A1
(MSB)
A0
(LSB)
Table 2. Instruction Byte Format
Instruction
Opcode
I3
(MSB)
I2
Data Register
Selection
I1
I0
R1
WCR/Pot Selection
R0
P1
P0
(LSB)
Figure 3. Potentiometer Timing (for All Load Instructions)
CS
SCK
SI
•••
MSB
•••
tWRL
LSB
VW/RW
SO
Doc. No. 2114 Rev. H
High Impedance
8
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT5411
WIPER CONTROL AND DATA REGISTERS
Wiper Control Register (WCR)
The CAT5411 contains two 6-bit Wiper Control
Registers, one for each potentiometer. The Wiper
Control Register output is decoded to select one of 64
switches along its resistor array. The contents of the
WCR can be altered in four ways: it may be written by
the host via Write Wiper Control Register instruction; it
may be written by transferring the contents of one of
four associated Data Registers via the XFR Data
Register instruction, it can be modified one step at a
time by the Increment/decrement instruction (see
Instruction section for more details). Finally, it is
loaded with the content of its data register zero (DR0)
upon power-up.
Write in Process
The contents of the Data Registers are saved to
nonvolatile memory when the ¯¯¯
CS input goes HIGH
after a write sequence is received. The status of the
internal write cycle can be monitored by issuing a
Read Status command to read the Write in Process
(WIP) bit.
The Wiper Control Register is a volatile register that
loses its contents when the CAT5411 is powereddown. Although the register is automatically loaded
with the value in DR0 upon power-up, this may be
different from the value present at power-down.
— Write Wiper Control Register – change current
wiper position in the WCR of the selected
potentiometer
INSTRUCTIONS
Four of the ten instructions are three bytes in length.
These instructions are:
— Read Wiper Control Register – read the current
wiper position of the selected potentiometer in
the WCR
— Read Data Register – read the contents of the
selected Data Register
Data Registers (DR)
Each potentiometer has four 6-bit non-volatile Data
Registers. These can be read or written directly by the
host. Data can also be transferred between any of the
four Data Registers and the associated Wiper Control
Register. Any data changes in one of the Data
Registers is a non-volatile operation and will take a
maximum of 5ms.
— Write Data Register – write a new value to the
selected Data Register
— Read Status – Read the status of the WIP bit
which when set to "1" signifies a write cycle is in
progress.
Table 3. Instruction Set
Note: 1/0 = data is one or zero
Instruction Set
Instruction
Operations
I3
I2
I1
I0
R1
R0
0
WCR0/ P0
Read Wiper Control Register 1
0
0
1
0
0
0
1/0
Write Wiper Control Register
1
0
1
0
0
0
0
1/0
Read Data Register
1
0
1
1 1/0 1/0
0
1/0
Write Data Register
1
1
0
0 1/0 1/0
0
1/0
XFR Data Register to Wiper
Control Register
1
1
0
1 1/0 1/0
0
1/0
XFR Wiper Control Register
to Data Register
1
1
1
0 1/0 1/0
0
1/0
Global XFR Data Registers
to Wiper Control Registers
0
0
0
1 1/0 1/0
0
0
Global XFR Wiper Control
Registers to Data Register
1
0
0
0 1/0 1/0
0
0
0
0
1
0
0
0
0
1/0
Enable Increment/decrement of the Control Latch
pointed to by P1-P0
0
1
0
1
0
0
0
1
Read WIP bit to check internal write cycle status
Increment/Decrement Wiper
Control Register
Read Status
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
9
Read the contents of the Wiper Control Register
pointed to by P1-P0
Write new value to the Wiper Control Register
pointed to by P1-P0
Read the contents of the Data Register pointed to by
P1-P0 and R1-R0
Write new value to the Data Register pointed to by
P1-P0 and R1-R0
Transfer the contents of the Data Register pointed to
by P1-P0 and R1-R0 to its associated Wiper Control
Register
Transfer the contents of the Wiper Control Register
pointed to by P1-P0 to the Data Register pointed to
by R1-R0
Transfer the contents of the Data Registers pointed to
by R1-R0 of all four pots to their respective Wiper
Control Registers
Transfer the contents of both Wiper Control Registers
to their respective data Registers pointed to by
R1-R0 of all four pots
Doc. No. 2114 Rev. H
CAT5411
The basic sequence of the three byte instructions is
illustrated in Figure 5. These three-byte instructions
exchange data between the WCR and one of the Data
Registers. The WCR controls the position of the wiper.
The response of the wiper to this action will be
delayed by tWRL. A transfer from the WCR (current
wiper position), to a Data Register is a write to nonvolatile memory and takes a minimum of tWR to
complete. The transfer can occur between one of the
four potentiometers and one of its associated
registers; or the transfer can occur between all
potentiometers and one associated register.
— Global XFR Data Register to Wiper Control
Register
This transfers the contents of all specified Data
Registers to the associated Wiper Control
Registers.
— Global XFR Wiper Counter Register to Data
Register
This transfers the contents of all Wiper Control
Registers to the specified associated Data
Registers.
INCREMENT/DECREMENT COMMAND
The final command is Increment/Decrement (Figure 6
and 7). The Increment/Decrement command is
different from the other commands. Once the command is issued the master can clock the selected
wiper up and/or down in one segment steps; thereby
providing a fine tuning capability to the host. For each
SCK clock pulse (tHIGH) while SI is HIGH, the selected
wiper will move one resistor segment towards the RH
terminal. Similarly, for each SCK clock pulse while SI
is LOW, the selected wiper will move one resistor
segment towards the RL terminal.
Four instructions require a two-byte sequence to
complete, as illustrated in Figure 4. These instructions
transfer data between the host/processor and the
CAT5411; either between the host and one of the data
registers or directly between the host and the Wiper
Control Register. These instructions are:
— XFR Data Register to Wiper Control Register
This transfers the contents of one specified Data
Register to the associated Wiper Control Register.
— XFR Wiper Control Register to Data Register
This transfers the contents of the specified Wiper
Control Register to the specified associated Data
Register.
See Instructions format for more detail.
Figure 4. Two-Byte Instruction Sequence
SI
0
1
0
1
0
0
ID3 ID2 ID1 ID0 A3
A2 A1 A0 I3
Internal
Address
Device ID
I2
I1
R1 R0 P1 P0
I0
Instruction
Opcode
Register
Address
Pot/WCR
Address
Figure 5. Three-Byte Instruction Sequence
SI
0
1
0
1
0
0
A2
ID3 ID2 ID1 ID0 A3
A1
A0 I3
Internal
Address
Device ID
I2
I1 I0
R1 R0 P1 P0
Instruction
Opcode
D7 D6 D5 D4 D3 D2 D1 D0
Data
Pot/WCR
Register Address
Address
WCR[7:0]
or
Data Register D[7:0]
Figure 6. Increment/Decrement Instruction Sequence
SI
1
0
ID3 ID2 ID1 ID0
0
1
0
A3
Device ID
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
0
A2 A1 A0
Internal
Address
I3
I2
I1
I0
Instruction
Opcode
10
R1 R0 P1 P0
I
N
Pot/WCR C
Data
Register Address 1
Address
I
N
C
2
I
N
C
n
D
E
C
1
D
E
C
n
Doc. No. 2114 Rev. H
CAT5411
Figure 7. Increment/Decrement Timing Limits
INC/DEC
Command
Issued
tWRL
SCK
SI
RW
Voltage Out
INSTRUCTION FORMAT
Read Wiper Control Register (WCR)
DEVICE ADDRESS
INSTRUCTION
DATA
0 1 0 1 0 0 A1 A0 1 0 0 1 0
0 0 P0 7 6 5 4 3 2 1
¯¯¯
CS
0 0
Write Wiper Control Register (WCR)
DEVICE ADDRESS
INSTRUCTION
DATA
0 1 0 1 0 0 A1 A0 1 0 0 1 0
0 0 P0 7 6 5 4 3 2 1
¯¯¯
CS
0 0
Read Data Register (DR)
DEVICE ADDRESS
INSTRUCTION
DATA
0 1 0 1 0 0 A1 A0 1 0 1 1 R1 R0 0 P0 7 6 5 4 3 2 1
¯¯¯
CS
Write Data Register (DR)
DEVICE ADDRESS
INSTRUCTION
DATA
0 1 0 1 0 0 A1 A0 1 1 0 0 R1 R0 0 P0 7 6 5 4 3 2 1
¯¯¯
CS
Read Status (WIP)
DEVICE ADDRESS
INSTRUCTION
0 1 0 1 0 0 A1 A0 0 1 0 1 0
0 0
¯¯¯
CS
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
11
1
0
0
0
0
DATA
7 6 5 4 3 2 1 W
0 0
I
P
¯¯¯
CS
¯¯¯
CS
¯¯¯
CS
¯¯¯
CS
High Voltage
Write Cycle
¯¯¯
CS
Doc. No. 2114 Rev. H
CAT5411
INSTRUCTION FORMAT (CONTINUED)
Global Transfer Data Register (DR) to Wiper Control Register (WCR)
¯¯¯
CS
0
DEVICE ADDRESS
1 0 1 0 0 A1
A0
0
0
INSTRUCTION
0 1 R1 R0 0
0
¯¯¯
CS
Global Transfer Wiper Control Register (WCR) to Data Register (DR)
¯¯¯
CS
0
1
DEVICE ADDRESS
0 1 0 0 A1
A0
1
0
INSTRUCTION
0 0 R1 R0 0
0
¯¯¯
CS
High Voltage
Write Cycle
¯¯¯
CS
High Voltage
Write Cycle
Transfer Wiper Control Register (WCR) to Data Register (DR)
¯¯¯
CS
0
DEVICE ADDRESS
1 0 1 0 0 A1
A0
1
1
INSTRUCTION
1 0 R1 R0 0
P0
Transfer Data Register (DR) to Wiper Control Register (WCR)
¯¯¯
CS
0
1
DEVICE ADDRESS
0 1 0 0 A1
A0
1
1
INSTRUCTION
0 1 R1 R0 0
P0
¯¯¯
CS
Increment (I)/Decrement (D) Wiper Control Register (WCR)
¯¯¯
CS
0
DEVICE ADDRESS
1 0 1 0 0 A1
A0
0
0
INSTRUCTION
1 0 0
0 0
DATA
P0
I/D
I/D
I/D I/D
•••
¯¯¯
CS
Note:
(1) Any write or transfer to the Non-volatile Data Registers is followed by a high voltage cycle after ¯¯¯
CS goes high.
Doc. No. 2114 Rev. H
12
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT5411
PACKAGE OUTLINES
24-LEAD 300 MIL WIDE SOIC (W)
SYMBOL
MIN
NOM
MAX
A
2.35
2.65
A1
0.10
0.30
b
0.31
0.51
C
0.20
0.33
D
15.20
15.40
E
10.11
10.51
E1
7.34
e
7.60
1.27 BSC
h
0.25
0.75
L
0.40
1.27
θ
0°
8°
θ1
5°
15°
TOP VIEW
SIDE VIEW
END VIEW
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
Notes:
(1) All dimensions in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-013.
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
13
Doc. No. 2114 Rev. H
CAT5411
24-LEAD TSSOP (Y)
SYMBOL
MIN
NOM
A
MAX
1.10
A1
0.05
0.15
A2
0.85
0.95
b
0.19
0.30
D
7.70
7.90
E
6.25
6.55
E1
4.30
4.50
e
0.65 BSC
L
1.00 REF
L1
0.50
0.70
θ1
0°
8°
VIEW A-A
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC specification MO-153.
Doc. No. 2114 Rev. H
14
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT5411
EXAMPLE OF ORDERING INFORMATION
Prefix
Device #
CAT
Suffix
5411
W
I
-10
Temperature Range
I = Industrial (-40ºC to 85ºC)
Company ID
Product Number
5411
Resistance
-25: 2.5kΩ
-10: 10kΩ
-50: 50kΩ
-00: 100kΩ
Package
W: SOIC
Y: TSSOP
Ordering Part Number
Resistor [kΩ]
CAT5411WI-25
2.5
CAT5411WI-10
10
CAT5411WI-50
50
CAT5411WI-00
100
CAT5411YI-25
2.5
CAT5411YI-10
10
CAT5411YI-50
50
CAT5411YI-00
100
–
T1
Tape & Reel
T: Tape & Reel
1: 1000/Reel
2: 2000/Reel
Notes:
(1) All packages are RoHS-compliant (Lead-free, Halogen-free).
(2) The standard lead finish is NiPdAu.
(3) The device used in the above example is a CAT5411WI-10-T1 (SOIC, Industrial Temperature range, 10kΩ, NiPdAu, Tape & Reel, 1000).
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
15
Doc. No. 2114 Rev. H
REVISION HISTORY
Date
Rev.
Reason
04/01/04
G
Eliminate data sheet designation
Update Features
Update Description
Update Pin Description
Update Absolute Maximum Ratings
Update Recommended Operating Conditions
Update Potentiometer Characteristics Update Reliability Characteristics
Update Ordering Information
03/26/07
H
Updated Outline Packages
Updated Example of Ordering Information
Copyrights, Trademarks and Patents
Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:
Beyond Memory™, DPP™, EZDim™, LDD™, MiniPot™, and Quad-Mode™
Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products.
CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS
PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE
RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING
OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.
Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a situation where personal
injury or death may occur.
Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets labeled
"Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.
Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical
semiconductor applications and may not be complete.
Catalyst Semiconductor, Inc.
Corporate Headquarters
2975 Stender Way
Santa Clara, CA 95054
Phone: 408.542.1000
Fax:
408.542.1200
www.catsemi.com
Document No: 2114
Revision:
H
Issue date:
03/26/07