CATALYST CAT64LC20UATE13

H
CAT64LC10/20/40
1K/2K/4K-Bit SPI Serial EEPROM
LE
EE
GEN FR
ALO
A D F R E ETM
FEATURES
■ SPI bus compatible
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■ Commercial, industrial and automotive
temperature ranges
■ Low power CMOS technology
■ 2.5V to 6.0V operation
■ Power-up inadvertant write protection
■ Self-timed write cycle with auto-clear
BSY pin for end-of-write indication
■ RDY/BSY
■ Hardware reset pin
■ 1,000,000 program/erase cycles
■ Hardware and software write protection
■ 100 year data retention
DESCRIPTION
The CAT64LC10/20/40 is a 1K/2K/4K-bit Serial EEPROM
which is configured as 64/128/256 registers by 16 bits.
Each register can be written (or read) serially by using
the DI (or DO) pin. The CAT64LC10/20/40 is
manufactured using Catalyst’s advanced CMOS
PIN CONFIGURATION
CS
SK
DI
DO
1
2
3
4
8
7
6
5
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EEPROM floating gate technology. It is designed to
endure 1,000,000 program/erase cycles and has a data
retention of 100 years. The device is available in 8-pin
DIP, SOIC and TSSOP packages.
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SOIC Package (J, W)
DIP Package (P, L)
VCC
RDY/BUSY
RESET
GND
RDY/BUSY
VCC
CS
SK
1
2
3
4
8
7
6
5
TSSOP Package (U, Y)
CS
SK
DI
DO
RESET
GND
DO
DI
SOIC Package (S, V)
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PIN FUNCTIONS
Pin Name
CS
CS
SK
DI
DO
1
2
3
4
8
7
6
5
a
P
8
7
6
5
1
2
3
4
VCC
RDY/BUSY
RESET
GND
TSSOP Package (UR, YR)
VCC
RDY/BUSY
RESET
GND
8
7
6
5
1
2
3
4
RDY/BUSY
VCC
CS
SK
RESET
GND
DO
DI
BLOCK DIAGRAM
Function
VCC
GND
Chip Select
SK
Clock Input
DI
Serial Data Input
DO
Serial Data Output
VCC
+2.5V to +6.0V Power Supply
GND
Ground
RESET
Reset
RDY/BUSY
Ready/BUSY Status
MEMORY ARRAY
64/128/256 x 16
ADDRESS
DECODER
DATA
REGISTER
OUTPUT
BUFFER
DI
RESET
CS
SK
MODE DECODE
LOGIC
CLOCK
GENERATOR
DO
RDY/BUSY
64LC10/20/40 F02
© 2004 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 1021, Rev. C
CAT64LC10/20/40
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Temperature Under Bias ................. –55°C to +125°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of
the device at these or any other conditions outside of those
listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for
extended periods may affect device performance and
reliability.
Storage Temperature ....................... –65°C to +150°C
Voltage on any Pin with
Respect to Ground(1) ............ –2.0V to +VCC +2.0V
VCC with Respect to Ground ............... –2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25°C) ................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(2) ........................ 100 mA
RELIABILITY CHARACTERISTICS
Symbol
NEND
(3)
Parameter
Min.
Endurance
Max.
Units
Reference Test Method
1,000,000
Cycles/Byte
MIL-STD-883, Test Method 1033
TDR(3)
Data Retention
100
Years
VZAP(3)
ESD Susceptibility
2000
Volts
ILTH(3)(4)
Latch-Up
100
mA
CAPACITANCE (TA = 25°C, f= 1.0 MHz, VCC =6.0V)
Symbol
Test
CI/O(3)
CIN
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Input/Output Capacitance (DO, RDY/BSY)
(3)
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Input Capacitance (CS, SK, DI, RESET)
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
Max.
Units
Conditions
8
pF
VI/O = 0V
6
pF
VIN = 0V
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V.
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Doc. No. 1021, Rev. C
2
CAT64LC10/20/40
D.C. OPERATING CHARACTERISTICS
VCC = +2.5V to +6.0V, unless otherwise specified.
Limits
Sym.
ICC
ICCP
Parameter
Max.
Units
0.4
mA
fSK = 250 kHz
EWEN, EWDS, READ 6.0V
1
mA
fSK = 1 MHz
Program Current
2.5V
2
mA
6.0V
3
mA
Operating Current
Min.
Typ.
2.5V
Test Conditions
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ISB(1)
Standby Current
3
µA
VIN = GND or VCC
CS = VCC
ILI
Input Leakage Current
2
µA
VIN = GND to VCC
ILO
Output Leakage Current
10
µA
VOUT = GND to VCC
VIL
Low Level Input Voltage, DI
–0.1
VCC x 0.3
V
VIH
High Level Input Voltage, DI
VCC x 0.7
VCC + 0.5
V
VIL
Low Level Input Voltage,
CS, SK, RESET
–0.1
VCC x 0.2
V
VIH
High Level Input Voltage,
CS, SK, RESET
VCC x 0.8
VCC + 0.5
V
VOH(1) High Level Output Voltage
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2.5V
VCC – 0.3
6.0V
VCC – 0.3
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V
IOH = –10µA
V
IOH = –10µA
V
IOH = –400µA
0.4
V
IOL = 10µA
0.4
V
IOL = 2.1mA
2.4
VOL(1)
Low Level Output Voltage
2.5V
6.0V
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Note:
(1) VOH and VOL spec applies to READY/BUSY pin also
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Doc. No. 1021, Rev. C
CAT64LC10/20/40
A.C. OPERATING CHARACTERISTICS
VCC = +2.5V to +6.0V, unless otherwise specified.
Limits
Symbol
Parameter
Min.
tCSS
CS Setup Time
100
tCSH
CS Hold Time
100
tDIS
DI Setup Time
200
tDIH
DI Hold Time
200
tPD1
Output Delay to 1
tPD0
Output Delay to 0
tHZ(2)
Output Delay to High Impendance
tCSMIN
Minimum CS High Time
tSKHI
Minimum SK High Time
2.5V
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2.5V
4.5V–6.0V
tSV
Output Delay to Status Valid
fSK
Maximum Clock Frequency
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tRESS
Reset to CS Setup Time
tRESMIN
Minimum RESET High Time
tRESH
RESET to READY Hold Time
tRC
Write Recovery
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Symbol
tPUR
tPUW
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2.5V
4.5V–6.0V
1000
Parameter
400
1000
400
s
t
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ns
ns
ns
a
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500
250
Units
ns
300
Minimum SK Low Time
POWER-UP TIMING(1)(3)
Max.
300
4.5V–6.0V
tSKLOW
Typ.
ns
ns
ns
ns
ns
ns
500
ns
250
kHz
1000
0
ns
250
ns
0
ns
100
ns
Min.
Max.
Units
Power-Up to Read Operation
10
µs
Power-Up to Program Operation
1
ms
Max.
Units
2.5V
10
ms
4.5V–6.0V
5
WRITE CYCLE LIMIITS
Symbol
tWR
Parameter
Min.
Program Cycle Time
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) This parameter is sampled but not 100% tested.
(3) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
Doc. No. 1021, Rev. C
4
CAT64LC10/20/40
INSTRUCTION SET
Instruction
Read
Opcode
Address
Data
64LC10
10101000
A5 A4 A3 A2 A1 A0 0
0
D15 - D0
64LC20
10101000
A6 A5 A4 A3 A2 A1 A0
0
D15 - D0
64LC40
10101000
A7 A6 A5 A4 A3 A2 A1 A0
D15 - D0
64LC10
10100100
A5 A4 A3 A2 A1 A0 0
0
D15 - D0
64LC20
10100100
A6 A5 A4 A3 A2 A1 A0
0
D15 - D0
64LC40
10100100
A7 A6 A5 A4 A3 A2 A1 A0
D15 - D0
Write Enable
10100011
XXXXXXXX
Write Disable
10100000
XXXXXXXX
[Write All Locations](1)
10100001
XXXXXXXX
Write
Figure 1. A.C. Testing Input/Output Waveform (2)(3(4) (CL = 100 pF)
VCC x 0.8
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VCC x 0.7
INPUT PULSE LEVELS
D15–D0
REFERENCE POINTS
VCC x 0.3
VCC x 0.2
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Note:
(1) (Write All Locations) is a test mode operation and is therefore not included in the A.C./D.C. Operations specifications.
(2) Input Rise and Fall Times (10% to 90%) < 10 ns.
(3) Input Pulse Levels = VCC x 0.2 and VCC x 0.8.
(4) Input and Output Timing Reference = VCC x 0.3 and VCC x 0.7.
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Doc. No. 1021, Rev. C
CAT64LC10/20/40
DEVICE OPERATION
and data to be written are clocked into the DI pin on the
rising edge of the SK clock. The DO pin is normally in a
high impedance state except when outputting data in a
READ operation or outputting RDY/BSY status when
polled during a WRITE operation.
The CAT64LC10/20/40 is a 1K/2K/4K-bit nonvolatile
memory intended for use with all standard controllers.
The CAT64LC10/20/40 is organized in a 64/128/256 x
16 format. All instructions are based on an 8-bit format.
There are four 16-bit instructions: READ, WRITE, EWEN,
and EWDS. The CAT64LC10/20/40 operates on a single
power supply ranging from 2.5V to 6.0V and it has an onchip voltage generator to provide the high voltage needed
during a programming operation. Instructions, addresses
The format for all instructions sent to this device includes
a 4-bit start sequence, 1010, a 4-bit op code and an 8bit address field or dummy bits. For a WRITE operation,
Figure 2. Sychronous Data Timing
RESET
tSKLOW
tRESS
tSKHI
SK
tDIS
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tDIH
DI
tCSH
tCSS
CS
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tPD0,tPD1
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DO
tRESH
tRC
RDY/BUSY
tCSMIN
tHZ
a
P
tSV
tSV
Figure 3. Read Instruction Timing
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RESET
i
D
SK
CS
DI
1
0
1
0
1
0
0
0
ADDRESS*
DO
D15 D14
HIGH
RDY/BUSY
* Please check the instruction set table for address
Doc. No. 1021, Rev. C
6
D1 D0
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CAT64LC10/20/40
a 16-bit data field is also required following the 8-bit
address field.
Read
Upon receiving a READ command and address (clocked
into the DI pin), the DO pin will output data one tPD after
the falling edge of the 16th clock (the last bit of the
address field). The READ operation is not affected by
the RESET input.
The CAT64LC10/20/40 requires an active LOW CS in
order to be selected. Each instruction must be preceded
by a HIGH-to-LOW transition of CS before the input of
the 4-bit start sequence. Prior to the 4-bit start sequence
(1010), the device will ignore inputs of all other logical
sequence.
Write
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After receiving a WRITE op code, address and data, the
device goes into the AUTO-Clear cycle and then the
Figure 4. Write Instruction Timing
RESET
SK
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CS
1
DI
0
1
0
0
1
0
0
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DO
RDY/BUSY
* Please check instruction set table for address
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ADDRESS*
D15
a
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D0
Figure 5. Ready/BUSY
BUSY Status Instruction Timing
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RESET
i
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SK
CS
LOW
WRITE INSTRUCTION
NEXT INSTRUCTION
DI
DO
HIGH
RDY/BUSY
7
Doc. No. 1021, Rev. C
CAT64LC10/20/40
WRITE cycle. The RDY/BSY pin will output the BUSY
status (LOW) one tSV after the rising edge of the 32nd
clock (the last data bit) and will stay LOW until the write
cycle is complete. Then it will output a logical “1” until the
next WRITE cycle. The RDY/BSY output is not affected
by the input of CS.
the device is deselected. The rising edge of the first “1”
input on the DI pin will reset DO back to the high
impedance state again.
The WRITE operation can be halted anywhere in the
operation by the RESET input. If a RESET pulse occurs
during a WRITE operation, the device will abort the
operation and output a READY status.
An alternative to get RDY/BSY status is from the DO pin.
During a write cycle, asserting a LOW input to the CS pin
will cause the DO pin to output the RDY/BSY status.
Bringing CS HIGH will bring the DO pin back to a high
impedance state again. After the device has completed
a WRITE cycle, the DO pin will output a logical “1” when
Figure 6. RESET During BUSY Instruction Timing
RESET
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SK
CS
DI
1
0
1
0
0
1
0
0
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DO
RDY/BUSY
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NOTE: Data may be corrupted if a RESET occurs while
the device is BUSY. If the reset occurs before the BUSY
period, no writing will be initiated. However, if RESET
occurs after the BUSY period, new data will have been
written over the old data.
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ADDRESS*
D15
a
P
D0
tWR
* Please check instruction set table for address
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Figure 7. EWEN Instruction Timing
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RESET
SK
CS
DI
DO
RDY/BUSY
1
0
1
0
0
0
1
1
HIGH-Z
HIGH
5064 FHD F09
Doc. No. 1021, Rev. C
8
CAT64LC10/20/40
RESET
ERASE/WRITE ENABLE and DISABLE
The RESET pin, when set to HIGH, will reset or abort a
WRITE operation. When RESET is set to HIGH while the
WRITE instruction is being entered, the device will not
execute the WRITE instruction and will keep DO in HighZ condition.
The CAT64LC10/20/40 powers up in the erase/write
disabled state. After power-up or while the device is in an
erase/write disabled state, any write operation must be
preceded by an execution of the EWEN instruction.
Once enabled, the device will stay enabled until an
EWDS has been executed or a power-down has occured.
The EWDS is used to prevent any inadvertent overwriting of the data. The EWEN and EWDS instructions
have no affect on the READ operation and are not
affected by the RESET input.
When RESET is set to HIGH, while the device is in a
clear/write cycle, the device will abort the operation and
will display READY status on the RDY/BSY pin and on
the DO pin if CS is low.
The RESET input affects only the WRITE and WRITE
ALL operations. It does not reset any other operations
such as READ, EWEN and EWDS.
Figure 8. EWDS Instruction Timing
RESET
d
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SK
CS
DI
1
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0
DO
1
0
0
HIGH-Z
HIGH
RDY/BUSY
0
0
0
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Doc. No. 1021, Rev. C
CAT64LC10/20/40
ORDERING INFORMATION
a
P
P: PDIP
S: SOIC (JEDEC)
J: SOIC (JEDEC)
U: TSSOP
UR: TSSOP (Rotated)
L: PDIP (Lead free, Halogen free)
V: SOIC (JEDEC) (Lead free, Halogen free)
W: SOIC (JEDEC) (Lead free, Halogen free)
Y: TSSOP (Lead free, Halogen free)
YR: TSSOP (Rotated) (Lead free, Halogen free)
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Notes:
(1) The device used in the above example is a 64LC10SI-TE13 (SOIC, Industrial Temperature, Tape & Reel)
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Doc. No. 1021, Rev. C
10
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CAT64LC10/20/40
PACKAGING INFORMATION
8-LEAD TSSOP (U)
3.0 + 0.1
-A5
8
7.72 TYP
4.16 TYP
6.4
4.4 + 0.1
-B(1.78 TYP)
3.2
0.42 TYP
a
P
0.65 TYP
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0.2 C B A
4
1
LAND PATTERN RECOMMENDATION
ALL LEAD TIPS
PIN #1 IDENT.
1.1 MAX TYP
0.1 C
ALL LEAD TIPS
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(0.9)
-C-
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SEE DETAIL A
0.09 - 0.20 TYP
0.10 + 0.05 TYP
0.65 TYP
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0.19 - 0.30 TYP
0.3 M A B S C S
GAGE PLANE
0.25
0 o- 8 o
0.6+0.1
SEATING PLANE
DETAIL A
11
Doc. No. 1021, Rev. C
CAT64LC10/20/40
REVISION HISTORY
Date
Rev.
Reason
9/3/2004
B
Added Green packages in all areas
Updated DC Operating Characteristics table & notes
11/17/2004
C
Changed ISB from 1µA, Max to 3µA, Max in DC Operating
Characteristics table
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Copyrights, Trademarks and Patents
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DPP ™
AE2 ™
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Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents
issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000.
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CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS
PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE
RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING
OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.
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Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or
other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a
situation where personal injury or death may occur.
Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets
labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.
Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate
typical semiconductor applications and may not be complete.
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Catalyst Semiconductor, Inc.
Corporate Headquarters
1250 Borregas Avenue
Sunnyvale, CA 94089
Phone: 408.542.1000
Fax: 408.542.1200
www.catalyst-semiconductor.com
Doc. No. 1021, Rev. C
Publication #:
Revison:
Issue date:
12
1021
C
11/3/04