Fairchild CD4019BCM Quad and-or select gate Datasheet

Revised January 1999
CD4019BC
Quad AND-OR Select Gate
General Description
Features
The CD4019BC is a complementary MOS quad AND-OR
select gate. Low power and high noise margin over a wide
voltage range is possible through implementation of N- and
P-channel enhancement mode transistors. These complementary MOS (CMOS) transistors provide the building
blocks for the 4 “AND-OR select” gate configurations, each
consisting of two 2-input AND gates driving a single 2-input
OR gate. Selection is accomplished by control bits KA and
KB. All inputs are protected against static discharge damage.
■ Wide supply voltage range:
■ High noise immunity:
3.0V to 15V
0.45 VDD (typ.)
■ Low power TTL compatibility: Fan out of 2 driving 74L
or 1 driving 74LS
Applications
• AND-OR select gating
• Shift-right/shift-left registers
• True/complement selection
• AND/OR/EXCLUSIVE-OR selection
Ordering Code:
Order Number
Package Number
Package Description
CD4019BCM
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
CD4019BCSJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
CD4019BCN
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Assignments for DIP, SOIC and SOP
Top View
© 1999 Fairchild Semiconductor Corporation
DS005952.prf
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CD4019BC Quad AND-OR Select Gate
October 1987
CD4019BC
Schematic Diagram
Schematic diagram for 1 of 4 identical stages
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2
Recommended Operation
Conditions (Note 2)
−0.5V to +18V
Supply Voltage (VDD)
Input Voltage (VIN)
−65°C to +150°C
Storage Temperature Range (TS)
700 mW
Small Outline
500 mW
Symbol
IDD
VOL
Parameter
VIH
IOL
IOH
IIN
−40°C
Conditions
Min
+25°C
Max
Min
+85°C
Typ
Max
Min
Max
Units
VDD = 5V
1
0.03
1
7.5
µA
Current
VDD = 10V
2
0.05
2
15
µA
VDD = 15V
4
0.07
4
30
µA
LOW Level
HIGH Level
Output Voltage
VIL
(Note 3)
Quiescent Device
Output Voltage
VOH
Note 2: VSS = 0V unless otherwise specified.
260°C
DC Electrical Characteristics
−40°C to +85°C
Note 1: “Absolute Maximum Ratings” are those values beyond which the
safety of the device cannot be guaranteed; they are not meant to imply that
the devices should be operated at these limits. The tables of “Recommended Operating Conditions” and “Electrical Characteristics” provide conditions for actual device operation.
Lead Temperature (TL)
(Soldering, 10 seconds)
0V to VDD V
Operating Temperature Range (TA)
Power Dissipation (PD)
Dual-In-Line
+3V to +15V
DC Supply Voltage (VDD)
−0.5V to VDD +0.5V
Input Voltage (VIN)
|IO| < 1 µA
VDD = 5V
0.05
0
0.05
0.05
V
VDD = 10V
0.05
0
0.05
0.05
V
VDD = 15V
0.05
0
0.05
0.05
V
|IO| < 1 µA
VDD = 5V
4.95
4.95
5
4.95
VDD = 10V
9.95
9.95
10
9.95
V
VDD = 15V
14.95
14.95
15
14.95
V
V
LOW Level
VDD = 5V, VO = 0.5V or 4.5V
1.5
2
1.5
1.5
Input Voltage
VDD = 10V, VO = 1.0V or 9.0V
3.0
4
3.0
3.0
V
VDD = 15V, VO = 1.5V or 13.5V
4.0
6
4.0
4.0
V
V
HIGH Level
VDD = 5V, VO = 0.5V or 4.5V
3.5
3.5
3
3.5
Input Voltage
VDD = 10V, VO = 1.0V or 9.0V
7.0
7.0
6
7.0
V
VDD = 15V, VO = 1.5V or 13.5V
11.0
11.0
9
11.0
V
LOW Level Output
VDD = 5V, VO = 0.4V
0.52
0.44
1
0.36
mA
Current (Note 4)
VDD = 10V, VO = 0.5V
1.3
1.1
2.5
0.9
mA
mA
V
VDD = 15V, VO = 1.5V
3.6
3.0
10
2.4
HIGH Level Output
VDD = 5V, VO = 4.6V
−0.2
−0.16
−0.4
−0.12
mA
Current (Note 4)
VDD = 10V, VO = 9.5V
−0.5
−0.4
−1.0
−0.3
mA
VDD = 15V, VO = 13.5V
−1.4
Input Current
VDD = 15V, VIN = 0V
−0.30
−10−5
−0.30
−1.0
µA
VDD = 15V, VIN = 15V
0.30
10−5
0.30
1.0
µA
−1.2
−3.0
−1.0
mA
Note 3: VSS = 0V unless otherwise specified.
Note 4: IOH and IOL are tested one output at a time.
3
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CD4019BC
Absolute Maximum Ratings(Note 1)
(Note 2)
CD4019BC
AC Electrical Characteristics
(Note 5)
TA = 25°C, CL = 50 pF, RL = 200k, unless otherwise specified
Typ
Max
Units
tPHL,
Symbol
Propagation Delay,
VDD = 5V
100
300
ns
tPLH
Input to Output
VDD = 10V
50
120
ns
VDD = 15V
45
100
ns
HIGH-to-LOW Level
VDD = 5V
100
200
ns
Transition Time
VDD = 10V
50
100
ns
VDD = 15V
40
80
ns
LOW-to-HIGH Level
VDD = 5V
150
300
ns
Transition Time
VDD = 10V
70
140
ns
VDD = 15V
50
100
ns
All A and B Inputs
5
7.5
pF
KA and KB Inputs
10
15
pF
tTHL
tTLH
CIN
Parameter
Input Capacitance
Conditions
Note 5: AC Parameters are guaranteed by DC correlated testing.
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4
Min
CD4019BC
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
Package Number M16A
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M16D
5
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CD4019BC Quad AND-OR Select Gate
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N16E
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