Intersil CD4095BMS Cmos gated j-k master-slave flip-flop Datasheet

CD4095BMS
CD4096BMS
CMOS Gated J-K
Master-Slave Flip-Flops
December 1992
Features
Pinouts
CD4095BMS
TOP VIEW
• Set-Reset Capability
NC 1
14 VDD
RESET 2
13 SET
• High Voltage Types (20V Rating)
• CD4095BMS Non-Inverting J and K Inputs
• CD4096BMS Inverting and Non-Inverting J and K
Inputs
• 16MHz Toggle Rate (Typ.) at VDD - VSS = 10V
• Gated Inputs
J1 3
12 CLOCK
J2 4
11 K1
J3 5
10 K2
Q 6
9 K3
8 Q
VSS 7
• 100% Tested for Quiescent Current at 20V
• 5V, 10V and 15V Parametric Ratings
CD4096BMS
TOP VIEW
• Standardized Symmetrical Output Characteristics
• Maximum Input Current of 1µA at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC
• Noise Margin (Over Full Package/Temperature Range)
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
NC 1
14 VDD
RESET 2
13 SET
• Meets all requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
J1 3
12 CLOCK
J2 4
11 K1
J3 5
10 K2
Q 6
9 K3
8 Q
VSS 7
NC = NO CONNECTION
Applications
Functional Diagrams
• Registers
• Counters
CD4095BMS
SET
• Control Circuits
Description
CD4095BMS and CD4096BMS are J-K Master-Slave FlipFlops featuring separate AND gating of multiple J and K
inputs. The gated J-K inputs control transfer of information
into the master section during clocked operation. Information
on the J-K inputs is transferred to the Q and Q outputs on
the positive edge of the clock pulse. SET and RESET inputs
(active high) are provided for asynchronous operation.
The CD4095BMS and CD4096BMS are supplied in these 14
lead outline packages:
Braze Seal DIP
H4Q
Frit Seal DIP
H1A
3
J1
4
J2
5
J3
12
CLOCK
11
K1
10
K2
9
K3
J
S
Q
R
Q
8
Q
CL
K
2
RESET
6
Q
VDD = 14
VSS = 7
NC = 1
CD4096BMS
SET
3
J1
4
J2
5
J3
12
CLOCK
11
K1
10
K2
9
K3
RESET
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-1094
13
13
J
S
Q
R
Q
8
Q
CL
K
2
6
Q
VDD = 14
VSS = 7
NC = 1
File Number
3331
Specifications CD4095BMS, CD4096BMS
Absolute Maximum Ratings
Reliability Information
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V
(Voltage Referenced to VSS Terminals)
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA
Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC
Package Types D, F, K, H
Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC
At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for
10s Maximum
Thermal Resistance . . . . . . . . . . . . . . . .
θja
θjc
Ceramic DIP and FRIT Package . . . . . 80oC/W
20oC/W
Flatpack Package . . . . . . . . . . . . . . . . 70oC/W
20oC/W
o
Maximum Package Power Dissipation (PD) at +125 C
For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW
For TA = +100oC to +125oC (Package Type D, F, K) . . . . . Derate
Linearity at 12mW/oC to 200mW
Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW
For TA = Full Package Temperature Range (All Package Types)
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
Supply Current
SYMBOL
IDD
CONDITIONS (NOTE 1)
VDD = 20V, VIN = VDD or GND
VDD = 18V, VIN = VDD or GND
Input Leakage Current
IIL
VIN = VDD or GND
VDD = 20
VDD = 18V
Input Leakage Current
IIH
VIN = VDD or GND
VDD = 20
GROUP A
SUBGROUPS
LIMITS
TEMPERATURE
MIN
+25
-
2
µA
+125oC
-
200
µA
3
-55oC
-
2
µA
1
+25o
C
-100
-
nA
2
+125oC
-1000
-
nA
3
-55oC
-100
-
nA
1
+25oC
-
100
nA
2
+125oC
-
1000
nA
-
100
nA
-
50
mV
-
V
3
Output Voltage
VOL15
VDD = 15V, No Load
1, 2, 3
+25oC, +125oC, -55oC
Output Voltage
VOH15
VDD = 15V, No Load (Note 3)
1, 2, 3
+25oC, +125oC, -55oC 14.95
Output Current (Sink)
IOL5
VDD = 5V, VOUT = 0.4V
UNITS
1
-55oC
VDD = 18V
MAX
2
oC
1
+25oC
0.53
-
mA
Output Current (Sink)
IOL10
VDD = 10V, VOUT = 0.5V
1
+25oC
1.4
-
mA
Output Current (Sink)
IOL15
VDD = 15V, VOUT = 1.5V
1
+25oC
3.5
-
mA
1
+25oC
-
-0.53
mA
1
+25oC
-
-1.8
mA
Output Current (Source)
Output Current (Source)
IOH5A
IOH5B
VDD = 5V, VOUT = 4.6V
VDD = 5V, VOUT = 2.5V
Output Current (Source)
IOH10
VDD = 10V, VOUT = 9.5V
1
+25oC
-
-1.4
mA
Output Current (Source)
IOH15
VDD = 15V, VOUT = 13.5V
1
+25oC
-
-3.5
mA
1
+25oC
-2.8
-0.7
V
1
+25oC
0.7
2.8
V
N Threshold Voltage
P Threshold Voltage
Functional
VNTH
VPTH
F
VDD = 10V, ISS = -10µA
VSS = 0V, IDD = 10µA
VDD = 2.8V, VIN = VDD or GND
7
+25oC
VDD = 20V, VIN = VDD or GND
7
+25oC
VDD = 18V, VIN = VDD or GND
8A
+125oC
VDD = 3V, VIN = VDD or GND
8B
-55oC
VOH > VOL <
VDD/2 VDD/2
V
Input Voltage Low
(Note 2)
VIL
VDD = 5V, VOH > 4.5V, VOL < 0.5V
1, 2, 3
+25oC, +125oC, -55oC
-
1.5
V
Input Voltage High
(Note 2)
VIH
VDD = 5V, VOH > 4.5V, VOL < 0.5V
1, 2, 3
+25oC, +125oC, -55oC
3.5
-
V
Input Voltage Low
(Note 2)
VIL
VDD = 15V, VOH > 13.5V,
VOL < 1.5V
1, 2, 3
+25oC, +125oC, -55oC
-
4
V
Input Voltage High
(Note 2)
VIH
VDD = 15V, VOH > 13.5V,
VOL < 1.5V
1, 2, 3
+25oC, +125oC, -55oC
11
-
V
NOTES: 1. All voltages referenced to device GND, 100% testing being
implemented.
2. Go/No Go test with limits applied to inputs.
7-1095
3. For accuracy, voltage is measured differentially to VDD. Limit
is 0.050V max.
Specifications CD4095BMS, CD4096BMS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
Propagation Delay
Clock to Output
Propagation Delay
Set or Reset to Output
Transition Time
Maximum Clock Input
Frequency
SYMBOL
TPHL1
TPLH1
TPHL2
TPLH2
TTHL
TTLH
CONDITIONS (NOTE 1, 2)
GROUP A
SUBGROUPS TEMPERATURE
VDD = 5V, VIN = VDD or GND
9
10, 11
VDD = 5V, VIN = VDD or GND
VDD = 5V, VIN = VDD or GND
9
VDD = 5V, VIN = VDD or GND
+125oC,
-55oC
+25oC
o
o
MIN
MAX
UNITS
-
500
ns
-
675
ns
-
300
ns
10, 11
+125 C, -55 C
-
405
ns
9
+25oC
-
200
ns
-
270
ns
3.5
-
MHz
2.59
-
MHz
10, 11
FCL
+25oC
LIMITS
9
10, 11
+125oC,
-55oC
o
+25 C
+125oC,
-55oC
NOTES:
1. VDD = 5V, CL = 50pF, RL = 200K
2. -55oC and +125oC limits guaranteed, 100% testing being implemented.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Supply Current
SYMBOL
CONDITIONS
NOTES
TEMPERATURE
MIN
MAX
UNITS
IDD
VDD = 5V, VIN = VDD or GND
1, 2
-55oC, +25oC
-
1
µA
+125oC
-
30
µA
-55oC, +25oC
-
2
µA
+125oC
-
60
µA
-55oC, +25oC
-
2
µA
+125oC
-
120
µA
VDD = 10V, VIN = VDD or GND
VDD = 15V, VIN = VDD or GND
1, 2
1, 2
Output Voltage
VOL
VDD = 5V, No Load
1, 2
+25oC, +125oC,
-55oC
-
50
mV
Output Voltage
VOL
VDD = 10V, No Load
1, 2
+25oC, +125oC,
-55oC
-
50
mV
Output Voltage
VOH
VDD = 5V, No Load
1, 2
+25oC, +125oC,
-55oC
4.95
-
V
Output Voltage
VOH
VDD = 10V, No Load
1, 2
+25oC, +125oC,
-55oC
9.95
-
V
Output Current (Sink)
IOL5
VDD = 5V, VOUT = 0.4V
1, 2
+125oC
0.36
-
mA
-55oC
0.64
-
mA
+125oC
0.9
-
mA
-55oC
1.6
-
mA
+125oC
2.4
-
mA
-55oC
4.2
-
mA
+125oC
-
-0.36
mA
-55oC
-
-0.64
mA
+125oC
-
-1.15
mA
-55oC
-
-2.0
mA
+125oC
-
-0.9
mA
-55oC
-
-1.6
mA
Output Current (Sink)
Output Current (Sink)
Output Current (Source)
Output Current (Source)
Output Current (Source)
IOL10
IOL15
IOH5A
IOH5B
IOH10
VDD = 10V, VOUT = 0.5V
VDD = 15V, VOUT = 1.5V
VDD = 5V, VOUT = 4.6V
1, 2
1, 2
1, 2
VDD = 5V, VOUT = 2.5V
1, 2
VDD = 10V, VOUT = 9.5V
7-1096
1, 2
Specifications CD4095BMS, CD4096BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
LIMITS
PARAMETER
Output Current (Source)
Input Voltage Low
SYMBOL
IOH15
VIL
CONDITIONS
VDD =15V, VOUT = 13.5V
VDD = 10V, VOH > 9V, VOL < 1V
NOTES
TEMPERATURE
MIN
MAX
UNITS
1, 2
+125oC
-
-2.4
mA
-55oC
-
-4.2
mA
+25oC, +125oC,
-
3
V
1, 2
-55oC
Input Voltage High
VIH
Propagation Delay
Clock to Output
TPHL
TPLH
Propagation Delay
Set or Reset to Output
Transition Time
Maximum Clock Input
Frequency
Minimum Set or Reset
Pulse Width
TPHL
TPLH
TTHL
TTLH
FCL
VDD = 10V, VOH > 9V, VOL < 1V
VDD = 10V
VDD = 15V
VDD = 10V
VDD = 15V
VDD = 10V
VDD = 15V
VDD = 10V
VDD = 15V
TW
VDD = 5V
VDD = 10V
VDD = 15V
Minimum Data Setup
Time
TS
VDD = 5V
VDD = 10V
VDD = 15V
Minimum Clock Pulse
Width
TW
VDD = 5V
VDD = 10V
VDD = 15V
Maximum Clock Input
Rise or Fall Time
TRCL
TFCL
VDD = 5V
VDD = 10V
VDD = 15V
Input Capacitance
CIN
Any Input
1, 2
+25oC, +125oC,
-55oC
+7
-
V
1, 2, 3
+25oC
-
200
ns
1, 2, 3
+25oC
-
150
ns
1, 2, 3
+25oC
-
150
ns
o
1, 2, 3
+25 C
-
100
ns
1, 2, 3
+25oC
-
100
ns
1, 2, 3
+25oC
-
80
ns
1, 2, 3
+25oC
8
-
MHz
1, 2, 3
+25oC
12
-
MHz
1, 2, 3
+25oC
-
200
ns
1, 2, 3
+25oC
-
100
ns
1, 2, 3
+25oC
-
50
ns
1, 2, 3
+25oC
-
400
ns
1, 2, 3
+25oC
-
160
ns
1, 2, 3
+25oC
-
100
ns
1, 2, 3
+25oC
-
140
ns
1, 2, 3
+25oC
-
60
ns
1, 2, 3
+25oC
-
40
ns
1, 2, 3
+25oC
-
15
µs
1, 2, 3
+25oC
-
5
µs
1, 2, 3
+25oC
-
5
µs
1, 2
+25oC
-
7.5
pF
NOTES:
1. All voltages referenced to device GND.
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized
on initial design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Supply Current
N Threshold Voltage
SYMBOL
IDD
VNTH
CONDITIONS
VDD = 20V, VIN = VDD or GND
VDD = 10V, ISS = -10µA
7-1097
NOTES
TEMPERATURE
MIN
MAX
UNITS
1, 4
+25oC
-
7.5
µA
1, 4
+25oC
-2.8
-0.2
V
Specifications CD4095BMS, CD4096BMS
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
SYMBOL
CONDITIONS
NOTES
TEMPERATURE
MIN
MAX
UNITS
VDD = 10V, ISS = -10µA
1, 4
+25oC
-
±1
V
N Threshold Voltage
Delta
∆VTN
P Threshold Voltage
VTP
VSS = 0V, IDD = 10µA
1, 4
+25oC
0.2
2.8
V
P Threshold Voltage
Delta
∆VTP
VSS = 0V, IDD = 10µA
1, 4
+25oC
-
±1
V
1
+25oC
VOH >
VDD/2
VOL <
VDD/2
V
1, 2, 3, 4
+25oC
-
1.35 x
+25oC
Limit
ns
Functional
F
VDD = 18V, VIN = VDD or GND
VDD = 3V, VIN = VDD or GND
Propagation Delay Time
TPHL
TPLH
VDD = 5V
3. See Table 2 for +25oC limit.
NOTES: 1. All voltages referenced to device GND.
2. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
4. Read and Record
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25oC
PARAMETER
SYMBOL
DELTA LIMIT
Supply Current - MSI-1
IDD
± 0.2µA
Output Current (Sink)
IOL5
± 20% x Pre-Test Reading
IOH5A
± 20% x Pre-Test Reading
Output Current (Source)
TABLE 6. APPLICABLE SUBGROUPS
MIL-STD-883
METHOD
GROUP A SUBGROUPS
Initial Test (Pre Burn-In)
100% 5004
1, 7, 9
IDD, IOL5, IOH5A
Interim Test 1 (Post Burn-In)
100% 5004
1, 7, 9
IDD, IOL5, IOH5A
Interim Test 2 (Post Burn-In)
100% 5004
1, 7, 9
IDD, IOL5, IOH5A
100% 5004
1, 7, 9, Deltas
100% 5004
1, 7, 9
100% 5004
1, 7, 9, Deltas
100% 5004
2, 3, 8A, 8B, 10, 11
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11
Subgroup B-5
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas
Subgroup B-6
Sample 5005
1, 7, 9
Sample 5005
1, 2, 3, 8A, 8B, 9
CONFORMANCE GROUP
PDA (Note 1)
Interim Test 3 (Post Burn-In)
PDA (Note 1)
Final Test
Group A
Group B
Group D
READ AND RECORD
IDD, IOL5, IOH5A
Subgroups 1, 2, 3, 9, 10, 11
Subgroups 1, 2 3
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.
TABLE 7. TOTAL DOSE IRRADIATION
CONFORMANCE GROUPS
Group E Subgroup 2
TEST
READ AND RECORD
MIL-STD-883
METHOD
PRE-IRRAD
POST-IRRAD
PRE-IRRAD
POST-IRRAD
5005
1, 7, 9
Table 4
1, 9
Table 4
7-1098
Specifications CD4095BMS, CD4096BMS
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS
OSCILLATOR
FUNCTION
OPEN
GROUND
VDD
Static Burn-In 1
Note 1
1, 6, 8
2-5, 7, 9-13
14
Static Burn-In 2
Note 1
1, 6, 8
7
2-5, 9-14
Dynamic BurnIn Note 1
1
2, 7, 13
3-5, 9-11, 14
1, 6, 8
7
2-5, 9-14
Static Burn-In 1
Note 1
1, 6, 8
2-5, 7, 9-13
14
Static Burn-In 2
Note 1
1, 6, 8
7
2-5, 9-14
Dynamic BurnIn Note 1
1
2, 5, 7, 9, 13
3, 4, 10, 11, 14
1, 6, 8
7
2-5, 9-14
9V ± -0.5V
50kHz
25kHz
6, 8
-
12
6, 8
12
CD4095BMS
Irradiation
Note 2
CD4096BMS
Irradiation
Note 2
NOTES:
1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V
2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD
= 10V ± 0.5V
7-1099
CD4095BMS, CD4096BMS
Logic Diagram
FOR
CD4095BMS
J3 5
FOR
CD4096BMS
J3 5
FOR
CD4095BMS
J3 9
*
SET 13
*
J1 3
*
J2 4
*
CL
CL
*
*
K1 11
*
K2 10
*
6 Q
TG
TG
2
2
CL
CL
1
1
2
CL
FOR
CD4096BMS
J3 9
1
1
2
TG
CL
TG
CL
CL
*
8 Q
RESET 2
*
TRANSMISSION GATE
CL
CLOCK 12
*
1
IN
CL
INPUT TO OUTPUT IS:
OUT
TG
2
a) A BIDIRECTIONAL LOW
IMPEDANCE WHEN CONTROL INPUT 1
IS “LOW” AND CONTROL INPUT 2 IS “HIGH”
VDD
b) AN OPEN CIRCUIT WHEN CONTROL INPUT 1
IS “HIGH” AND CONTROL INPUT 2 IS “LOW”
*ALL INPUTS ARE PROTECTED
BY CMOS PROTECTION
NETWORK
VSS
FIGURE 1. CD4095BMS AND CD4096BMS LOGIC DIAGRAM
TRUTH TABLES
SYNCHRONOUS OPERATION
(S = 0, R = 0)
INPUTS BEFORE POSITIVE
CLOCK TRANSITION
ASYNCHRONOUS OPERATION
(J AND K = Don’t Care)
OUTPUTS AFTER POSITIVE
CLOCK TRANSITION
INPUTS BEFORE POSITIVE
CLOCK TRANSITION
OUTPUTS AFTER POSITIVE
CLOCK TRANSITION
J*
K*
Q
Q
S
R
Q
Q
0
0
1
1
0
1
0
1
No Change
0
1
Toggles
No Change
1
0
Toggles
0
0
1
1
0
1
0
1
No Change
0
1
0
No Change
1
0
0
* For CD4095BMS
J = J1 • J2 • J3
K = K1 • K2 • K3
For CD4096BMS
J = J1 • J2 • J3
K = K1 • K2 • K3
0 = VSS, 1 = VDD
7-1100
CD4095BMS, CD4096BMS
trCL
tfCL
VDD
90%
50%
10% 0
CLOCK*
INPUT
J OR K
GATE INPUTS
50%
tSLH
tSHL
tTLH
tWL + tWH =
0
tPLH
trCL
VDD
90%
50%
10% 0
tTHL
Q OR Q
OUTPUT
tfCL
VDD
90%
50%
10%
CLOCK
tWL
tPHL
FIGURE 2. PROPAGATION DELAY, TRANSITION, AND SETUP
TIME WAVEFORMS
I
fCL
0
tWH
FIGURE 3. CLOCK PULSE RISE AND FALL TIME WAVEFORMS
VDD
VSS
VSS
13
3
4
5
S
J
13
3
4
5
D
Q
S
J
Q
VSS
12
CLOCK
9
10
11
CL
12
CLOCK
Q
K
CL
VDD
11
10
9
R
Q
K
R
2
2
VSS
VSS
FIGURE 4. CD4095BMS CONNECTED IN TOGGLE MODE
QA
FIGURE 5. CD4096BMS CONNECTED AS A “D” TYPE FLIP-FLOP
QB
QC
QD
CLOCK
INPUT
VDD
3
4
5
J
12
Q
3
4
5
8
J
12
CL
CD4095BMS
9
10
11
STATE 0
1
2
3
4
5
3
4
5
8
J
12
CL
CD4095BMS
9
10
11
Q
K
Q
6
7
8
9
0
3
4
5
8
CL
9
10
11
J
12
CD4095BMS
Q
K
Q
8
CL
CD4095BMS
9
10
11
Q
K
Q
STATE
QA
QB
QC
QD
0
1
2
3
4
5
6
7
8
9
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
K
Q
6
1
CLOCK
QA
QB
QC
QD
FIGURE 6. SYNCHRONOUS BINARY DIVIDE-BY-TEN COUNTER
7-1101
NOTE:
PINS 2 & 13 RESET &
SET, GO TO VSS ON
ALL UNITS
CD4095BMS, CD4096BMS
30
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
25
20
15
10V
10
5
5V
0
AMBIENT TEMPERATURE (TA) = +25oC
15.0
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
12.5
10.0
10V
7.5
5.0
2.5
5V
0
5
10
15
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
5
10
15
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
FIGURE 7. TYPICAL OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS
FIGURE 8. MINIMUM OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
-15
-10
-5
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
-15
-10
-5
AMBIENT TEMPERATURE (TA) = +25oC
GATE-TO-SOURCE VOLTAGE (VGS) = -5V
0
-5
-10
-15
-10V
-20
-25
-15V
-30
-5
-10V
AMBIENT TEMPERATURE (TA) = +25oC
SUPPLY VOLTAGE (VDD) = 5V
200
150
10V
15V
50
0
25
-15
FIGURE 10. MINIMUM OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS
250
100
-10
-15V
AMBIENT TEMPERATURE (TA) = +25oC
300
200
150
SUPPLY VOLTAGE (VDD) = 5V
100
10V
15V
50
0
0
50
75
100
LOAD CAPACITANCE (CL) (pF)
FIGURE 11. TYPICAL PROPAGATION DELAY TIME vs LOAD
CAPACITANCE
0
GATE-TO-SOURCE VOLTAGE (VGS) = -5V
TRANSITION TIME (tTHL, tTLH) (ns)
PROPAGATION DELAY TIME (tPHL, tPLH) (ns)
FIGURE 9. TYPICAL OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS
0
AMBIENT TEMPERATURE (TA) = +25oC
OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)
0
OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)
AMBIENT TEMPERATURE (TA) = +25oC
OUTPUT LOW (SINK) CURRENT (IOL) (mA)
OUTPUT LOW (SINK) CURRENT (IOL) (mA)
Typical Performance Characteristics
20
40
60
80
100
LOAD CAPACITANCE (CL) (pF)
FIGURE 12. TYPICAL TRANSITION TIME vs LOAD
CAPACITANCE
7-1102
CD4095BMS, CD4096BMS
(Continued)
AMBIENT TEMPERATURE (TA) = +25oC
trl tf = 5ns
CL = 50pF
30
POWER DISSIPATION PER (PD) (µW)
CLOCK FREQUENCY (fCL) (MHz)
Typical Performance Characteristics
25
20
15
10
5
106
AMBIENT TEMPERATURE (TA) = +25oC
MAXIMUM PACKAGE DISSIPATION =200mW
4
2
105 4 SUPPLY VOLTAGE (VDD) = 15V
2
104 4
2
10V
4
103
2
10V
4
102 2
10
5V
4
2
LOAD CAPACITANCE (CL) = 50pF
4
2
CL = 15pF
1
0
5
10
15
2
20
4 6
1
2
10
4 6
102
2
4 6
103
2
4 6
104
2
4 6
INPUT FREQUENCY (fIN) (kHz)
SUPPLY VOLTAGE (VDD) (V)
FIGURE 13. TYPICAL CLOCK FREQUENCY vs SUPPLY
VOLTAGE (TOGGLE MODE - SEE FIGURE 4)
FIGURE 14. TYPICAL POWER DISSIPATION vs INPUT CLOCK
FREQUENCY
Chip Dimensions and Pad Layouts
CD4096BHMS
CD4095BHMS
Dimensions in parenthesis are in millimeters and are
derived from the basic inch dimensions as indicated.
Grid graduations are in mils (10-3 inch).
METALLIZATION:
PASSIVATION:
Thickness: 11kÅ − 14kÅ,
AL.
10.4kÅ - 15.6kÅ, Silane
BOND PADS: 0.004 inches X 0.004 inches MIN
DIE THICKNESS: 0.0198 inches - 0.0218 inches
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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