Revised January 1999 CD4099BC 8-Bit Addressable Latch General Description The CD4099BC is an 8-bit addressable latch with three address inputs (A0–A2), an active low enable input (E), active high clear input (CL), a data input (D), and eight outputs (Q0–Q7). Data is entered into a particular bit in the latch when that bit is addressed by the address inputs and the enable (E) is LOW. Data entry is inhibited when enable (E) is HIGH. When clear (CL) and enable (E) are HIGH, all outputs are LOW. When clear (CL) is HIGH and enable (E) is LOW, the channel demultiplexing occurs. The bit that is addressed has an active output which follows the data input while all unaddressed bits are held LOW. When operating in the addressable latch mode (E = CL = LOW), changing more than one bit of the address could impose a transient wrong address. Therefore, this should only be done while in the memory mode (E = HIGH, CL = LOW). Features ■ Wide supply voltage range: ■ High noise immunity: 3.0V to 15V 0.45 VDD (typ.) ■ Low power TTL: fan out of 2 driving 74L compatibility: or 1 driving 74LS ■ Serial to parallel capability ■ Storage register capability ■ Random (addressable) data entry ■ Active high demultiplexing capability ■ Common active high clear Ordering Code: Order Number CD4099BCN Package Number N16E Package Description 16-Lead Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Connection Diagram Pin Assignments for DIP Top View Truth Table Mode Selection E CL Addressed Unaddressed Latch Latch Mode L L Follows Data H L Holds Previous Data Holds Previous Data Memory Holds Previous Data Addressable Latch L H Follows Data Reset to “0” Demultiplexer H H Reset to “0” Reset to “0” Clear © 1999 Fairchild Semiconductor Corporation DS005984.prf www.fairchildsemi.com CD4099BC 8-Bit Addressable Latch October 1987 CD4099BC Logic Diagram www.fairchildsemi.com 2 Recommended Operating Conditions (Note 2) −0.5 to +18 VDC DC Supply Voltage (VDD ) Input Voltage (VIN) DC Supply Voltage (VDD) −0.5 to VDD +0.5 VDC Storage Temperature −65°C to +150°C Range (TS) Dual-In-Line 700 mW Small Outline 500 mW (Soldering, 10 seconds) Note 2: VSS = 0V unless otherwise specified. 260°C DC Electrical Characteristics VOL Parameter VIH IOL IOH IIN −40°C Conditions Min Max +25°C Min +85°C Typ Max Min Max Units Quiescent Device VDD = 5V, VIN = VDD or VSS 20 0.02 20 150 µA VDD = 10V, VIN = VDD or VSS 40 0.02 40 300 µA VDD = 15V, VIN = VDD or VSS 80 0.02 80 600 µA LOW Level HIGH Level Output Voltage VIL (Note 2) Current Output Voltage VOH −40°C to +85°C Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed; they are not meant to imply that the devices should be operated at these limits. The tables of “Recommended Operating Conditions” and “Electrical Characteristics” provide conditions for actual device operation. Lead Temperature (TL) IDD 0 to VDD VDC Operating Temperature Range (TA) Power Dissipation (PD) Symbol 3.0 to 15 VDC Input Voltage (VIN) |IO| ≤ 1µA VDD = 5V 0.05 0 0.05 0.05 V VDD = 10V 0.05 0 0.05 0.05 V VDD = 15V 0.05 0 0.05 0.05 V |IO| ≤ 1 µA VDD = 5V 4.95 4.95 5 4.95 VDD = 10V 9.95 9.95 10 9.95 V VDD = 15V 14.95 14.95 15 14.95 V V LOW Level VDD = 5V, VO = 0.5V or 4.5V 1.5 2.25 1.5 1.5 Input Voltage VDD = 10V, VO = 1.0V or 9.0V 3.0 4.5 3.0 3.0 V VDD = 15V, VO = 1.5V or 13.5V 4.0 6.75 4.0 4.0 V V HIGH Level VDD = 5V, VO = 0.5V or 4.5V 3.5 3.5 2.75 3.5 V Input Voltage VDD = 10V, VO = 1.0V or 9.0V 7.0 7.0 5.5 7.0 V VDD = 15V, VO = 1.5V or 13.5V 11.0 11.0 8.25 11.0 V LOW Level Output VDD = 5V, VO = 0.4V 0.52 0.44 0.88 0.36 mA Current (Note 3) VDD = 10V, VO = 0.5V 1.3 1.1 2.25 0.9 mA VDD = 15V, VO = 1.5V 3.6 3.0 8.8 2.4 mA HIGH Level Output VDD = 5V, VO = 4.6V −0.52 −0.44 −0.88 −0.36 mA Current (Note 3) VDD = 10V, VO = 9.5V −1.3 −1.1 −2.25 −0.9 mA VDD = 15V, VO = 13.5V −3.6 Input Current VDD = 15V, VIN = 0V −0.30 −10−5 −0.30 −1.0 µA VDD = 15V, VIN = 15V 0.30 10−5 0.30 1.0 µA −3.0 −8.8 −2.4 mA Note 3: IOH and IOL are tested one output at a time. 3 www.fairchildsemi.com CD4099BC Absolute Maximum Ratings(Note 1) (Note 2) CD4099BC AC Electrical Characteristics (Note 4) TA = 25°C, CL = 50 pF, RL = 200k, Input tr = tf = 20 ns, unless otherwise noted Symbol tPHL, tPLH tPLH, tPHL tPHL tTLH, tTHL tTHL, tTLH TWH, TWL tWH, tWL tWH tSU tH tSU tH Typ Max Units Propagation Delay Parameter VDD = 5V Conditions Min 200 400 ns Data to Output VDD = 10V 75 150 ns VDD = 15V 50 100 ns Propagation Delay VDD = 5V 200 400 ns Enable to Output VDD = 10V 80 160 ns VDD = 15V 60 120 ns Propagation Delay VDD = 5V 175 350 ns Clear to Output VDD = 10V 80 160 ns VDD = 15V 65 130 ns Propagation Delay VDD = 5V 225 450 ns Address to Output VDD = 10V 100 200 ns VDD = 15V 75 150 ns Transition Time VDD = 5V 100 200 ns (Any Output) VDD = 10V 50 100 ns VDD = 15V 40 80 ns Minimum Data VDD = 5V 100 200 ns Pulse Width VDD = 10V 50 100 ns VDD = 15V 40 80 ns Minimum Address VDD = 5V 200 400 ns Pulse Width VDD = 10V 100 200 ns VDD = 15V 65 125 ns Minimum Clear VDD = 5V 75 150 ns Pulse Width VDD = 10V 40 75 ns ns VDD = 15V 25 50 Minimum Set-Up Time VDD = 5V 40 80 ns Data to E VDD = 10V 20 40 ns ns VDD = 15V 15 30 Minimum Hold Time VDD = 5V 60 120 ns Data to E VDD = 10V 30 60 ns VDD = 15V 25 50 ns Minimum Set-Up Time VDD = 5V −15 50 ns Address to E VDD = 10V 0 30 ns VDD = 15V 0 20 ns VDD = 5V −50 15 ns ns Minimum Hold Time Address to E CPD Power Dissipation Capacitance CIN Input Capacitance VDD = 10V −20 10 VDD = 15V −15 5 Per Package 100 ns pF (Note 5) Any Input 5.0 7.5 pF Note 4: AC Parameters are guaranteed by DC correlated testing. Note 5: Dynamic power dissipation (PD) is given by: PD = (CPD + CL) VCC2f + PQ; where CL = load capacitance; f = frequency of operation; for further details, see application note AN-90, “54C/74C Family Characteristics”. www.fairchildsemi.com 4 CD4099BC Switching Time Waveforms 5 www.fairchildsemi.com CD4099BC 8-Bit Addressable Latch Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Package Number N16E LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user. Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.