TI CD54HC109 Dual j-k flip-flop with set and reset positive-edge trigger Datasheet

[ /Title
(CD74H
C109,
CD74H
CT109)
/Subject
(Dual JK FlipFlop
with Set
and
Reset
CD54HC109, CD74HC109,
CD54HCT109, CD74HCT109
Data sheet acquired from Harris Semiconductor
SCHS140E
Dual J-K Flip-Flop with Set and Reset
Positive-Edge Trigger
March 1998 - Revised October 2003
Features
Description
• Asynchronous Set and Reset
The ’HC109 and ’HCT109 are dual J-K flip-flops with set and
reset. The flip-flop changes state with the positive transition
of Clock (1CP and 2CP).
• Schmitt Trigger Clock Inputs
• Typical fMAX = 54MHz at VCC = 5V, CL = 15pF,
TA = 25oC
The flip-flop is set and reset by active-low S and R,
respectively. A low on both the set and reset inputs
simultaneously will force both Q and Q outputs high.
However, both set and reset going high simultaneously
results in an unpredictable output condition.
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
Ordering Information
• Wide Operating Temperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
PART NUMBER
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH
Pinout
16 VCC
1J 2
15 2R
1K 3
14 2J
1CP 4
13 2K
1S 5
12 2CP
1Q 6
11 2S
1Q 7
10 2Q
GND 8
9 2Q
CD54HC109F3A
-55 to 125
16 Ld CERDIP
CD54HCT109F3A
-55 to 125
16 Ld CERDIP
CD74HC109E
-55 to 125
16 Ld PDIP
CD74HC109M
-55 to 125
16 Ld SOIC
CD74HC109MT
-55 to 125
16 Ld SOIC
CD74HC109M96
-55 to 125
16 Ld SOIC
CD74HCT109E
-55 to 125
16 Ld PDIP
CD74HCT109M
-55 to 125
16 Ld SOIC
CD74HCT109MT
-55 to 125
16 Ld SOIC
CD74HCT109M96
-55 to 125
16 Ld SOIC
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
© 2003, Texas Instruments Incorporated
PACKAGE
NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel. The suffix T denotes a small-quantity reel of
250.
CD54HC109, CD54HCT109
(CERDIP)
CD74HC109, CD74HCT109
(PDIP, SOIC)
TOP VIEW
1R 1
TEMP. RANGE
(oC)
1
CD54HC109, CD74HC109, CD54HCT109, CD74HCT109
Functional Diagram
1S
1J
1K
1CP
1R
2S
2J
2K
2CP
2R
5
2
6
1Q
3
F/F 1
7
1Q
4
1
11
14
10
2Q
13
F/F 2
9
2Q
12
GND = 8
VCC = 16
15
TRUTH TABLE
INPUTS
OUTPUTS
S
R
CP
J
K
Q
Q
L
H
X
X
X
H
L
H
L
X
X
X
L
H
L
L
X
X
X
H (Note 1)
H (Note 1)
H
H
↑
L
L
L
H
H
↑
H
L
Toggle
H
H
↑
L
H
No Change
H
H
↑
H
H
H
H
L
X
X
H
H
L
No Change
H= High Level (Steady State)
L= Low Level (Steady State)
X= Don’t Care
↑= Low-to-High Transition
NOTE:
1. Unpredictable and unstable condition if both S and R go high simultaneously
Logic Diagram
5(11)
S
2(14)
J
J S
3(13)
K
K
FF
4(12)
CP
1(15)
R
16
VCC
Q
8
GND
2
CL
CL
R Q
6(10)
Q
7(9)
Q
CD54HC109, CD74HC109, CD54HCT109, CD74HCT109
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, IIK
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA
DC Drain Current, per Output, IO
For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±25mA
DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA
Thermal Resistance (Typical, Note 2)
θJA (oC/W)
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . .
67
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . .
73
Maximum Junction Temperature (Hermetic Package or Die) . . . 175oC
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC
CP Input Rise and Fall Time, tr, tf
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0ms (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0ms (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0ms (Max)
Input Rise and Fall Time (All Inputs Except CP), tr, tf
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
2. The package thermal impedance is calculated in accordance with JESD 51-7
DC Electrical Specifications
TEST
CONDITIONS
PARAMETER
SYMBOL
VI (V)
VIH
-
25oC
IO (mA) VCC (V)
-40oC TO 85oC
-55oC TO 125oC
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
2
1.5
-
-
1.5
-
1.5
-
V
4.5
3.15
-
-
3.15
-
3.15
-
V
6
4.2
-
-
4.2
-
4.2
-
V
2
-
-
0.5
-
0.5
-
0.5
V
4.5
-
-
1.35
-
1.35
-
1.35
V
6
-
-
1.8
-
1.8
-
1.8
V
HC TYPES
High Level Input
Voltage
Low Level Input
Voltage
High Level Output
Voltage
CMOS Loads
High Level Output
Voltage
TTL Loads
VIL
VOH
-
VIH or
VIL
-
-
-0.02
2
1.9
-
-
1.9
-
1.9
-
V
4.5
4.4
-
-
4.4
-
4.4
-
V
6
5.9
-
-
5.9
-
5.9
-
V
-
-
-
-
-
-
-
-
-
V
-4
4.5
3.96
-
-
3.84
-
3.7
-
V
-5.2
6
5.48
-
-
5.34
-
5.2
-
V
3
CD54HC109, CD74HC109, CD54HCT109, CD74HCT109
DC Electrical Specifications
(Continued)
TEST
CONDITIONS
PARAMETER
Low Level Output
Voltage
CMOS Loads
SYMBOL
VI (V)
VOL
VIH or
VIL
Low Level Output
Voltage
TTL Loads
25oC
IO (mA) VCC (V)
-40oC TO 85oC
-55oC TO 125oC
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
2
-
-
0.1
-
0.1
-
0.1
V
4.5
-
-
0.1
-
0.1
-
0.1
V
6
-
-
0.1
-
0.1
-
0.1
V
-
-
-
-
-
-
-
-
-
V
4
4.5
-
-
0.26
-
0.33
-
0.4
V
5.2
6
-
-
0.26
-
0.33
-
0.4
V
0.02
II
VCC or
GND
-
6
-
-
±0.1
-
±1
-
±1
µA
ICC
VCC or
GND
0
6
-
-
4
-
40
-
80
µA
High Level Input
Voltage
VIH
-
-
4.5 to
5.5
2
-
-
2
-
2
-
V
Low Level Input
Voltage
VIL
-
-
4.5 to
5.5
-
-
0.8
-
0.8
-
0.8
V
High Level Output
Voltage
CMOS Loads
VOH
VIH or
VIL
-0.02
4.5
4.4
-
-
4.4
-
4.4
-
V
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
4
4.5
-
-
0.26
-
0.33
-
0.4
V
±0.1
-
±1
-
±1
µA
Input Leakage
Current
Quiescent Device
Current
HCT TYPES
High Level Output
Voltage
TTL Loads
Low Level Output
Voltage CMOS Loads
VOL
VIH or
VIL
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
Quiescent Device
Current
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
II
VCC
and
GND
-
5.5
-
ICC
VCC or
GND
0
5.5
-
-
4
-
40
-
80
µA
∆ICC
(Note 3)
VCC
- 2.1
-
4.5 to
5.5
-
100
360
-
450
-
490
µA
NOTE:
3. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.
HCT Input Loading Table
INPUT
UNIT LOADS
All
0.3
NOTE: Unit Load is ∆ICC limit specified in DC Electrical Specifications table, e.g., 360µA max at 25oC.
4
CD54HC109, CD74HC109, CD54HCT109, CD74HCT109
Prerequisite For Switching Specifications
PARAMETER
25oC
-40oC TO 85oC -55oC TO 125oC
SYMBOL
TEST
CONDITIONS
VCC
(V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
tSU
-
2
80
-
-
100
-
120
-
ns
4.5
16
-
-
20
-
24
-
ns
6
14
-
-
17
-
20
-
ns
2
5
-
-
5
-
5
-
ns
4.5
5
-
-
5
-
5
-
ns
6
5
-
-
5
-
5
-
ns
2
80
-
-
100
-
120
-
ns
4.5
16
-
-
20
-
24
-
ns
6
14
-
-
17
-
20
-
ns
2
80
-
-
100
-
120
-
ns
HC TYPES
Setup Time J, K, to CP
Hold Time J, K, to CP
Removal Time R, S, to CP
Pulse Width CP, R, S
CP Frequency
tH
-
tREM
-
tW
-
fMAX
-
4.5
16
-
-
20
-
24
-
ns
6
14
-
-
17
-
20
-
ns
2
6
-
-
5
-
4
-
MHz
4.5
30
-
-
25
-
20
-
MHz
6
35
-
-
29
-
23
-
MHz
HCT TYPES
Setup Time J, K to CP
tSU
-
4.5
18
-
-
23
-
27
-
ns
Hold Time J, K to CP
tH
-
4.5
3
-
-
3
-
3
-
ns
tREM
-
4.5
18
-
-
23
-
27
-
ns
tW
-
4.5
18
-
-
23
-
27
-
ns
fMAX
-
4.5
27
-
-
22
-
18
-
MHz
SYMBOL
TEST
CONDITIONS
VCC
(V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
tPLH, tPHL
CL = 50pF
2
-
-
175
-
220
-
265
ns
CL = 50pF
4.5
-
-
35
-
44
-
53
ns
CL = 15pF
5
-
14
-
-
-
-
-
ns
CL = 50pF
6
-
-
30
-
37
-
45
ns
CL = 50pF
2
-
-
120
-
150
-
180
ns
CL = 50pF
4.5
-
-
24
-
30
-
36
ns
CL = 15pF
5
-
9
-
-
-
-
-
ns
CL = 50pF
6
-
-
20
-
26
-
31
ns
CL = 50pF
2
-
-
155
-
195
-
235
ns
CL = 50pF
4.5
-
-
31
-
39
-
47
ns
CL = 15pF
5
-
13
-
-
-
-
-
ns
CL = 50pF
6
-
-
26
-
33
-
40
ns
Removal Time R, S, to CP
Pulse Width CP, R, S
CP Frequency
Switching Specifications Input tr, tf = 6ns
PARAMETER
25oC
-40oC TO 85oC -55oC TO 125oC
HC TYPES
Propagation Delay,
CP → Q, Q
Propagation Delay,
S→Q
Propagation Delay,
S→Q
tPLH, tPHL
tPLH, tPHL
5
CD54HC109, CD74HC109, CD54HCT109, CD74HCT109
Switching Specifications Input tr, tf = 6ns
PARAMETER
Propagation Delay,
R→Q
Propagation Delay,
R→Q
Transition Time
Input Capacitance
(Continued)
25oC
-40oC TO 85oC -55oC TO 125oC
SYMBOL
TEST
CONDITIONS
tPLH, tPHL
CL = 50pF
2
-
-
185
-
230
-
280
ns
CL = 50pF
4.5
-
-
37
-
46
-
56
ns
CL = 15pF
5
-
15
-
-
-
-
-
ns
CL = 50pF
6
-
-
31
-
39
-
48
ns
CL = 50pF
2
-
-
170
-
215
-
255
ns
CL = 50pF
4.5
-
-
34
-
43
-
51
ns
CL = 15pF
5
-
14
-
-
-
-
-
ns
CL = 50pF
6
-
-
29
-
37
-
43
ns
CL = 50pF
2
-
-
75
-
95
-
110
ns
CL = 50pF
4.5
-
-
15
-
19
-
22
ns
CL = 50pF
6
-
-
13
-
16
-
19
ns
-
-
-
10
-
10
-
10
pF
5
-
60
-
-
-
-
-
MHz
5
-
30
-
-
-
-
-
pF
CL = 50pF
4.5
-
-
40
-
50
-
60
ns
CL = 15pF
5
-
17
-
-
-
-
-
ns
CL = 50pF
4.5
-
-
30
-
38
-
45
ns
CL = 15pF
5
-
12
-
-
-
-
-
ns
CL = 50pF
4.5
-
-
45
-
56
-
68
ns
CL = 15pF
5
-
19
-
-
-
-
-
ns
CL = 50pF
4.5
-
-
45
-
56
-
68
ns
CL = 15pF
5
-
19
-
-
-
-
-
ns
CL = 50pF
4.5
-
-
37
-
46
-
56
ns
CL = 15pF
5
-
15
-
-
-
-
-
ns
CL = 50pF
4.5
-
-
15
-
19
-
22
ns
tPLH, tPHL
tTLH, tTHL
CI
CP Frequency
fMAX
Power Dissipation Capacitance
(Notes 4, 5)
CPD
CL = 15pF
-
VCC
(V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
HCT TYPES
Propagation Delay,
CP → Q, Q
tPLH, tPHL
Propagation Delay,
S→Q
tPLH, tPHL
Propagation Delay,
S→Q
tPLH, tPHL
Propagation Delay,
R→Q
tPLH, tPHL
Propagation Delay,
R→Q
tPLH, tPHL
Transition Time (Figure 5)
tTLH, tTHL
Input Capacitance
CI
-
-
-
-
10
-
10
-
10
pF
CP Frequency
fMAX
CL = 15pF
5
-
54
-
-
-
-
-
MHz
Power Dissipation Capacitance
(Notes 4, 5)
CPD
-
5
-
33
-
-
-
-
-
pF
NOTES:
4. CPD is used to determine the dynamic power consumption, per flip-flop.
5. PD = CPD VCC2 fi + Σ CL fo where fi = input frequency, fo = output frequency, CL = output load capacitance, VCC = supply voltage.
6
CD54HC109, CD74HC109, CD54HCT109, CD74HCT109
Test Circuits and Waveforms
tWL + tWH =
tfCL
trCL
50%
10%
10%
tf = 6ns
tr = 6ns
GND
tTLH
90%
INVERTING
OUTPUT
tPHL
FIGURE 9. HC AND HCU TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC
trCL
VCC
tfCL
GND
1.3V
0.3V
GND
tH(H)
tH(L)
VCC
DATA
INPUT
3V
2.7V
CLOCK
INPUT
50%
tH(H)
tPLH
FIGURE 10. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
tfCL
10%
tTLH
1.3V
10%
tPLH
90%
GND
tTHL
90%
50%
10%
trCL
3V
2.7V
1.3V
0.3V
INPUT
tTHL
tPHL
tWH
FIGURE 8. HCT CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
VCC
INVERTING
OUTPUT
GND
NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table. For fMAX, input duty cycle = 50%.
tf = 6ns
90%
50%
10%
1.3V
1.3V
tWL
tWH
FIGURE 7. HC CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
INPUT
1.3V
0.3V
0.3V
GND
tr = 6ns
DATA
INPUT
50%
tH(L)
3V
1.3V
1.3V
1.3V
GND
tSU(H)
tSU(H)
tSU(L)
tTLH
90%
OUTPUT
tTHL
90%
50%
10%
tTLH
90%
1.3V
OUTPUT
tREM
3V
SET, RESET
OR PRESET
GND
tTHL
1.3V
10%
FIGURE 11. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
tPHL
1.3V
GND
IC
CL
50pF
GND
90%
tPLH
50%
IC
tSU(L)
tPHL
tPLH
I
fCL
3V
2.7V
CLOCK
NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table. For fMAX, input duty cycle = 50%.
tREM
VCC
SET, RESET
OR PRESET
tfCL = 6ns
fCL
50%
50%
tWL
CLOCK
INPUT
tWL + tWH =
trCL = 6ns
VCC
90%
CLOCK
I
CL
50pF
FIGURE 12. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
7
PACKAGE OPTION ADDENDUM
www.ti.com
9-Oct-2007
PACKAGING INFORMATION
(1)
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
5962-9070101MEA
ACTIVE
CDIP
J
16
1
TBD
A42 SNPB
N / A for Pkg Type
CD54HC109F3A
ACTIVE
CDIP
J
16
1
TBD
A42 SNPB
N / A for Pkg Type
CD54HCT109F3A
ACTIVE
CDIP
J
16
1
TBD
A42 SNPB
N / A for Pkg Type
CD74HC109E
ACTIVE
PDIP
N
16
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
CD74HC109EE4
ACTIVE
PDIP
N
16
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
CD74HC109M
ACTIVE
SOIC
D
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HC109M96
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HC109M96E4
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HC109M96G4
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HC109ME4
ACTIVE
SOIC
D
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HC109MG4
ACTIVE
SOIC
D
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HC109MT
ACTIVE
SOIC
D
16
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HC109MTE4
ACTIVE
SOIC
D
16
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HC109MTG4
ACTIVE
SOIC
D
16
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HCT109E
ACTIVE
PDIP
N
16
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
CD74HCT109EE4
ACTIVE
PDIP
N
16
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
CD74HCT109M
ACTIVE
SOIC
D
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HCT109M96
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HCT109M96E4
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HCT109M96G4
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HCT109ME4
ACTIVE
SOIC
D
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HCT109MG4
ACTIVE
SOIC
D
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HCT109MT
ACTIVE
SOIC
D
16
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HCT109MTE4
ACTIVE
SOIC
D
16
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HCT109MTG4
ACTIVE
SOIC
D
16
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
The marketing status values are defined as follows:
Addendum-Page 1
Lead/Ball Finish
MSL Peak Temp (3)
PACKAGE OPTION ADDENDUM
www.ti.com
9-Oct-2007
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Mar-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
Diameter Width
(mm) W1 (mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
CD74HC109M96
SOIC
D
16
2500
330.0
16.4
6.5
10.3
2.1
8.0
16.0
Q1
CD74HCT109M96
SOIC
D
16
2500
330.0
16.4
6.5
10.3
2.1
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Mar-2008
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
CD74HC109M96
SOIC
D
16
2500
333.2
345.9
28.6
CD74HCT109M96
SOIC
D
16
2500
333.2
345.9
28.6
Pack Materials-Page 2
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