TI1 CD54HC4520F3A High-speed cmos logic dual synchronous counter Datasheet

[ /Title
(CD74
HC451
8,
CD74
HC452
0,
CD74
HCT45
20)
/Subject
CD74HC4518, CD54HC4520,
CD74HC4520, CD74HCT4520
Data sheet acquired from Harris Semiconductor
SCHS216D
High-Speed CMOS Logic
Dual Synchronous Counters
November 1997 - Revised October 2003
Features
having interchangeable CLOCK and ENABLE lines for
incrementing on either the positive-going or the negativegoing transition of CLOCK. The counters are cleared by high
levels on the MASTER RESET lines. The counter can be
cascaded in the ripple mode by connecting Q3 to the
ENABLE input of the subsequent counter while the CLOCK
input of the latter is held low.
• Positive or Negative Edge Triggering
• Synchronous Internal Carry Propagation
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
Ordering Information
• Wide Operating Temperature Range . . . -55oC to 125oC
TEMP. RANGE
(oC)
PACKAGE
CD54HC4520F3A
-55 to 125
16 Ld CERDIP
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V
CD74HC4518E
-55 to 125
16 Ld PDIP
CD74HC4520E
-55 to 125
16 Ld PDIP
CD74HC4520M
-55 to 125
16 Ld SOIC
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH
CD74HC4520MT
-55 to 125
16 Ld SOIC
CD74HC4520M96
-55 to 125
16 Ld SOIC
CD74HCT4520E
-55 to 125
16 Ld PDIP
CD74HCT4520M
-55 to 125
16 Ld SOIC
Description
CD74HCT4520MT
-55 to 125
16 Ld SOIC
CD74HCT4520M96
-55 to 125
16 Ld SOIC
• Balanced Propagation Delay and Transition Times
PART NUMBER
• Significant Power Reduction Compared to LSTTL
Logic ICs
The CD74HC4518 is a dual BCD up-counter. The ’HC4520
and CD74HCT4520 are dual binary up-counters. Each
device consists of two independent internally synchronous
4-stage counters. The counter stages are D-type flip-flops
NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel. The suffix T denotes a small-quantity reel
of 250.
Pinout
CD54HC4520
(CERDIP)
CD74HC4518
(PDIP)
CD74HC4520, CD74HCT4520,
(PDIP, SOIC)
TOP VIEW
1CP 1
16 VCC
1E 2
15 2MR
1Q0 3
14 2Q3
1Q1 4
13 2Q2
1Q2 5
12 2Q1
1Q3 6
11 2Q0
1MR 7
10 2E
9 2CP
GND 8
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
© 2003, Texas Instruments Incorporated
1
CD74HC4518, CD54HC4520, CD74HC4520, CD74HCT4520
Functional Diagram
1CP
1E
÷10/÷16
1
2CP
2E
1Q1
2
CL
5
1Q2
6
1Q3
7
÷10/÷16
9
11
2Q0
12
2Q1
10
CL
13
2Q2
R
2MR
1Q0
4
R
1MR
3
14
2Q3
GND = 8
VCC = 16
15
TRUTH TABLE
CP
E
MR
OUTPUT STATE
↑
H
L
Increment Counter
L
↓
L
Increment Counter
↓
X
L
No Change
X
↑
L
No Change
↑
L
L
No Change
H
↓
L
No Change
X
X
H
Q0 thru Q3 = L
H
= High State.
L
= Low State.
↑
= High-to-Low Transition.
↓
= Low-to-High Transition.
X
= Don’t Care.
2
CD74HC4518, CD54HC4520, CD74HC4520, CD74HCT4520
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, IIK
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA
Thermal Resistance (Typical, Note 1)
θJA (oC/W)
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
TEST
CONDITIONS
PARAMETER
25oC
-40oC TO 85oC
-55oC TO
125oC
SYMBOL
VI (V)
IO (mA)
VCC (V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
VIH
-
-
2
1.5
-
-
1.5
-
1.5
-
V
4.5
3.15
-
-
3.15
-
3.15
-
V
6
4.2
-
-
4.2
-
4.2
-
V
HC TYPES
High Level Input
Voltage
Low Level Input
Voltage
High Level Output
Voltage
CMOS Loads
VIL
VOH
-
VIH or VIL
High Level Output
Voltage
TTL Loads
Low Level Output
Voltage
CMOS Loads
VOL
VIH or VIL
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
Quiescent Device
Current
-
2
-
-
0.5
-
0.5
-
0.5
V
4.5
-
-
1.35
-
1.35
-
1.35
V
6
-
-
1.8
-
1.8
-
1.8
V
-0.02
2
1.9
-
-
1.9
-
1.9
-
V
-0.02
4.5
4.4
-
-
4.4
-
4.4
-
V
-0.02
6
5.9
-
-
5.9
-
5.9
-
V
-
-
-
-
-
-
-
-
-
V
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
-5.2
6
5.48
-
-
5.34
-
5.2
-
V
0.02
2
-
-
0.1
-
0.1
-
0.1
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
0.02
6
-
-
0.1
-
0.1
-
0.1
V
-
-
-
-
-
-
-
-
-
V
4
4.5
-
-
0.26
-
0.33
-
0.4
V
5.2
6
-
-
0.26
-
0.33
-
0.4
V
II
VCC or
GND
-
6
-
-
±0.1
-
±1
-
±1
µA
ICC
VCC or
GND
0
6
-
-
8
-
80
-
160
µA
3
CD74HC4518, CD54HC4520, CD74HC4520, CD74HCT4520
DC Electrical Specifications
(Continued)
TEST
CONDITIONS
25oC
-55oC TO
125oC
-40oC TO 85oC
SYMBOL
VI (V)
IO (mA)
VCC (V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
High Level Input
Voltage
VIH
-
-
4.5 to 5.5
2
-
-
2
-
2
-
V
Low Level Input
Voltage
VIL
-
-
4.5 to 5.5
-
-
0.8
-
0.8
-
0.8
V
High Level Output
Voltage
CMOS Loads
VOH
VIH or VIL
-0.02
4.5
4.4
-
-
4.4
-
4.4
-
V
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
4
4.5
-
-
0.26
-
0.33
-
0.4
V
PARAMETER
HCT TYPES
High Level Output
Voltage
TTL Loads
Low Level Output
Voltage
CMOS Loads
VOL
VIH or VIL
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
Quiescent Device
Current
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
II
VCC and
GND
0
5.5
-
-
±0.1
-
±1
-
±1
µA
ICC
VCC or
GND
0
5.5
-
-
8
-
80
-
160
µA
∆ICC
(Note 2)
VCC
-2.1
-
4.5 to 5.5
-
100
360
-
450
-
490
µA
NOTE:
2. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.
HCT Input Loading Table
INPUT
UNIT LOADS
MR
1.2
CP
0.25
ENABLE
0.5
NOTE: Unit Load is ∆ICC limit specified in DC Electrical Table, e.g.,
360µA max at 25oC.
Prerequisite for Switching Specifications
25oC
PARAMETER
-40oC TO 85oC
-55oC TO 125oC
SYMBOL
VCC (V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
fMAX
2
6
-
-
5
-
4
-
MHz
4.5
30
-
-
24
-
20
-
MHz
6
35
-
-
28
-
24
-
MHz
2
80
-
-
100
-
120
-
ns
4.5
16
-
-
20
-
24
-
ns
HC TYPES
Maximum Clock
Frequency
CP Pulse Width
MR Pulse Width
tW
tW
6
14
-
-
17
-
20
-
ns
2
100
-
-
125
-
150
-
ns
4.5
20
-
-
25
-
30
-
ns
6
17
-
-
21
-
26
-
ns
4
CD74HC4518, CD54HC4520, CD74HC4520, CD74HCT4520
Prerequisite for Switching Specifications
(Continued)
25oC
PARAMETER
Set-up Time,
Enable to CP
Removal Time,
MR to CP
Set-up Time,
CP to Enable
Removal Time,
MR to Enable
-40oC TO 85oC
-55oC TO 125oC
SYMBOL
VCC (V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
tSU
2
80
-
-
100
-
120
-
ns
4.5
16
-
-
20
-
24
-
ns
6
14
-
-
17
-
20
-
ns
2
0
-
-
0
-
0
-
ns
4.5
0
-
-
0
-
0
-
ns
tREM
tSU
tREM
6
0
-
-
0
-
0
-
ns
2
80
-
-
100
-
120
-
ns
4.5
16
-
-
20
-
24
-
ns
6
14
-
-
17
-
20
-
ns
2
0
-
-
0
-
0
-
ns
4.5
0
-
-
0
-
0
-
ns
6
0
-
-
0
-
0
-
ns
fMAX
4.5
25
-
-
20
-
17
-
MHz
Clock Pulse Width
tW
4.5
20
-
-
25
-
30
-
ns
MR Pulse Width
tW
4.5
20
-
-
25
-
30
-
ns
Set-up Time,
Enable to CP
tSU
4.5
16
-
-
20
-
24
-
ns
tREM
4.5
0
-
-
0
-
0
-
ns
HCT TYPES
Maximum Clock
Frequency
Removal Time,
MR tp Enable
Switching Specifications Input tr, tf = 6ns
PARAMETER
HC TYPES
Propagation Delay
CP to Qn
Enable to Qn
MR to Qn
Output Transition Time
TEST
SYMBOL CONDITIONS
tPLH,
tPHL
tPLH,
tPHL
tPLH,
tPHL
tTHL, tTLH
VCC (V)
MIN
TYP
MAX
MIN
MAX
-55oC TO 125oC
MIN
MAX
UNITS
CL = 50pF
2
-
-
240
-
300
-
360
ns
CL = 50pF
4.5
-
-
48
-
60
-
72
ns
CL = 15pF
5
-
20
-
-
-
-
-
ns
CL = 50pF
6
-
-
41
-
51
-
61
ns
CL = 50pF
2
-
-
240
-
300
-
360
ns
CL = 50pF
4.5
-
-
48
-
60
-
72
ns
CL = 15pF
5
-
20
-
-
-
-
-
ns
CL = 50pF
6
-
-
41
-
51
-
61
ns
CL = 50pF
2
-
-
150
-
190
-
225
ns
CL = 50pF
4.5
-
-
30
-
38
-
45
ns
CL = 15pF
5
-
12
-
-
-
-
-
ns
CL = 50pF
6
-
-
26
-
33
-
38
ns
CL = 50pF
2
-
-
75
-
95
-
110
ns
CL = 50pF
4.5
-
-
15
-
19
-
22
ns
19
ns
-
-
10
-
10
-
10
pF
-
33
-
-
-
-
-
CL = 50pF
6
CIN
CL = 50pF
-
Maximum Clock Frequency
fMAX
CL = 15pF
5
Power Dissipation Capacitance
(Note 3, 4)
CPD
CL = 15pF
5
Input Capacitance
-40oC TO
85oC
25oC
13
16
60
5
MHz
pF
CD74HC4518, CD54HC4520, CD74HC4520, CD74HCT4520
Switching Specifications Input tr, tf = 6ns
(Continued)
TEST
SYMBOL CONDITIONS
PARAMETER
-40oC TO
85oC
25oC
-55oC TO 125oC
VCC (V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
4.5
-
-
53
-
66
-
80
ns
HCT TYPES
Propagation Delay
CP to Qn
tPLH,
tPHL
CL = 50pF
CL = 15pF
5
-
22
-
-
-
-
-
ns
CL = 50pF
4.5
-
-
55
-
69
-
83
ns
Enable to Qn
tPLH,
tPHL
MR to Qn
tPLH,
tPHL
CL = 15pF
tTHL, tTLH
CL = 50pF
Output Transition Time
Input Capacitance
CL = 15pF
5
-
23
-
-
-
-
-
ns
CL = 50pF
4.5
-
-
35
-
44
-
53
ns
5
-
14
-
-
-
-
-
ns
4.5
-
-
15
-
19
-
22
ns
CIN
CL = 50pF
-
-
-
10
-
10
-
10
pF
Maximum Clock Frequency
fMAX
CL = 15pF
5
-
50
-
-
-
-
-
MHz
Power Dissipation Capacitance
(Note 3,4)
CPD
-
5
-
33
-
-
-
-
-
pF
NOTES:
3. CPD is used to determine the dynamic power consumption, per counter.
4. PD = VCC2 fi (CPD + CL) where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.
Timing Diagram
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
CLOCK
ENABLE
MASTER RESET
0
1
2
3
4
5
6
7
8
9
0
0
1
2
3 4
Q1
Q2
HC4518
Q3
Q4
Q1
Q2
’HC/HCT4520
Q3
Q4
FIGURE 1.
6
CD74HC4518, CD54HC4520, CD74HC4520, CD74HCT4520
Waveforms
tWL + tWH =
tfCL
trCL
50%
10%
10%
tf = 6ns
tr = 6ns
tTLH
90%
INVERTING
OUTPUT
tPHL
FIGURE 4. HC TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
tPLH
FIGURE 5. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
trCL
tfCL
VCC
tfCL
GND
1.3V
0.3V
GND
tH(H)
tH(L)
VCC
DATA
INPUT
3V
2.7V
CLOCK
INPUT
50%
tH(H)
tTLH
1.3V
10%
tPLH
10%
GND
tTHL
90%
50%
10%
90%
3V
2.7V
1.3V
0.3V
GND
tTHL
trCL
tWH
FIGURE 3. HCT CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
INPUT
INVERTING
OUTPUT
GND
NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table. For fMAX, input duty cycle = 50%.
VCC
90%
50%
10%
1.3V
1.3V
tWL
tf = 6ns
tPHL
1.3V
0.3V
tWH
FIGURE 2. HC CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
INPUT
2.7V
0.3V
GND
tr = 6ns
DATA
INPUT
50%
tH(L)
3V
1.3V
1.3V
1.3V
GND
tSU(H)
tSU(H)
tSU(L)
tTLH
90%
OUTPUT
tTHL
90%
50%
10%
tTLH
90%
1.3V
OUTPUT
tREM
3V
SET, RESET
OR PRESET
GND
tTHL
1.3V
10%
FIGURE 6. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
tPHL
1.3V
GND
IC
CL
50pF
GND
90%
tPLH
50%
IC
tSU(L)
tPHL
tPLH
I
fCL
3V
NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table. For fMAX, input duty cycle = 50%.
tREM
VCC
SET, RESET
OR PRESET
tfCL = 6ns
CLOCK
50%
50%
tWL
CLOCK
INPUT
tWL + tWH =
trCL = 6ns
VCC
90%
CLOCK
I
fCL
CL
50pF
FIGURE 7. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
7
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
5962-8995401EA
ACTIVE
CDIP
J
16
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-8995401EA
CD54HC4520F3A
CD54HC4520F
ACTIVE
CDIP
J
16
1
TBD
A42
N / A for Pkg Type
-55 to 125
CD54HC4520F
CD54HC4520F3A
ACTIVE
CDIP
J
16
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-8995401EA
CD54HC4520F3A
CD74HC4518E
ACTIVE
PDIP
N
16
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-55 to 125
CD74HC4518E
CD74HC4520E
ACTIVE
PDIP
N
16
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-55 to 125
CD74HC4520E
CD74HC4520M
ACTIVE
SOIC
D
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC4520M
CD74HC4520M96
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC4520M
CD74HC4520M96G4
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC4520M
CD74HC4520ME4
ACTIVE
SOIC
D
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC4520M
CD74HC4520MG4
ACTIVE
SOIC
D
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC4520M
CD74HC4520MT
ACTIVE
SOIC
D
16
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC4520M
CD74HCT4520E
ACTIVE
PDIP
N
16
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-55 to 125
CD74HCT4520E
CD74HCT4520EE4
ACTIVE
PDIP
N
16
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-55 to 125
CD74HCT4520E
CD74HCT4520M
ACTIVE
SOIC
D
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
HCT4520M
CD74HCT4520M96
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
HCT4520M
CD74HCT4520MG4
ACTIVE
SOIC
D
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
HCT4520M
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2014
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF CD54HC4520, CD74HC4520 :
• Catalog: CD74HC4520
• Military: CD54HC4520
NOTE: Qualified Version Definitions:
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2014
• Catalog - TI's standard catalog product
• Military - QML certified for Military and Defense Applications
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Mar-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
Diameter Width
(mm) W1 (mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
CD74HC4520M96
SOIC
D
16
2500
330.0
16.4
6.5
10.3
2.1
8.0
16.0
Q1
CD74HCT4520M96
SOIC
D
16
2500
330.0
16.4
6.5
10.3
2.1
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Mar-2008
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
CD74HC4520M96
SOIC
D
16
2500
333.2
345.9
28.6
CD74HCT4520M96
SOIC
D
16
2500
333.2
345.9
28.6
Pack Materials-Page 2
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