TI CD54HC640 High-speed cmos logic octal three-state bus transceiver, inverting Datasheet

[ /Title
(CD74
HC640
,
CD74
HCT64
0)
/Subject
(High
Speed
CMOS
CD54HC640, CD74HC640,
CD54HCT640, CD74HCT640
Data sheet acquired from Harris Semiconductor
SCHS192B
January 1998 - Revised May 2003
High-Speed CMOS Logic
Octal Three-State Bus Transceiver, Inverting
Features
Description
• Buffered Inputs
The ’HC640 and ’HCT640 silicon-gate CMOS three-state
bidirectional inverting and non-inverting buffers are intended
for two-way asynchronous communication between data
buses. They have high drive current outputs which enable
high-speed operation when driving large bus capacitances.
These circuits possess the low power dissipation of CMOS
circuits, and have speeds comparable to low power Schottky
TTL circuits. They can drive 15 LSTTL loads. The ’HC640
and ’HCT640 are inverting buffers.
• Three-State Outputs
• Applications in Multiple-Data-Bus Architecture
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55oC to 125oC
The direction of data flow (A to B, B to A) is controlled by the
DIR input.
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
Outputs are enabled by a low on the Output Enable input
(OE); a high OE puts these devices in the high impedance
mode.
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V
Ordering Information
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH
PART NUMBER
Pinout
CD54HC640, CD54HCT640
(CERDIP)
CD74HC640, CD74HCT640
(PDIP, SOIC)
TOP VIEW
DIR
1
20 VCC
A0
2
19 OE
A1
3
18 B0
A2
4
17 B1
A3
5
16 B2
A4
6
15 B3
A5
7
14 B4
A6
8
13 B5
A7
9
12 B6
GND 10
11 B7
TEMP. RANGE
(oC)
CD54HC640F3A
-55 to 125
20 Ld CERDIP
CD54HCT640F3A
-55 to 125
20 Ld CERDIP
CD74HC640E
-55 to 125
20 Ld PDIP
CD74HC640M
-55 to 125
20 Ld SOIC
CD74HCT640E
-55 to 125
20 Ld PDIP
CD74HCT640M
-55 to 125
20 Ld SOIC
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
© 2003, Texas Instruments Incorporated
1
PACKAGE
CD54HC640, CD74HC640, CD54HCT640, CD74HCT640
Functional Diagram
A0
B0
A1
THRU
A6
B1
THRU
B6
A7
B7
OE
DIR
OUTPUT ENABLE AND
DIRECTION-SELECT LOGIC
TRUTH TABLE
CONTROL INPUTS
DATA PORT STATUS
OE
DIR
An
Bn
L
L
O
I
H
H
Z
Z
H
L
Z
Z
L
H
I
O
To prevent excess currents in the High-Z modes all I/O terminals
should be terminated with 1kΩ to 1MΩ resistors.
H = High Level
L = Low Level
I = Input
O = Output (Inversion of Input Level)
Z = High Impedance
2
VCC = 20
GND = 10
CD54HC640, CD74HC640, CD54HCT640, CD74HCT640
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, IIK
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
DC Drain Current, per Output, IO
For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±35mA
DC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA
Thermal Resistance (Typical, Note 1)
θJA (oC/W)
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . .
69
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . .
58
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
TEST
CONDITIONS
SYMBOL
VI (V)
IO (mA)
High Level Input
Voltage
VIH
-
-
Low Level Input
Voltage
VIL
High Level Output
Voltage
CMOS Loads
VOH
PARAMETER
VCC
(V)
25oC
-40oC TO 85oC -55oC TO 125oC
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
HC TYPES
-
VIH or VIL
High Level Output
Voltage
TTL Loads
Low Level Output
Voltage
CMOS Loads
VOL
VIH or VIL
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
II
VCC or
GND
-
2
1.5
-
-
1.5
-
1.5
-
V
4.5
3.15
-
-
3.15
-
3.15
-
V
6
4.2
-
-
4.2
-
4.2
-
V
2
-
-
0.5
-
0.5
-
0.5
V
4.5
-
-
1.35
-
1.35
-
1.35
V
6
-
-
1.8
-
1.8
-
1.8
V
-0.02
2
1.9
-
-
1.9
-
1.9
-
V
-0.02
4.5
4.4
-
-
4.4
-
4.4
-
V
-0.02
6
5.9
-
-
5.9
-
5.9
-
V
-
-
-
-
-
-
-
-
-
V
-6
4.5
3.98
-
-
3.84
-
3.7
-
V
-7.8
6
5.48
-
-
5.34
-
5.2
-
V
0.02
2
-
-
0.1
-
0.1
-
0.1
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
0.02
6
-
-
0.1
-
0.1
-
0.1
V
-
-
-
-
-
-
-
-
-
V
6
4.5
-
-
0.26
-
0.33
-
0.4
V
7.8
6
-
-
0.26
-
0.33
-
0.4
V
-
6
-
-
±0.1
-
±1
-
±1
µA
3
CD54HC640, CD74HC640, CD54HCT640, CD74HCT640
DC Electrical Specifications
(Continued)
TEST
CONDITIONS
25oC
-40oC TO 85oC -55oC TO 125oC
SYMBOL
VI (V)
IO (mA)
VCC
(V)
Quiescent Device
Current
ICC
VCC or
GND
0
6
-
-
8
-
80
-
160
µA
Three-State Leakage
Current
IOZ
VIL or VIH
VO =
VCC or
GND
6
-
-
±0.5
-
±5
-
±10
µA
High Level Input
Voltage
VIH
-
-
4.5 to
5.5
2
-
-
2
-
2
-
V
Low Level Input
Voltage
VIL
-
-
4.5 to
5.5
-
-
0.8
-
0.8
-
0.8
V
High Level Output
Voltage
CMOS Loads
VOH
VIH or VIL
-0.02
4.5
4.4
-
-
4.4
-
4.4
-
V
-6
4.5
3.98
-
-
3.84
-
3.7
-
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
6
4.5
-
-
0.26
-
0.33
-
0.4
V
PARAMETER
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
HCT TYPES
High Level Output
Voltage
TTL Loads
Low Level Output
Voltage
CMOS Loads
VOL
VIH or VIL
Low Level Output
Voltage
TTL Loads
II
VCC and
GND
0
5.5
-
-
±0.1
-
±1
-
±1
µA
Quiescent Device
Current
ICC
VCC or
GND
0
5.5
-
-
8
-
80
-
160
µA
Three-State Leakage
Current
IOZ
VIL or VIH
VO =
VCC or
GND
5.5
-
-
±0.5
-
±5
-
±10
µA
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
∆ICC
(Note 2)
VCC
-2.1
-
4.5 to
5.5
-
100
360
-
450
-
490
µA
Input Leakage
Current
NOTE:
2. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.
HCT Input Loading Table
INPUT
UNIT LOADS
DIR
0.9
OE, A
1.5
B
1.5
NOTE: Unit Load is ∆ICC limit specified in DC Electrical Table, e.g.,
360µA max at 25oC.
4
CD54HC640, CD74HC640, CD54HCT640, CD74HCT640
Switching Specifications
PARAMETER
CL = 50pF, Input tr, tf = 6ns
SYMBOL
TEST
CONDITIONS
tPHL, tPLH
CL = 50pF
-40oC TO
85oC
25oC
-55oC TO
125oC
VCC (V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
2
-
-
90
-
115
-
135
ns
4.5
-
-
18
-
23
-
27
ns
CL = 15pF
5
-
7
-
-
-
-
-
ns
CL = 50pF
6
-
-
15
-
20
-
23
ns
CL = 50pF
2
-
-
150
-
190
-
225
ns
4.5
-
-
30
-
38
-
45
ns
CL = 15pF
5
-
12
-
-
-
-
-
ns
CL = 50pF
6
-
-
26
-
33
-
38
ns
CL = 50pF
2
-
-
150
-
190
-
225
ns
4.5
-
-
30
-
38
-
45
ns
CL = 15pF
5
-
12
-
-
-
-
-
ns
CL = 50pF
6
-
-
26
-
33
-
38
ns
CL = 50pF
2
-
-
60
-
75
-
90
ns
4.5
-
-
12
-
15
-
18
ns
6
-
-
10
-
13
-
15
ns
HC TYPES
Propagation Delay
A to B
B to A
Output High-Z
To High Level,
To Low Level
Output High Level
Output Low Level to High Z
Output Transition Time
tPHL, tPLH
tPHZ, tPLZ
tTHL, tTLH
Input Capacitance
CIN
CL = 50pF
-
10
-
10
-
10
-
10
pF
Three-State Output
Capacitance
CO
-
-
-
-
20
-
20
-
20
pF
Power Dissipation Capacitance
(Notes 3, 4)
CPD
-
5
-
38
-
-
-
-
-
pF
A to B
B to A
tPHL, tPLH
CL = 50pF
4.5
-
-
22
-
28
-
33
ns
CL = 15pF
5
-
9
-
-
-
-
-
ns
Output High-Z
To High Level,
To Low Level
tPHL, tPLH
CL = 50pF
4.5
-
-
30
-
38
-
45
ns
CL = 15pF
5
-
12
-
-
-
-
-
ns
Output High Level
Output Low Level to High Z
tPHZ, tPLZ
CL = 50pF
4.5
-
-
30
-
38
-
45
ns
CL = 15pF
5
-
12
-
-
-
-
-
ns
tTHL, tTLH
CL = 50pF
4.5
-
-
12
-
15
-
18
ns
Input Capacitance
CIN
CL = 50pF
-
10
-
10
-
10
-
10
pF
Three-State Output
Capacitance
CO
-
-
-
-
20
-
20
-
20
pF
Power Dissipation Capacitance
(Notes 3, 4)
CPD
-
5
-
41
-
-
-
-
-
pF
HCT TYPES
Propagation Delay
Output Transition Time
NOTES:
3. CPD is used to determine the dynamic power consumption, per channel.
4. PD = VCC2 fi (CPD + CL) where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.
5
CD54HC640, CD74HC640, CD54HCT640, CD74HCT640
Test Circuits and Waveforms
tr = 6ns
tf = 6ns
90%
50%
10%
INPUT
GND
tTLH
tPHL
6ns
10%
2.7
1.3
OUTPUT LOW
TO OFF
90%
OUTPUT HIGH
TO OFF
50%
OUTPUTS
DISABLED
FIGURE 9. HC THREE-STATE PROPAGATION DELAY
WAVEFORM
OTHER
INPUTS
TIED HIGH
OR LOW
OUTPUT
DISABLE
IC WITH
THREESTATE
OUTPUT
GND
1.3V
tPZH
90%
OUTPUTS
ENABLED
OUTPUTS
ENABLED
0.3
10%
tPHZ
tPZH
3V
tPZL
tPLZ
50%
OUTPUTS
ENABLED
6ns
GND
10%
tPHZ
tf
OUTPUT
DISABLE
tPZL
tPLZ
OUTPUT HIGH
TO OFF
6ns
tr
VCC
90%
tPLH
FIGURE 8. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
6ns
OUTPUT LOW
TO OFF
1.3V
10%
INVERTING
OUTPUT
FIGURE 7. HC TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
50%
tTLH
90%
tPLH
tPHL
GND
tTHL
90%
50%
10%
INVERTING
OUTPUT
3V
2.7V
1.3V
0.3V
INPUT
tTHL
OUTPUT
DISABLE
tf = 6ns
tr = 6ns
VCC
1.3V
OUTPUTS
DISABLED
OUTPUTS
ENABLED
FIGURE 10. HCT THREE-STATE PROPAGATION DELAY
WAVEFORM
OUTPUT
RL = 1kΩ
CL
50pF
VCC FOR tPLZ AND tPZL
GND FOR tPHZ AND tPZH
NOTE: Open drain waveforms tPLZ and tPZL are the same as those for three-state shown on the left. The test circuit is Output RL = 1kΩ to
VCC, CL = 50pF.
FIGURE 11. HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT
6
PACKAGE OPTION ADDENDUM
www.ti.com
30-Mar-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
5962-8974001RA
ACTIVE
CDIP
J
20
1
TBD
Call TI
Level-NC-NC-NC
CD54HC640F3A
ACTIVE
CDIP
J
20
1
TBD
Call TI
Level-NC-NC-NC
CD54HCT640F3A
ACTIVE
CDIP
J
20
1
TBD
Call TI
Level-NC-NC-NC
CD74HC640E
ACTIVE
PDIP
N
20
20
Pb-Free
(RoHS)
CU NIPDAU
Level-NC-NC-NC
CD74HC640M
ACTIVE
SOIC
DW
20
25
Pb-Free
(RoHS)
CU NIPDAU
Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
CD74HCT640E
ACTIVE
PDIP
N
20
20
Pb-Free
(RoHS)
CU NIPDAU
Level-NC-NC-NC
CD74HCT640M
ACTIVE
SOIC
DW
20
25
Pb-Free
(RoHS)
CU NIPDAU
Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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