TI1 CD74FCT653EN Bicmos octal registered transceiver with 3-state output Datasheet

CD74FCT543
BiCMOS OCTAL REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS
SCBS742 – JULY 2000
D
D
D
D
D
D
D
D
D
EN, M, OR SM PACKAGE
(TOP VIEW)
BiCMOS Technology With Low Quiescent
Power
Buffered Inputs
Inverted Outputs
Input/Output Isolation From VCC
Controlled Output Edge Rates
64-mA Output Sink Current
Output Voltage Swing Limited to 3.7 V
SCR Latch-Up-Resistant BiCMOS Process
and Circuit Design
Package Options Include Plastic
Small-Outline (M) and Shrink Small-Outline
(SM) Packages and Standard Plastic (EN)
DIP
LEBA
OEBA
A1
A2
A3
A4
A5
A6
A7
A8
CEAB
GND
1
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
11
14
12
13
VCC
CEBA
B1
B2
B3
B4
B5
B6
B7
B8
LEAB
OEAB
description
The CD74FCT543 is an octal register/transceiver with 3-state outputs that uses a small-geometry BiCMOS
technology. The output stage is a combination of bipolar and CMOS transistors that limits the output high level
to two diode drops below VCC. This resultant lowering of output swing (0 V to 3.7 V) reduces power-bus ringing
[a source of electromagnetic interference (EMI)] and minimizes VCC bounce and ground bounce and their
effects during simultaneous output switching. The output configuration also enhances switching speed and is
capable of sinking 64 mA.
This device contains two sets of eight D-type latches with separate input and output controls for each set. For
data flow from A to B, for example, the A-to-B enable (CEAB) input must be low to enter data from A1 to A8 or
to take data from B1 to B8. When CEAB is low, a low signal on the A-to-B latch enable (LEAB) input makes the
A-to-B latches transparent; a subsequent low-to-high transition of the LEAB signal puts the A latches in the
storage mode and their outputs no longer change with the A inputs. With CEAB and OEAB both low, the B output
buffers are active and reflect the data present at the output of the A latches. Control of data from B to A is similar,
but uses the CEBA, LEBA, and OEBA inputs.
The CD74FCT543 contains two sets of D-type latches for temporary storage of data flowing in either direction.
Separate latch-enable (LEAB or LEBA) and output-enable (OEAB or OEBA) inputs are provided for each
register to permit independent control in either direction of data flow.
The A-to-B enable (CEAB) input must be low to enter data from A or to output data from B. If CEAB is low and
LEAB is low, the A-to-B latches are transparent; a subsequent low-to-high transition of LEAB puts the A latches
in the storage mode. With CEAB and OEAB both low, the 3-state B outputs are active and reflect the data present
at the output of the A latches. Data flow from B to A is similar but requires using the CEBA, LEBA, and OEBA
inputs.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The CD74FCT543 is characterized for operation from 0°C to 70°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
CD74FCT543
BiCMOS OCTAL REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS
SCBS742 – JULY 2000
FUNCTION TABLE†
INPUTS
OEAB
A
LATCH
STATUS
OUTPUT
B
X
X
X
Storing
Z
X
H
X
–
Z
L
H
L
X
Storing
L
L
L
L
Transparent
B0‡
L
L
L
L
H
CEAB
LEAB
H
X
Transparent
H
† A-to-B data flow is shown; B-to-A flow control is the same except that
it uses CEBA, LEBA, and OEBA.
‡ Output level before the indicated steady-state input conditions were
established
logic symbol§
2
1EN3
OEBA
23
CEBA
1
1C5
LEBA
13
OEAB
11
CEAB
14
LEAB
A1
A2
A3
A4
A5
A6
A7
A8
G1
2EN4
G2
2C6
3
4
3
1
5D
6D
1
4
21
5
20
6
19
7
18
8
17
9
16
10
15
§ This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
2
22
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B1
B2
B3
B4
B5
B6
B7
B8
CD74FCT543
BiCMOS OCTAL REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS
SCBS742 – JULY 2000
logic diagram (positive logic)
OEBA
CEBA
LEBA
OEAB
CEAB
LEAB
A1
2
23
1
13
11
14
C1
3
1D
22
B1
C1
1D
To Seven Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
DC supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6 V
DC input clamp current, IIK (VI < –0.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20 mA
DC output clamp current, IOK (VO < –0.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
DC output sink current per output pin, IOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 mA
DC output source current per output pin, IOH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –30 mA
Continuous current through VCC, ICC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 mA
Continuous current through GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528 mA
Package thermal impedance, θJA (see Note 1): EN package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
M package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46°C/W
SM package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The package thermal impedance is calculated in accordance with JESD 51.
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3
CD74FCT543
BiCMOS OCTAL REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS
SCBS742 – JULY 2000
recommended operating conditions (see Note 2)
MIN
MAX
UNIT
4.75
5.25
V
VCC
VIH
Supply voltage
VIL
VI
Low-level input voltage
Input voltage
0
VO
IOH
Output voltage
0
IOL
∆t/∆v
Low-level output current
High-level input voltage
2
High-level output current
Input transition rise or fall rate
0
V
0.8
V
VCC
VCC
V
–15
mA
V
64
mA
10
ns/V
TA
Operating free-air temperature
0
70
°C
NOTE 2: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25°C
MIN
MAX
MIN
UNIT
–1.2
V
VIK
VOH
II = –18 mA
IOH = –15 mA
4.75 V
VOL
II
IOL = 64 mA
VI = VCC or GND
4.75 V
0.55
0.55
V
5.25 V
±0.1
±1
mA
IOZ
IOS†
VO = VCC or GND
VI = VCC or GND,
ICC
VI = VCC or GND,
One input at 3.4 V,
Other inputs at VCC or GND
∆ICC‡
Ci
Co
4.75 V
–1.2
MAX
2.4
±0.5
5.25 V
VO = 0
IO = 0
5.25 V
2.4
V
±10
–60
–60
mA
mA
5.25 V
8
80
mA
5.25 V
1.6
1.6
mA
10
10
pF
15
15
pF
VI = VCC or GND
VO = VCC or GND
† Not more than one output should be tested at a time, and the duration of the test should not exceed 100 ms.
‡ This is the increase in supply current for each input at one of the specified TTL voltage levels rather than 0 V or VCC.
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
MIN
tw
Pulse duration
LEAB or LEBA low
A or B before LEAB or LEBA↑
tsu
Setup time
A or B before CEAB or CEBA↑
th
4
Hold time
9
Data high
3
Data low
3
Data high
3
Data low
3
A or B after LEAB or LEBA↑
2
A or B after CEAB or CEBA↑
2
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MAX
UNIT
ns
ns
ns
CD74FCT543
BiCMOS OCTAL REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS
SCBS742 – JULY 2000
switching characteristics over recommended operating conditions (unless otherwise noted) (see
Figure 1)
PARAMETER
tpd
d
ten
tdis
FROM
(INPUT)
TO
(OUTPUT)
TA = 25°C
TYP
MIN
MAX
UNIT
A or B
B or A
6.4
2.5
8.5
LEBA or LEAB
A or B
9.4
2.5
12.5
LEBA or LEAB
A or B
9
2
12
ns
A or B
6.8
2
9
ns
TYP
MAX
LEBA or LEAB
ns
noise characteristics, VCC = 5 V, CL = 50 pF, TA = 25°C
PARAMETER
VOL(P)
VOH(V)
Quiet output, maximum dynamic VOL
VIH(D)
VIL(D)
High-level dynamic input voltage
MIN
Quiet output, minimum dynamic VOH
UNIT
1
V
0.5
V
2
Low-level dynamic input voltage
V
0.8
V
TYP
UNIT
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER
Cpd
TEST CONDITIONS
Power dissipation capacitance
No load,
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f = 1 MHz
49
pF
5
CD74FCT543
BiCMOS OCTAL REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS
SCBS742 – JULY 2000
PARAMETER MEASUREMENT INFORMATION
7V
CL = 50 pF
(see Note A)
500 Ω
From Output
Under Test
Test
Point
From Output
Under Test
Open
TEST
GND
CL = 50 pF
(see Note A)
500 Ω
S1
S1
Open
7V
Open
7V
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
500 Ω
Open Drain
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
90%
1.5 V
10%
3V
1.5 V
10% 0 V
90%
tr
tf
VOLTAGE WAVEFORM
INPUT RISE AND FALL TIMES
3V
1.5 V
Timing Input
0V
tw
tsu
3V
1.5 V
1.5 V
Input
th
3V
1.5 V
Data Input
1.5 V
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3V
1.5 V
1.5 V
Input
0V
tPLH
tPHL
1.5 V
1.5 V
VOL
tPHL
Out-of-Phase
Output
tPLZ
≈3.5 V
1.5 V
tPZH
VOH
1.5 V
VOL
1.5 V
0V
Output
Waveform 1
(see Note B)
tPLH
1.5 V
1.5 V
tPZL
VOH
In-Phase
Output
3V
Output
Control
Output
Waveform 2
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOL + 0.3 V
VOL
tPHZ
1.5 V
V
VOH – 0.3 V OH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr and tf = 2.5 ns.
D. The outputs are measured one at a time with one input transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPHL and tPLH are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
6
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PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
CD74FCT543EN
OBSOLETE
PDIP
NT
24
TBD
Call TI
Call TI
0 to 70
CD74FCT543M
OBSOLETE
SOIC
DW
24
TBD
Call TI
Call TI
0 to 70
CD74FCT543M96
OBSOLETE
SOIC
DW
24
TBD
Call TI
Call TI
0 to 70
CD74FCT543SM
OBSOLETE
SSOP
DB
24
TBD
Call TI
Call TI
0 to 70
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
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