[ /Title (CD74 HC431 6, CD74 HCT43 16) /Subject (HighSpeed CMOS CD54HC4316, CD74HC4316, CD74HCT4316 Data sheet acquired from Harris Semiconductor SCHS212D High-Speed CMOS Logic Quad Analog Switch with Level Translation February 1998 - Revised October 2003 Features In addition these devices contain logic-level translation circuits that provide for analog signal switching of voltages between ±5V via 5V logic. Each switch is turned on by a high-level voltage on its select input (S) when the common Enable (E) is Low. A High E disables all switches. The digital inputs can swing between VCC and GND; the analog inputs/outputs can swing between VCC as a positive limit and VEE as a negative limit. Voltage ranges are shown in Figures 2 and 3. • Wide Analog-Input-Voltage Range VCC - VEE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 10V • Low “ON” Resistance - 45Ω (Typ) . . . . . . . . . . . . . . . . . . . . . . . . . . .VCC = 4.5V - 35Ω (Typ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC = 6V - 30Ω (Typ) . . . . . . . . . . . . . . . . . . . . . . . VCC - VEE = 9V • Fast Switching and Propagation Delay Times Ordering Information • Low “OFF” Leakage Current • Built-In “Break-Before-Make” Switching PART NUMBER • Logic-Level Translation to Enable 5V Logic to Accommodate ±5V Analog Signals TEMP. RANGE (oC) PACKAGE CD54HC4316F3A -55 to 125 16 Ld CERDIP CD74HC4316E -55 to 125 16 Ld PDIP CD74HC4316M -55 to 125 16 Ld SOIC • HC Types - 2V to 10V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V CD74HC4316MT -55 to 125 16 Ld SOIC CD74HC4316M96 -55 to 125 16 Ld SOIC CD74HC4316NSR -55 to 125 16 Ld SOP • HCT Types - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH CD74HC4316PW -55 to 125 16 Ld TSSOP CD74HC4316PWR -55 to 125 16 Ld TSSOP CD74HC4316PWT -55 to 125 16 Ld TSSOP CD74HCT4316E -55 to 125 16 Ld PDIP Description CD74HCT4316M -55 to 125 16 Ld SOIC CD74HCT4316MT -55 to 125 16 Ld SOIC CD74HCT4316M96 -55 to 125 16 Ld SOIC • Wide Operating Temperature Range . . . -55oC to 125oC The ’HC4316 and CD74HCT4316 contain four independent digitally controlled analog switches that use silicon-gate CMOS technology to achieve operating speeds similar to LSTTL with the low power consumption of standard CMOS integrated circuits. Pinout NOTE: When ordering, use the entire part number. The suffixes 96 and R denote tape and reel. The suffix T denotes a small-quantity reel of 250. CD54HC4316 (CERDIP) CD74HC4316 (PDIP, SOIC, SOP, TSSOP) CD74HCT4316 (PDIP, SOIC) TOP VIEW 1Z 1 16 VCC 1Y 2 15 1S 2Y 3 14 4S 2Z 4 13 4Z 2S 5 12 4Y 3S 6 11 3Y E 7 10 3Z 9 VEE GND 8 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, Texas Instruments Incorporated 1 CD54HC4316, CD74HC4316, CD74HCT4316 Functional Diagram VCC 16 2 15 1Y 1S 1 5 1Z 3 2S LOGIC LEVEL CONV. AND CONTROL 6 3S 2Y 4 2Z 11 3Y 14 4S 10 12 E 7 3Z 4Y 13 4Z 8 9 GND VEE TRUTH TABLE INPUTS E S SWITCH L L OFF L H ON H X OFF H= High Level Voltage L= Low Level Voltage X= Don’t Care Logic Diagram nY TO 3 OTHER SWITCHES E nS VCC VCC LOGIC LEVEL CONV. nZ VEE VEE FIGURE 1. ONE SWITCH 2 CD54HC4316, CD74HC4316, CD74HCT4316 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Supply Voltage, VCC - VEE . . . . . . . . . . . . . . . . . . -0.5V to 10.5V DC Supply Voltage, VEE . . . . . . . . . . . . . . . . . . . . . . . . 0.5V to -7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC 0.5V. . . . . . . . . . . . . . . . . . . . . . . .±20mA DC Switch Diode Current, IOK For VI < VEE -0.5V or VI < VCC + 0.5V . . . . . . . . . . . . . . . . .±25mA DC Switch Diode Current For VI > VEE -0.5V or VI < VCC + 0.5V . . . . . . . . . . . . . . . . .±25mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA Package Thermal Impedance, θJA (see Note 1): E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67oC/W M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73oC/W NS (SOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64oC/W PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . 108oC/W Maximum Junction Temperature (Plastic Package) . . . . . . . . . 150o Maximum Storage Temperature Range . . . . . . . . . . . -65oC to 150o Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . 300o SOIC - Lead Tips Only Operating Conditions Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V Supply Voltage Range, VCC - VEE HC, HCT Types (Figure 2) . . . . . . . . . . . . . . . . . . . . . . .2V to 10V Supply Voltage Range, VEE HC, HCT Types (Figure 3) . . . . . . . . . . . . . . . . . . . . . . . 0V to -6V DC Input or Output Voltage, VI . . . . . . . . . . . . . . . . . . . GND to VCC Analog Switch I/O Voltage, VIS . . . . . . . . . . . . . . . . . . . . . VEE (Min) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC (Max) Input Rise and Fall Time, tr, tf 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. The package thermal impedance is calculated in accordance with JESD 51-7. Recommended Operating Area as a Function of Supply Voltage 8 8 6 VCC - GND (V) 4 6 VCC - GND (V) 4 HCT HC 2 0 HCT HC 2 0 2 0 4 6 8 10 12 VCC - VEE (V) FIGURE 2. 0 -2 -4 -6 -8 VEE - GND (V) FIGURE 3. 3 CD54HC4316, CD74HC4316, CD74HCT4316 DC Electrical Specifications TEST CONDITIONS PARAMETER SYMBOL VI (V) VIS (V) VIH - - -40oC TO 85oC 25oC VEE (V) VCC (V) -55oC TO 125oC MIN TYP MAX MIN MAX MIN MAX UNITS 2 1.5 - - 1.5 - 1.5 - V 4.5 3.15 - - 3.15 - 3.15 - V 6 4.2 - - 4.2 - 4.2 - V 2 - - 0.5 - 0.5 - 0.5 V 4.5 - - 1.35 - 1.35 - 1.35 V 6 - - 1.8 - 1.8 - 1.8 V 0 4.5 - 45 180 - 225 - 270 Ω 0 6 - 35 160 - 200 - 240 Ω -4.5 4.5 - 30 135 - 170 - 205 Ω 0 4.5 - 85 320 - 400 - 480 Ω 0 6 - 55 240 - 300 - 360 Ω -4.5 4.5 - 35 170 - 215 - 255 Ω 0 4.5 - 10 - - - - - Ω 0 6 - 8.5 - - - - - Ω -4.5 4.5 - 5 - - - - - Ω 0 6 - - ±0.1 - ±1 - ±1 µA -5 5 - - ±0.1 - ±1 - ±1 µA HC TYPES High Level Input Voltage Low Level Input Voltage “ON” Resistance IO = 1mA (Figures 4, 5) VIL RON - VIH or VIL - VCC or VEE VCC to VEE Maximum “ON” Resistance Between Any Two Channels ∆RON Switch Off Leakage Current IIZ Control Input Leakage Current Quiescent Device Current IO = 0 - - - - VIH or VIL VCC VEE IIL VCC or GND - 0 6 - - ±0.1 - ±1 - ±1 µA ICC VCC or When 0 GND VIS = VEE, VOS=VCC -5 6 - - 8 - 80 - 160 µA 5 - - 16 - 160 - 320 µA When VIS = VCC, VOS =VEE HCT TYPES High Level Input Voltage VIH - - - 4.5 to 5.5 2 - - 2 - 2 - V Low Level Input Voltage VIL - - - 4.5 to 5.5 - - 0.8 - 0.8 - 0.8 V “ON” Resistance IO = 1mA (Figures 4, 5) RON VIH or VIL VCC or VEE 0 4.5 - 45 180 - 225 - 270 Ω -4.5 4.5 - 30 135 - 170 - 205 Ω 0 4.5 - 85 320 - 400 - 480 Ω -4.5 4.5 - 35 170 - 215 - 255 Ω 0 4.5 - 10 - - - - - Ω -4.5 4.5 - 5 - - - - - Ω 0 6 - - ±0.1 - ±1 - ±1 µA -5 5 - - ±0.1 - ±1 - ±1 µA VCC to VEE Maximum “ON” Resistance Between Any Two Channels ∆RON Switch Off Leakage Current IIZ - VIH or VIL - VCC VEE 4 CD54HC4316, CD74HC4316, CD74HCT4316 DC Electrical Specifications (Continued) PARAMETER SYMBOL VI (V) VIS (V) Control Input Leakage Current II VCC or GND - Quiescent Device Current IO = 0 Additional Quiescent Device Current Per Input Pin: 1 Unit Load ICC ∆ICC (Note 2) Any When Voltage VIS = VEE, BeVOS = tween VCC, VCC and When GND VIS = VCC, VOS = VEE VCC -2.1 -40oC TO 85oC 25oC TEST CONDITIONS VEE (V) VCC (V) -55oC TO 125oC MIN TYP MAX MIN MAX MIN MAX UNITS 0 5.5 - - ±0.1 - ±1 - ±1 µA 0 5.5 - - 8 - 80 - 160 µA -4.5 5.5 - - 16 - 160 - 320 µA - 4.5 to 5.5 - 100 360 - 450 - 490 µA - NOTE: 2. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. HCT Input Loading Table INPUT UNIT LOADS All 0.5 NOTE: Unit Load is ∆ICC limit specified in DC Electrical Table, e.g., 360µA max at 25oC. Switching Specifications Input tr, tf = 6ns PARAMETER -40oC TO 85oC 25oC -55oC TO 125oC SYMBOL TEST CONDITIONS VEE (V) VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS tPLH, tPHL CL = 50pF 0 2 - - 60 - 75 - 90 ns 0 4.5 - - 12 - 15 - 18 ns 0 6 - - 10 - 13 - 15 ns -4.5 4.5 - - 8 - 10 - 12 ns 0 2 - - 205 - 255 - 310 ns 0 4.5 - - 41 - 51 - 62 ns 0 6 - - 35 - 43 - 53 ns HC TYPES Propagation Delay, Switch In to Out Turn “ON” Time E to Out Turn “ON” Time nS to Out Turn “OFF” Time E to Out tPZH, tPZL tPZH, tPZL tPLZ, tPHZ CL = 50pF -4.5 4.5 - - 37 - 47 - 56 ns CL = 15pF - 5 - 17 - - - - - ns CL = 50pF 0 2 - - 175 - 220 - 265 ns 0 4.5 - - 35 - 44 - 53 ns 0 6 - - 30 - 37 - 45 ns -4.5 4.5 - - 34 - 43 - 51 ns CL = 15pF - 5 - 14 - - - - - ns CL = 50pF 0 2 - - 205 - 255 - 310 ns 0 4.5 - - 41 - 51 - 62 ns 0 6 - - 35 - 43 - 53 ns -4.5 4.5 - - 37 - 47 - 56 ns - 5 - 17 - - - - - ns CL = 15pF 5 CD54HC4316, CD74HC4316, CD74HCT4316 Switching Specifications Input tr, tf = 6ns PARAMETER Turn “OFF” Time nS to Out Input (Control) Capacitance Power Dissipation Capacitance (Notes 3, 4) (Continued) -40oC TO 85oC 25oC -55oC TO 125oC VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS 0 2 - - 175 - 220 - 265 ns 0 4.5 - - 35 - 44 - 53 ns SYMBOL TEST CONDITIONS VEE (V) tPLZ, tPHZ CL = 50pF 0 6 - - 30 - 37 - 45 ns -4.5 4.5 - - 34 - 43 - 51 ns CL = 15pF - 5 - 14 - - - - - ns CI - - - - - 10 - 10 - 10 pF CPD - - 5 - 42 - - - - - pF tPLH, tPHL CL = 50pF 0 4.5 - - 12 - 15 - 18 ns -4.5 4.5 - - 8 - 10 - 12 ns tPZH CL = 50pF 0 4.5 - - 44 - 55 - 66 ns -4.5 4.5 - - 42 - 53 - 63 ns - 5 - 18 - - - - - ns HCT TYPES Propagation Delay, Switch In to Switch Out Turn “ON” Time E to Out CL = 15pF tPZL Turn “ON” Time nS to Out tPZH CL = 50pF Turn “OFF” Time E to Out Turn “OFF” Time nS to Out Input (Control) Capacitance Power Dissipation Capacitance (Notes 3, 4) 4.5 - - 56 - 70 - 85 ns 4.5 - - 42 - 53 - 63 ns CL = 15pF - 5 - 24 - - - - - ns CL = 50pF 0 4.5 - - 40 - 53 - 60 ns -4.5 4.5 - - 34 - 43 - 51 ns - 5 - 17 - - - - - ns CL = 15pF tPZL 0 -4.5 CL = 50pF 0 4.5 - - 50 - 63 - 75 ns -4.5 4.5 - - 34 - 43 - 51 ns CL = 15pF - 5 - 18 - - - - - ns tPLZ CL = 50pF 0 4.5 - - 50 - 63 - 75 ns -4.5 4.5 - - 46 - 58 - 69 ns tPLZ, tPHZ CL = 15pF - 5 - 21 - - - - - ns tPHZ CL = 50pF 0 4.5 - - 44 - 55 - 66 ns -4.5 4.5 - - 40 - 50 - 60 ns tPLZ, tPHZ CL = 15pF - 5 - 18 - - - - - ns CI - - - - - 10 - 10 - 10 pF CPD - - 5 - 47 - - - - - pF NOTES: 3. CPD is used to determine the dynamic power consumption, per package. 4. PD = CPD VCC2 fi + Σ (CL + CS) VCC2 fo where fi = input frequency, fo = output frequency, CL = output load capacitance, CS = switch capacitance, VCC = supply voltage. Analog Channel Specifications TA = 25oC TEST CONDITIONS VCC (V) HC4316 CD74HCT4316 UNITS Figure 9 (Notes 5, 6) 4.5 >200 >200 MHz Crosstalk Between Any Two Switches (Figure 7) Figure 8 (Notes 6, 7) 4.5 TBE TBE dB PARAMETER Switch Frequency Response Bandwidth at -3dB (Figure 6) 6 CD54HC4316, CD74HC4316, CD74HCT4316 Analog Channel Specifications TA = 25oC (Continued) TEST CONDITIONS VCC (V) HC4316 CD74HCT4316 UNITS 1kHz, VIS = 4VP-P (Figure 10) 4.5 0.078 0.078 % 1kHz, VIS = 8VP-P (Figure 10) 9 0.018 0.018 % 4.5 TBE TBE mV 9 TBE TBE mV Figure 12 (Notes 6, 7) 4.5 -62 -62 dB - - 5 5 pF PARAMETER Total Harmonic Distortion Control to Switch Feedthrough Noise Switch “OFF” Signal Feedthrough (Figure 7) Figure 11 Switch Input Capacitance, CS NOTES: 5. Adjust input level for 0dBm at output, f = 1MHz. 6. VIS is centered at VCC/2. 7. Adjust input for 0dBm at VIS. Typical Performance Curves 110 60 “ON” RESISTANCE, RON (Ω) “ON” RESISTANCE, RON (Ω) 100 90 VCC = 4.5V, VEE = 0V 80 70 60 50 40 VCC = 6V, VEE = 0V 30 20 50 45 40 30 25 20 15 10 5 10 0 1 2 3 4 4.5 INPUT SIGNAL VOLTAGE, VIS (V) 5 0 -4.5 6 CROSSTALK, dB SWITCH OFF SIGNAL FEEDTHROUGH, dB CL = 10pF -2 VCC = 4.5V RL = 50Ω TA = 25oC PIN 4 TO 3 -3 CL = 10pF VCC = 9V RL = 50Ω TA = 25oC PIN 4 TO 3 -4 10K 100K 1M 10M FREQUENCY (f), Hz -2.5 -1.5 -0.5 0.5 1.5 2.5 3.5 4.5 FIGURE 5. TYPICAL “ON” RESISTANCE vs INPUT SIGNAL VOLTAGE 0 -1 -3.5 INPUT SIGNAL VOLTAGE, VIS (V) FIGURE 4. TYPICAL “ON” RESISTANCE vs INPUT SIGNAL VOLTAGE CHANNEL ON BANDWIDTH, dB VCC = 4.5V, VEE = 4.5V 35 0 -40 FIGURE 6. SWITCH FREQUENCY RESPONSE CL = 10pF VCC = 9V RL = 50Ω TA = 25oC PIN 4 TO 3 -60 -80 -100 10K 100M CL = 10pF VCC = 4.5V RL = 50Ω TA = 25oC PIN 4 TO 3 -20 100K 1M 10M FREQUENCY (f), Hz 100M FIGURE 7. SWITCH-OFF SIGNAL FEEDTHROUGH AND CROSSTALK vs FREQUENCY 7 CD54HC4316, CD74HC4316, CD74HCT4316 Analog Test Circuits VIS VCC VCC 0.1µF SWITCH ON VIS VOS1 R R VOS2 SWITCH ON R C R VCC/2 C dB METER VCC/2 fIS = 1MHz SINEWAVE R = 50Ω C = 10pF VCC/2 FIGURE 8. CROSSTALK BETWEEN TWO SWITCHES TEST CIRCUIT VCC VCC 0.1µF VIS SINE WAVE 10µF VIS VOS SWITCH ON 50Ω VIS VI = VIH SWITCH ON VOS 10kΩ 10pF dB METER VCC/2 50pF DISTORTION METER VCC/2 fIS = 1kHz TO 10kHz FIGURE 9. FREQUENCY RESPONSE TEST CIRCUIT E VCC 600Ω VCC/2 SWITCH ALTERNATING ON AND OFF tr, tf ≤ 6ns fCONT = 1MHz 50% DUTY CYCLE FIGURE 10. TOTAL HARMONIC DISTORTION TEST CIRCUIT VCC VP-P VOS 0.1µF 600Ω 50pF VCC/2 SCOPE FIGURE 11. CONTROL-TO-SWITCH FEEDTHROUGH NOISE TEST CIRCUIT fIS ≥ 1MHz SINEWAVE R = 50Ω C = 10pF VOS SWITCH ON VIS VOS VC = VIL R R VCC/2 VCC/2 C dB METER FIGURE 12. SWITCH OFF SIGNAL FEEDTHROUGH 8 CD54HC4316, CD74HC4316, CD74HCT4316 Test Circuits and Waveforms 6ns 6ns 3V (HCT) 90% 50% tf = 6ns tPLH OUTPUT LOW TO OFF 90% 50% 10% 50% 50% SWITCH ON FIGURE 13. SWITCH PROPAGATION DELAY TIMES tPZH 90% OUTPUT HIGH TO OFF VEE SWITCH OUTPUT 50% 10% tPHZ tPHL GND tPZL tPLZ tr = 6ns SWITCH INPUT 10% E VCC VCC (HC) OUTPUTS DISABLED SWITCH OFF OUTPUTS ENABLED SWITCH ON FIGURE 14. SWITCH TURN-ON AND TURN-OFF PROPAGATION DELAY TIMES WAVEFORMS 9 10 PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2014 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) CD54HC4316F3A ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 CD54HC4316F3A CD74HC4316E ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -55 to 125 CD74HC4316E CD74HC4316EE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -55 to 125 CD74HC4316E CD74HC4316M ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4316M CD74HC4316M96 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4316M CD74HC4316M96G4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4316M CD74HC4316ME4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4316M CD74HC4316MG4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4316M CD74HC4316MT ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4316M CD74HC4316NSR ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4316M CD74HC4316PW ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ4316 CD74HC4316PWR ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ4316 CD74HC4316PWRE4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ4316 CD74HC4316PWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ4316 CD74HCT4316E ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -55 to 125 CD74HCT4316E CD74HCT4316M ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4316M CD74HCT4316M96 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4316M Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 24-Aug-2014 Status (1) CD74HCT4316M96G4 ACTIVE Package Type Package Pins Package Drawing Qty SOIC D 16 2500 Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Op Temp (°C) Device Marking (4/5) -55 to 125 HCT4316M (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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OTHER QUALIFIED VERSIONS OF CD54HC4316, CD74HC4316 : Addendum-Page 2 Samples PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2014 • Catalog: CD74HC4316 • Military: CD54HC4316 NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product • Military - QML certified for Military and Defense Applications Addendum-Page 3 PACKAGE MATERIALS INFORMATION www.ti.com 18-Aug-2014 TAPE AND REEL INFORMATION *All dimensions are nominal Device CD74HC4316M96 Package Package Pins Type Drawing SOIC SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 CD74HC4316NSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 CD74HC4316PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 CD74HCT4316M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 18-Aug-2014 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CD74HC4316M96 SOIC D 16 2500 333.2 345.9 28.6 CD74HC4316NSR SO NS 16 2000 367.0 367.0 38.0 CD74HC4316PWR TSSOP PW 16 2000 367.0 367.0 35.0 CD74HCT4316M96 SOIC D 16 2500 333.2 345.9 28.6 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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