TI CD74HCT193M High speed cmos logic presettable synchronous 4-bit up/down counter Datasheet

[ /Title
(CD74
HC192
,
CD74
HC193
,
CD74
HCT19
3)
/Subject
(High
Speed
CMOS
Logic
Preset-
CD74HC192, CD74HC193,
CD74HCT193
Data sheet acquired from Harris Semiconductor
SCHS163
September 1997
High Speed CMOS Logic
Presettable Synchronous 4-Bit Up/Down Counters
Features
Description
• Synchronous Counting and Asynchronous
Loading
The Harris CD74HC192, CD74HC193 and CD74HCT193 are
asynchronously presettable BCD Decade and Binary
Up/Down synchronous counters, respectively.
• Two Outputs for N-Bit Cascading
Presetting the counter to the number on the preset data inputs
(P0-P3) is accomplished by a LOW asynchronous parallel
load input (PL). The counter is incremented on the low-to-high
transition of the Clock-Up input (and a high level on the ClockDown input) and decremented on the low to high transition of
the Clock-Down input (and a high level on the Clock-up input).
A high level on the MR input overrides any other input to clear
the counter to its zero state. The Terminal Count up (carry)
goes low half a clock period before the zero count is reached
and returns to a high level at the zero count. The Terminal
Count Down (borrow) in the count down mode likewise goes
low half a clock period before the maximum count (9 in the
192 and 15 in the 193) and returns to high at the maximum
count. Cascading is effected by connecting the carry and
borrow outputs of a less significant counter to the Clock-Up
and CLock-Down inputs, respectively, of the next most
significant counter.
• Look-Ahead Carry for High-Speed Counting
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH
If a decade counter is present to an illegal state or assumes
an illegal state when power is applied, it will return to the
normal sequence in one count as shown in state diagram.
Ordering Information
Pinout
PART NUMBER
CD74HC192, CD74HC193, CD74HCT193
(PDIP, SOIC)
TOP VIEW
TEMP. RANGE
(oC)
CD74HC192E
-55 to 125
16 Ld PDIP
E16.3
CD74HC193E
-55 to 125
16 Ld PDIP
E16.3
P1 1
16 VCC
Q1 2
15 P0
CD74HCT193E
-55 to 125
16 Ld PDIP
E16.3
Q0 3
14 MR
CD74HCT193M
-55 to 125
16 Ld SOIC
M16.15
CPD 4
13 TCD
CPU 5
12 TCU
Q2 6
11 PL
Q3 7
10 P2
GND 8
9 P3
NOTES:
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
2. Wafer or die for this part number is available which meets all electrical specifications. Please contact your local sales office or
Harris customer service for ordering information.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
PKG.
NO.
PACKAGE
© Harris Corporation 1997
1
File Number
1674.1
CD74HC192, CD74HC193, CD74HCT193
Functional Diagram
BCD/BINARY
PRESET
P0
15
ASYN.
PARALLEL
LOAD
ENABLE
PL
P1
1
P2
10
P3
9
3
11
Q0
2
MASTER 14
RESET
CLOCK UP
CLOCK DOWN
Q1
6
Q2
7
5
BCD (192)
BINARY (193)
OUTPUTS
Q3
12 TERMINAL
COUNT UP
13
TERMINAL
COUNT DOWN
4
TRUTH TABLE
CLOCK UP
CLOCK
DOWN
RESET
PARALLEL
LOAD
↑
H
L
H
Count Up
H
↑
L
H
Count Down
X
X
H
X
Reset
X
X
L
L
Load Preset Inputs
FUNCTION
NOTE: H = High Voltage Level, L = Low Voltage Level, X = Don’t Care, ↑ = Transition from
Low to High Level
2
CD74HC192, CD74HC193, CD74HCT193
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, IIK
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, ICC or IGND . . . . . . . . . . . . . . . . . .±50mA
Thermal Resistance (Typical, Note 3)
θJA (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
90
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
160
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
3. θJA is measured with the component mounted on an evaluation PC board in free air.
DC Electrical Specifications
TEST
CONDITIONS
PARAMETER
SYMBOL
VI (V)
VIH
-
25oC
IO (mA) VCC (V)
-40oC TO 85oC
-55oC TO 125oC
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
2
1.5
-
-
1.5
-
1.5
-
V
4.5
3.15
-
-
3.15
-
3.15
-
V
6
4.2
-
-
4.2
-
4.2
-
V
HC TYPES
High Level Input
Voltage
Low Level Input
Voltage
High Level Output
Voltage
CMOS Loads
VIL
VOH
-
VIH or
VIL
High Level Output
Voltage
TTL Loads
Low Level Output
Voltage
CMOS Loads
VOL
VIH or
VIL
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
Quiescent Device
Current
-
-
2
-
-
0.5
-
0.5
-
0.5
V
4.5
-
-
1.35
-
1.35
-
1.35
V
6
-
-
1.8
-
1.8
-
1.8
V
-0.02
2
1.9
-
-
1.9
-
1.9
-
V
-0.02
4.5
4.4
-
-
4.4
-
4.4
-
V
-0.02
6
5.9
-
-
5.9
-
5.9
-
V
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
-5.2
6
5.48
-
-
5.34
-
5.2
-
V
0.02
2
-
-
0.1
-
0.1
-
0.1
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
0.02
6
-
-
0.1
-
0.1
-
0.1
V
4
4.5
-
-
0.26
-
0.33
-
0.4
V
5.2
6
-
-
0.26
-
0.33
-
0.4
V
II
VCC or
GND
-
6
-
-
±0.1
-
±1
-
±1
µA
ICC
VCC or
GND
0
6
-
-
8
-
80
-
160
µA
3
CD74HC192, CD74HC193, CD74HCT193
DC Electrical Specifications
(Continued)
TEST
CONDITIONS
SYMBOL
VI (V)
High Level Input
Voltage
VIH
-
-
Low Level Input
Voltage
VIL
-
High Level Output
Voltage
CMOS Loads
VOH
VIH or
VIL
PARAMETER
25oC
IO (mA) VCC (V)
-40oC TO 85oC
-55oC TO 125oC
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
4.5 to
5.5
2
-
-
2
-
2
-
V
-
4.5 to
5.5
-
-
0.8
-
0.8
-
0.8
V
-
4.5
4.4
-
-
4.4
-
4.4
-
V
-
4.5
3.98
-
-
3.84
-
3.7
-
V
-
4.5
-
-
0.1
-
0.1
-
0.1
V
-
4.5
-
-
0.26
-
0.33
-
0.4
V
HCT TYPES
High Level Output
Voltage
TTL Loads
Low Level Output
Voltage
CMOS Loads
VOL
VIH or
VIL
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
Quiescent Device
Current
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
(Note 4)
II
VCC to
GND
-
5.5
-
-
±0.1
-
±1
-
±1
µA
ICC
VCC or
GND
-
5.5
-
-
8
-
80
-
160
µA
∆ICC
VCC
-2.1
-
4.5 to
5.5
-
100
360
-
450
-
490
µA
NOTE:
4. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.
HCT Input Loading Table
INPUT
UNIT LOADS
P0-P3
0.4
MR
1.45
PL
0.85
CPU, CPD
1.45
NOTE: Unit Load is ∆ICC limit specified in DC Electrical
Specifications table, e.g. 360µA max at 25oC.
4
CD74HC192, CD74HC193, CD74HCT193
Prerequisite For Switching Specifications
PARAMETER
SYMBOL
HC TYPES
Pulse Width
tW
CPU, CPD
192
tW
CPU, CPD
193
PL
tW
MR
tW
Set-up Time
tSU
Pn to PL
Hold Time
tH
Pn to PL
Hold Time
tH
CPD to CPU or
CPU to CPD
Recovery Time
tREC
PL to CPU, CPD
MR to CPU, CPD
tREC
Maximum Frequency
fMAX
CPU, CPD
192
fMAX
CPU, CPD
193
HCT TYPES
Pulse Width
tW
CPU, CPD
192
CPU, CPD
tW
193
25oC
-40oC TO 85oC
-55oC TO 125oC
VCC
(V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
2
115
-
-
145
-
175
-
ns
4.5
23
-
-
29
-
35
-
ns
6
20
-
-
25
-
30
-
ns
2
100
-
-
125
-
150
-
ns
4.5
20
-
-
25
-
30
-
ns
6
17
-
-
21
-
26
-
ns
2
80
-
-
100
-
120
-
ns
4.5
16
-
-
20
-
24
-
ns
6
14
-
-
17
-
20
-
ns
2
100
-
-
125
-
150
-
ns
4.5
20
-
-
25
-
30
-
ns
6
17
-
-
21
-
26
-
ns
2
80
-
-
100
-
120
-
ns
4.5
16
-
-
20
-
24
-
ns
6
14
-
-
17
-
20
-
ns
2
0
-
-
0
-
0
-
ns
4.5
0
-
-
0
-
0
-
ns
6
0
-
-
0
-
0
-
ns
2
80
-
-
100
-
120
-
ns
4.5
16
-
-
20
-
24
-
ns
6
14
-
-
17
-
20
-
ns
2
80
-
-
100
-
120
-
ns
4.5
16
-
-
20
-
24
-
ns
6
14
-
-
17
-
20
-
ns
2
5
-
-
5
-
5
-
ns
4.5
5
-
-
5
-
5
-
ns
6
5
-
-
5
-
5
-
ns
2
5
-
-
4
-
3
-
MHz
4.5
22
-
-
18
-
15
-
MHz
6
24
-
-
21
-
18
-
MHz
2
5
-
-
4
-
3
-
MHz
4.5
25
-
-
20
-
17
-
MHz
6
29
-
-
24
-
20
-
MHz
2
-
-
-
-
-
-
-
ns
4.5
23
-
-
29
-
35
-
ns
6
-
-
-
-
-
-
-
ns
2
-
-
-
-
-
-
-
ns
4.5
23
-
-
29
-
35
-
ns
6
-
-
-
-
-
-
-
ns
5
CD74HC192, CD74HC193, CD74HCT193
Prerequisite For Switching Specifications
PARAMETER
SYMBOL
PL
VCC
(V)
tW
MR
Hold Time
Hold Time
MR to CPU, CPD
-
-
-
-
ns
-
24
-
ns
6
-
-
-
-
-
-
-
ns
2
-
-
-
-
-
-
-
ns
4.5
20
-
-
25
-
30
-
ns
6
-
-
-
-
-
-
-
ns
2
-
-
-
-
-
-
-
ns
4.5
15
-
-
19
-
22
-
ns
6
-
-
-
-
-
-
-
ns
2
-
-
-
-
-
-
-
ns
4.5
0
-
-
0
-
0
-
ns
6
-
-
-
-
-
-
-
ns
2
-
-
-
-
-
-
-
ns
4.5
16
-
-
20
-
24
-
ns
6
-
-
-
-
-
-
-
ns
2
-
-
-
-
-
-
-
ns
4.5
15
-
-
19
-
22
-
ns
6
-
-
-
-
-
-
-
ns
2
-
-
-
-
-
-
-
ns
4.5
5
-
-
5
-
5
-
ns
6
-
-
-
-
-
-
-
ns
2
-
-
-
-
-
-
-
MHz
4.5
22
-
-
18
-
15
-
MHz
6
-
-
-
-
-
-
-
MHz
fMAX
193
Switching Specifications
PARAMETER
HC TYPES
Propagation Delay
CPU to Qn
2
-
-
-
-
-
-
-
MHz
4.5
22
-
-
18
-
15
-
MHz
6
-
-
-
-
-
-
-
MHz
Input tr, tf = 6ns
SYMBOL
tPLH, tPHL
CPU to TCU
CPD to TCD
UNITS
20
192
CPU, CPD
MAX
-
fMAX
CPU, CPD
MIN
-
tREC
Maximum Frequency
MAX
-
tREC
PL to CPU, CPD
MIN
-
CPU to CPD
Recovery Time
MAX
-
tH
CPD to CPU or
TYP
-55oC TO 125oC
16
tH
Pn to PL
MIN
-40oC TO 85oC
2
tSU
Pn to PL
25oC
4.5
tW
Set-up Time
(Continued)
tPLH, tPHL
tPLH, tPHL
TEST
CONDITIONS
25oC
-40oC TO 85oC -55oC TO 125oC
VCC
(V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
CL = 50pF
2
-
-
125
-
155
-
190
ns
CL = 50pF
4.5
-
-
25
-
31
-
38
ns
CL = 15pF
5
-
10
-
-
-
-
-
ns
CL = 50pF
6
-
21
-
26
-
32
ns
CL = 50pF
2
-
-
125
-
155
-
190
ns
CL = 50pF
4.5
-
-
25
-
31
-
38
ns
CL = 15pF
5
-
10
-
-
-
-
-
ns
CL = 50pF
6
-
-
21
-
26
-
32
ns
CL = 50pF
2
-
-
220
-
270
-
325
ns
CL = 50pF
4.5
-
-
43
-
54
-
65
ns
CL = 15pF
5
-
18
-
-
-
-
-
ns
CL = 50pF
6
-
-
37
-
46
-
55
ns
6
CD74HC192, CD74HC193, CD74HCT193
Switching Specifications
PARAMETER
CPD to Qn
PL to Qn
MR to Qn
Transition Time
Input tr, tf = 6ns (Continued)
SYMBOL
tPLH, tPHL
CL = 50pF
2
CL = 50pF
4.5
CL = 15pF
5
-
CL = 50pF
6
-
CL = 50pF
2
-
CL = 50pF
4.5
CL = 15pF
5
CL = 50pF
6
tPLH, tPHL
tPHL
tTLH, tTHL
VCC
(V)
25oC
TEST
CONDITIONS
MIN
-40oC TO 85oC -55oC TO 125oC
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
-
-
220
-
270
-
325
ns
-
-
43
-
54
-
65
ns
18
-
-
-
-
-
37
-
46
-
55
ns
-
220
-
275
-
330
ns
-
-
44
-
55
-
66
ns
-
18
-
-
-
-
-
ns
-
-
37
-
47
-
56
ns
ns
CL = 50pF
2
-
-
200
-
250
-
300
ns
CL = 50pF
4.5
-
-
40
-
50
-
60
ns
CL = 15pF
5
-
17
-
-
-
-
-
ns
CL = 50pF
6
-
-
34
-
43
-
51
ns
CL = 50pF
2
-
-
75
-
95
-
110
ns
Q, TCU, TCD
4.5
-
-
15
-
19
-
22
ns
6
-
-
13
-
16
-
19
ns
Input Capacitance
CIN
CL = 50pF
-
-
-
10
-
10
-
10
pF
Power Dissipation Capacitance
CPD
CL = 15pF
5
-
40
-
-
-
-
-
pF
CL = 50pF
4.5
-
-
27
-
34
-
41
ns
HCT TYPES
Propagation Delay
tPLH, tPHL
CPU to TCU
CPU to TCD
CPU to Qn
tPLH, tPHL
tPLH, tPHL
CPD to Qn
tPLH, tPHL
PL to Qn
tPLH, tPHL
MR to Qn
tPHL
Transition Time
tTLH, tTHL
CL = 15pF
5
-
11
-
-
-
-
-
ns
CL = 50pF
4.5
-
-
27
-
34
-
41
ns
CL = 15pF
5
-
11
-
-
-
-
-
ns
CL = 50pF
4.5
-
-
40
-
50
-
60
ns
CL = 15pF
5
-
17
-
-
-
-
-
ns
CL = 50pF
4.5
-
-
40
-
50
-
60
ns
CL = 15pF
5
-
17
-
-
-
-
-
ns
CL = 50pF
4.5
-
-
46
-
58
-
69
ns
CL = 15pF
5
-
21
-
-
-
-
-
ns
CL = 50pF
4.5
-
-
43
-
54
-
65
ns
CL = 15pF
5
-
18
-
-
-
-
-
ns
4.5
-
-
15
-
19
-
22
ns
CL = 50pF
Q, TCU, TCD
Input Capacitance
CIN
CL = 50pF
-
-
-
10
-
10
-
10
pF
Power Dissipation Capacitance
CPD
CL = 15pF
5
-
50
-
-
-
-
-
pF
NOTES:
5. CPD is used to determine the dynamic power consumption, per gate.
6. PD = VCC2 fi + ∑ (CL VCC2) where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.
7
CD74HC192, CD74HC193, CD74HCT193
Test Circuits and Waveforms
MASTER RESET
ASYNCHRONOUS PARALLEL LOAD
P0
PRESET DATA
P1
P2
P3
SEQUENCES:
1. RESET OUTPUTS TO ZERO.
CLOCK UP
2. LOAD (PRESET) TO BCD SEVEN.
3. COUNT UP TO EIGHT, NINE,
CLOCK DOWN
TERMINAL COUNT UP, ZERO,
ONE AND TWO.
Q0
4. COUNT DOWN TO ONE, ZERO,
TERMINAL COUNT DOWN, NINE,
Q1
EIGHT AND SEVEN.
OUTPUTS
Q2
Q3
TERMINAL COUNT UP
TERMINAL COUNT DOWN
0
8
7
RESET PRESET
9
0
1
COUNT UP
2
1
0
9
8
7
COUNT DOWN
FIGURE 1. CD74HC192 SYNCHRONOUS DECADE COUNTERS, TYPICAL RESET, PRESET AND COUNT SEQUENCES
8
CD74HC192, CD74HC193, CD74HCT193
Test Circuits and Waveforms
(Continued)
MASTER RESET
ASYNCHRONOUS PARALLEL LOAD
P0
P1
PRESET DATA
P2
P3
SEQUENCES:
1. RESET OUTPUTS TO ZERO.
2. LOAD (PRESET) TO BINARY THIRTEEN.
CLOCK UP
3. COUNT UP TO FOURTEEN,
CLOCK DOWN
FIFTEEN, TERMINAL COUNT UP,
ZERO, ONE AND TWO.
4. COUNT DOWN TO ONE, ZERO,
Q0
TERMINAL COUNT DOWN,
FIFTEEN, FOURTEEN AND
Q1
THIRTEEN.
OUTPUTS
Q2
Q3
TERMINAL COUNT UP
TERMINAL COUNT DOWN
0
NOTES:
1. Master reset overrides load data and clock inputs.
14
13
RESET PRESET
15
0
1
2
1
COUNT UP
0
15
14
13
COUNT DOWN
2. When counting up, clock-down input must be high.
When counting down, clock-up input must be high.
FIGURE 2. CD74HC193 SYNCHRONOUS BINARY COUNTERS, TYPICAL RESET, PRESET AND COUNT SEQUENCES
l/fMAX
CPU OR CPD
VS
VS
VS
INPUT LEVEL
INPUT LEVEL
CPU OR CPD
VS
VS
tW
tPHL
VS
Qn
VS
FIGURE 4. CLOCK TO TERMINAL COUNT DELAYS
INPUT LEVEL
Pn
tW
VS
tW
VS
VS
VS
tREC
CPU OR CPD
Qn
VS
TCU OR TCD
VS
FIGURE 3. CLOCK TO OUTPUT DELAYS AND CLOCK PULSE
WIDTH
PL
tPLH
tPHL
tPLH
MR
INPUT LEVEL
VS
VS
VS
CPU OR CPD
INPUT LEVEL
VS
tPHL
Qn
VS
FIGURE 5. PARALLEL LOAD PULSE WIDTH, PARALLEL
LOAD TO OUTPUT DELAYS, AND PARALLEL
LOAD TO CLOCK RECOVERY TIME
INPUT LEVEL
tREC
tW
tPHL
tPLH
VS
VS
INPUT LEVEL
FIGURE 6. MASTER RESET PULSE WIDTH, MASTER RESET
TO OUTPUT DELAY AND MASTER RESET TO
CLOCK RECOVERY TIME
9
CD74HC192, CD74HC193, CD74HCT193
Test Circuits and Waveforms
(Continued)
VS
Pn
tSU(H)
PL
Qn
tH
tSU(L)
VS
INPUT LEVEL
tH
VS
INPUT LEVEL
Q=p
Q=p
FIGURE 7. SET-UP AND HOLD TIMES DATA TO PARALLEL LOAD (PL)
DATA INPUT
UP CLOCK
DOWN CLOCK
ASYNCHRONOUS,
PARALLEL LOAD
P0 P1 P2 P3
TCU
CPU
TCD
CPD
PL
MR
Q0 Q1 Q2 Q3
P0 P1 P2 P3
TCU
CPU
TCD
CPD
PL
MR
Q0 Q1 Q2 Q3
BORROW
CARRY
RESET
OUTPUT
FIGURE 8. CASCADED UP/DOWN COUNTER WITH PARALLEL LOAD
0
4
0
15
5
15
5
14
6
14
6
13
7
13
7
8
12
12
1
11
2
10
3
9
1
11
2
10
3
9
4
8
COUNT DOWN
COUNT UP
NOTE: Illegal states in BCD counters corrected in one count.
NOTE: Illegal states in BCD counters corrected in one or two counts.
FIGURE 9. CD74HC192, CD74HCT193 STATE DIAGRAMS
10
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