TI CD74HCT240E High speed cmos logic octal buffer/line drivers, three-state Datasheet

[ /Title
(CD74
HC240
,
CD74
HCT24
0,
CD74
HC241
,
CD74
HCT24
1,
CD74
HC244
,
CD74
CD74HC240, CD74HCT240,
CD74HC241, CD74HCT241,
CD74HC244, CD74HCT244
Data sheet acquired from Harris Semiconductor
SCHS167
High Speed CMOS Logic
Octal Buffer/Line Drivers, Three-State
November 1997
Features
• CD74HC/HCT240 Inverting
• CD74HC/HCT241 Non-Inverting
• CD74HC/HCT244 Non-Inverting
• Typical Propagation Delay = 8ns at VCC = 5V,
CL = 15pF, TA = 25oC for HC240
• Three-State Outputs
• Buffered Inputs
• High-Current Bus Driver Outputs
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH
Pinout
CD74HC240, CD74HCT240, CD74HC241, CD74HCT241,
CD74HC244, CD74HCT244
(PDIP, SOIC)
TOP VIEW
241
244
240
241
244
1OE
1OE
1
1A0
1A0
2
19 2OE (241) 2OE (240, 244)
2Y3
2Y3
3
18 1Y0
1Y0
1A1
1A1
4
17 2A3
2A3
2Y2
2Y2
5
16 1Y1
1Y1
1A2
1A2
6
15 2A2
2A2
2Y1
2Y1
7
14 1Y2
1Y2
1A3
1A3
8
13 2A1
2A1
2Y0
9
12 1Y3
1Y3
GND 10
11 2A0
2A0
2Y0
GND
20 VCC
240
VCC
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
© Harris Corporation 1997
1
File Number
1656.1
CD74HC240, CD74HCT240, CD74HC241, CD74HCT241, CD74HC244, CD74HCT244
Description
Ordering Information
The Harris CD74HC240 and CD74HCT240 are inverting
three-state buffers having two active-low output enables. The
Harris CD74HC241, CD74HCT241, CD74HC244 and
CD74HCT244 are non-inverting three-state buffers that differ
only in that the 241 has one active-high and one active-low
output enable, and the 244 has two active-low output
enables. All three types have identical pinouts.
CD74HCT244E
-55 to 125
20 Ld PDIP
E20.3
CD74HC240M
-55 to 125
20 Ld SOIC
M20.3
CD74HCT241M
-55 to 125
20 Ld SOIC
M20.3
Ordering Information
CD74HCT240M
-55 to 125
20 Ld SOIC
M20.3
CD74HC244M
-55 to 125
20 Ld SOIC
M20.3
CD74HCT244M
-55 to 125
20 Ld SOIC
M20.3
PART NUMBER
TEMP. RANGE
(oC)
PART NUMBER
PKG.
NO.
PACKAGE
TEMP. RANGE
(oC)
PACKAGE
PKG.
NO.
CD74HC240E
-55 to 125
20 Ld PDIP
E20.3
CD74HCT240E
-55 to 125
20 Ld PDIP
E20.3
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
CD74HC241E
-55 to 125
20 Ld PDIP
E20.3
CD74HCT241E
-55 to 125
20 Ld PDIP
E20.3
2. Wafer and die for this part number is available which meets all
electrical specifications. Please contact your local sales office or
Harris customer service for ordering information.
CD74HC244E
-55 to 125
20 Ld PDIP
E20.3
NOTES:
Functional Diagram
241
AND
244 240
2
18
4
16
6
14
8
12
11
9
13
7
15
5
240
17
AND 2A3
244 241
3
1A0
1A1
1A2
1A3
2A0
2A1
2A2
1
1OE 1OE
2OE 2OE
19
2
1Y0
1Y0
1Y1
1Y1
1Y2
1Y2
1Y3
1Y3
2Y0
2Y0
2Y1
2Y1
2Y2
2Y2
2Y3
2Y3
VCC = 20
GND = 10
CD74HC240, CD74HCT240, CD74HC241, CD74HCT241, CD74HC244, CD74HCT244
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, IIK
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
DC Drain Current, per Output, IO
For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . . ±35mA
DC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±70mA
Thermal Resistance (Typical, Note 3)
θJA (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
125
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
120
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
3. θJA is measured with the component mounted on an evaluation PC board in free air.
DC Electrical Specifications
TEST
CONDITIONS
PARAMETER
SYMBOL
VI (V)
VIH
-
25oC
IO (mA) VCC (V)
-40oC TO 85oC
-55oC TO 125oC
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
2
1.5
-
-
1.5
-
1.5
-
V
4.5
3.15
-
-
3.15
-
3.15
-
V
6
4.2
-
-
4.2
-
4.2
-
V
2
-
-
0.5
-
0.5
-
0.5
V
4.5
-
-
1.35
-
1.35
-
1.35
V
HC TYPES
High Level Input
Voltage
Low Level Input
Voltage
VIL
High Level Output
Voltage
CMOS Loads
VOH
-
VIH or
VIL
High Level Output
Voltage
TTL Loads
Low Level Output
Voltage
CMOS Loads
VOL
VIH or
VIL
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
Quiescent Device
Current
-
-
6
-
-
1.8
-
1.8
-
1.8
V
-0.02
2
1.9
-
-
1.9
-
1.9
-
V
-0.02
4.5
4.4
-
-
4.4
-
4.4
-
V
-0.02
6
5.9
-
-
5.9
-
5.9
-
V
-6
4.5
3.98
-
-
3.84
-
3.7
-
V
-7.8
6
5.48
-
-
5.34
-
5.2
-
V
0.02
2
-
-
0.1
-
0.1
-
0.1
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
0.02
6
-
-
0.1
-
0.1
-
0.1
V
6
4.5
-
-
0.26
-
0.33
-
0.4
V
7.8
6
-
-
0.26
-
0.33
-
0.4
V
II
VCC or
GND
-
6
-
-
±0.1
-
±1
-
±1
µA
ICC
VCC or
GND
0
6
-
-
8
-
80
-
160
µA
3
CD74HC240, CD74HCT240, CD74HC241, CD74HCT241, CD74HC244, CD74HCT244
DC Electrical Specifications
(Continued)
TEST
CONDITIONS
25oC
-55oC TO 125oC
SYMBOL
VI (V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
IOZ
VIL or
VIH
-
6
-
-
±0.5
-
±0.5
-
±10
µA
High Level Input
Voltage
VIH
-
-
4.5 to
5.5
2
-
-
2
-
2
-
V
Low Level Input
Voltage
VIL
-
-
4.5 to
5.5
-
-
0.8
-
0.8
-
0.8
V
High Level Output
Voltage
CMOS Loads
VOH
VIH or
VIL
-0.02
4.5
4.4
-
-
4.4
-
4.4
-
V
-6
4.5
3.98
-
-
3.84
-
3.7
-
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
6
4.5
-
-
0.26
-
0.33
-
0.4
V
PARAMETER
Three-State Leakage
Current
IO (mA) VCC (V)
-40oC TO 85oC
HCT TYPES
High Level Output
Voltage
TTL Loads
Low Level Output
Voltage
CMOS Loads
VOL
VIH or
VIL
Low Level Output
Voltage
TTL Loads
II
VCC to
GND
0
5.5
-
-
±0.1
-
±1
-
±1
µA
ICC
VCC or
GND
0
5.5
-
-
8
-
80
-
160
µA
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
(Note 4)
∆ICC
VCC
-2.1
-
4.5 to
5.5
-
100
360
-
450
-
490
µA
Three-State Leakage
Current
IOZ
VIL or
VIH
-
5.5
-
-
±0.5
-
±5
-
±10
µA
Input Leakage
Current
Quiescent Device
Current
NOTE:
4. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.
HCT Input Loading Table
INPUT
UNIT LOADS
CD74HCT240
nA0-A3
1.5
1OE
0.7
2OE
0.7
CD74HCT241
nA0-A3
0.7
1OE
0.7
2OE
1.5
CD74HCT244
nA0-A3
0.7
1OE
0.7
2OE
0.7
NOTE: Unit Load is ∆ICC limit specified in DC Electrical
Specifications table, e.g., 360µA max at 25oC.
4
CD74HC240, CD74HCT240, CD74HC241, CD74HCT241, CD74HC244, CD74HCT244
Switching Specifications
PARAMETER
CL = 50pF, Input tr, tf = 6ns
SYMBOL
TEST
CONDITIONS
tPLH, tPHL
CL = 50pF
25oC
-40oC TO 85oC
-55oC TO 125oC
VCC
(V)
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
2
-
-
100
-
-
125
-
-
150
ns
4.5
-
-
20
-
-
25
-
-
30
ns
CL = 15pF
5
-
8
-
-
-
-
-
-
-
ns
CL = 50pF
6
-
-
17
-
-
21
-
-
26
ns
CL = 50pF
2
-
-
110
-
-
140
-
-
165
ns
4.5
-
-
22
-
-
28
-
-
33
ns
CL = 15pF
5
-
9
-
-
-
-
-
-
-
ns
CL = 50pF
6
-
-
19
-
-
24
-
-
28
ns
CL = 50pF
2
-
-
110
-
-
140
-
-
165
ns
4.5
-
-
22
-
-
28
-
-
33
ns
CL = 15pF
5
-
9
-
-
-
-
-
-
-
ns
CL = 50pF
6
-
-
19
-
-
24
-
-
28
ns
CL = 50pF
2
-
-
150
-
-
190
-
-
225
ns
4.5
-
-
30
-
-
38
-
-
45
ns
5
-
12
-
-
-
-
-
-
-
ns
6
-
-
26
-
-
33
-
-
38
ns
2
-
-
60
-
-
75
-
-
90
ns
4.5
-
-
12
-
-
15
-
-
18
ns
6
-
-
10
-
-
13
-
-
15
ns
MAX UNITS
HC TYPES
Propagation Delay
Data to Outputs
HC240
Data to Outputs
HC241
Data to Outputs
HC244
Output Enable and Disable
Time
Output Transition Time
tPLH, tPHL
tPLH, tPHL
tTHL, tTLH
tTLH, tTHL
CL = 50pF
Input Capacitance
CI
CL = 50pF
-
10
-
10
-
-
10
-
-
10
pF
Three-State Output
Capacitance
CO
CL = 50pF
-
-
-
20
-
-
20
-
-
20
pF
Power Dissipation Capacitance
(Notes 5, 6)
CPD
CL = 15pF
HC240
5
-
38
-
-
-
-
-
-
-
pF
HC241
5
-
34
-
-
-
-
-
-
-
pF
HC244
5
-
46
-
-
-
-
-
-
-
pF
CL = 50pF
4.5
-
-
22
-
-
28
-
-
33
ns
CL = 15pF
5
-
9
-
-
-
-
-
-
-
ns
CL = 50pF
4.5
-
-
25
-
-
31
-
-
38
ns
CL = 15pF
5
-
10
-
-
-
-
-
-
-
ns
CL = 50pF
4.5
-
-
25
-
-
31
-
-
38
ns
CL = 15pF
5
-
10
-
-
-
-
-
-
-
ns
HCT TYPES
Propagation Delay
Data to Outputs
HCT240
tPHL, tPLH
Data to Outputs
HCT241
tPHL, tPLH
Data to Outputs
HCT244
tPHL, tPLH
5
CD74HC240, CD74HCT240, CD74HC241, CD74HCT241, CD74HC244, CD74HCT244
Switching Specifications
CL = 50pF, Input tr, tf = 6ns (Continued)
25oC
-40oC TO 85oC
-55oC TO 125oC
SYMBOL
TEST
CONDITIONS
VCC
(V)
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
Output Enable and Disable
Times
tTLH, tTHL
CL = 50pF
4.5
-
-
30
-
-
38
-
-
45
ns
Output Transition Time
tTHL, tTLH
CL = 50pF
4.5
-
-
12
-
-
15
-
-
18
ns
CI
CL = 50pF
-
10
-
10
-
-
10
-
-
10
pF
HCT240
-
5
-
40
-
-
-
-
-
-
-
pF
HCT241
-
5
-
38
-
-
-
-
-
-
-
pF
HCT244
-
5
-
40
-
-
-
-
-
-
-
pF
PARAMETER
Input Capacitance
Power Dissipation Capacitance
(Notes 5, 6))
MAX UNITS
CPD
NOTES:
5. CPD is used to determine the dynamic power consumption, per channel.
6. PD = VCC2 fi (CPD + CL) where fi = Input Frequency, fO = Output Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.
Test Circuits and Waveforms
tr = 6ns
tf = 6ns
VCC
90%
50%
10%
INPUT
GND
tTLH
90%
INVERTING
OUTPUT
tPHL
FIGURE 1. HC TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
6ns
OUTPUT
DISABLE
GND
OUTPUT LOW
TO OFF
10%
OUTPUT HIGH
TO OFF
OUTPUTS
ENABLED
OUTPUT HIGH
TO OFF
50%
OUTPUTS
DISABLED
OUTPUTS
ENABLED
OUTPUTS
ENABLED
FIGURE 3. HC THREE-STATE PROPAGATION DELAY
WAVEFORM
3V
0.3
GND
1.3V
10%
tPHZ
tPZH
90%
6ns
tPZL
tPLZ
50%
tPHZ
tf
2.7
1.3
tPZL
tPLZ
OUTPUT LOW
TO OFF
6ns
tr
VCC
10%
tPLH
FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
6ns
90%
50%
tTLH
1.3V
10%
tPLH
tPHL
GND
tTHL
90%
50%
10%
INVERTING
OUTPUT
3V
2.7V
1.3V
0.3V
INPUT
tTHL
OUTPUT
DISABLE
tf = 6ns
tr = 6ns
90%
tPZH
1.3V
OUTPUTS
DISABLED
OUTPUTS
ENABLED
FIGURE 4. HCT THREE-STATE PROPAGATION DELAY
WAVEFORM
6
CD74HC240, CD74HCT240, CD74HC241, CD74HCT241, CD74HC244, CD74HCT244
Test Circuits and Waveforms
OTHER
INPUTS
TIED HIGH
OR LOW
OUTPUT
DISABLE
(Continued)
IC WITH
THREESTATE
OUTPUT
OUTPUT
RL = 1kΩ
CL
50pF
VCC FOR tPLZ AND tPZL
GND FOR tPHZ AND tPZH
NOTE: Open drain waveforms tPLZ and tPZL are the same as those for three-state shown on the left. The test circuit is Output RL = 1kΩ to
VCC, CL = 50pF.
FIGURE 5. HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT
7
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