CDCLVP110 www.ti.com SCAS683A – JUNE 2002 – REVISED AUGUST 2002 LOW-VOLTAGE 1:10 LVPECL/HSTL WITH SELECTABLE INPUT CLOCK DRIVER FEATURES • • • • • • • • • DESCRIPTION Distributes One Differential Clock Input Pair LVPECL/HSTL to 10 Differential LVPECL Clock Outputs Fully Compatible With LVECL/LVPECL/HSTL Single Supply Voltage Required, ±3.3-V or ±2.5-V Supply Selectable Clock Input Through CLK_SEL Low-Output Skew (Typ 15 ps) for Clock-Distribution Applications VBB Reference Voltage Output for Single-Ended Clocking Available in a 32-Pin LQFP Package Frequency Range From DC to 3.5 GHz Pin-to-Pin Compatible With MC100 Series EP111, ES6111, LVEP111, PTN1111 LQFP PACKAGE (TOP VIEW) The CDCLVP110 clock driver distributes one differential clock pair of either LVPECL or HSTL (selectable) input, (CLK0, CLK1) to ten pairs of differential LVPECL clock (Q0, Q9) outputs with minimum skew for clock distribution. The CDCLVP110 can accept two clock sources into an input multiplexer. The CLK0 input accepts either LVECL/LVPECL input signals, while CLK1 accepts an HSTL input signal when operated under LVPECL conditions. The CDCLVP110 is specifically designed for driving 50-Ω transmission lines. The VBB reference voltage output is used if single-ended input operation is required. In this case the VBB pin should be connected to CLK0 and bypassed to GND via a 10-nF capacitor. However, for high-speed performance up to 3.5 GHz, the differential mode is strongly recommended. Q3 Q3 Q4 Q4 Q5 Q5 Q6 Q6 The CDCLVP110 is characterized for operation from -40°C to 85°C. 24 23 22 21 20 19 18 17 VCC Q2 Q2 Q1 Q1 Q0 Q0 VCC 25 16 26 15 27 14 28 13 29 12 30 11 31 10 32 9 4 5 6 7 8 VCC CLK_SEL CLK0 CLK0 VBB CLK1 CLK1 VEE 1 2 3 VCC Q7 Q7 Q8 Q8 Q9 Q9 VCC FUNCTION TABLE CLK_SEL ACTIVE CLOCK INPUT 0 CLK0, CLK0 1 CLK1, CLK1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2002, Texas Instruments Incorporated CDCLVP110 www.ti.com SCAS683A – JUNE 2002 – REVISED AUGUST 2002 31 30 29 28 27 26 24 23 3 CLK0 4 CLK0 0 22 21 6 CLK1 7 CLK1 20 1 19 18 17 2 CLK_SEL 15 14 13 12 11 VBB 5 10 Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 Q4 Q4 Q5 Q5 Q6 Q6 Q7 Q7 Q8 Q8 Q9 Q9 TERMINAL FUNCTIONS TERMINAL NAME CLK_SEL CLK0, CLK0 CLK1, CLK1 DESCRIPTION NO. 2 Clock select. Used to select between CLK0 and CLK1 input pairs. 3, 4 Differential LVECL/LVPECL input pair 6, 7 Differential HSTL input pair Q [9:0] 11, 13, 15, 18, 20, 22, 24, 27, 29, 31 LVECL/LVPECL clock outputs, these outputs provide low-skew copies of CLKn. Q[9:0] 10, 12, 14, 17, 19, 21,23, 26, 28, 30 LVECL/LVPECL complementary clock outputs, these outputs provide copies of CLKn. VBB 5 VCC 1, 9, 16, 25, 32 VEE 8 2 Reference voltage output for single-ended input operation Supply voltage Device ground or negative supply voltage in ECL mode CDCLVP110 www.ti.com SCAS683A – JUNE 2002 – REVISED AUGUST 2002 ABSOLUTE MAXIMUM RATINGS (1) VCC Supply voltage -0.3 V to 4.6 V VI Input voltage -0.3 V to VCC + 0.5 V VO Output voltage -0.3 V to VCC + 0.5 V IIN Input current ±20 mA VEE Negative supply voltage -0.3 V to 4.6 V IBB Sink/source current -1 to 1 mA IO DC output current -50 mA Tstg Storage temperature range -65°C to 150°C (1) Stresses beyond those listed under "absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS MIN VCC Supply voltage (relative to VEE) TA (1) Operating free-air temperature (1) NOM MAX 2.375 2.5/3.3 3.8 V 85 °C -40 UNIT Operating junction temperature affects device lifetime. The continuous operation junction temperature is recommended to be at max 110°C. The device ac and dc parameters are specified up to 85°C ambient temperature. See the PCB Layout Guidelines for CDCLVP110 application note, literature number SCAA057 for more details. PACKAGE THERMAL IMPEDANCE TEST CONDITION ΘJA ΘJC (1) Thermal resistance junction to ambient (1) MAX UNIT 0 LFM MIN 78 °C/W 150 LFM 73 °C/W 250 LFM 71 °C/W 500 LFM 68 °C/W 51 °C/W Thermal resistance junction to case According to JESD 51-7 standard. LVECL DC ELECTRICAL CHARACTERISTICS Vsupply: VCC = 0 V, VEE = -2.375 V to -3.8 V PARAMETER IEE ICC IIN Supply internal current Output and internal supply current Input current TEST CONDITIONS Absolute value of current All outputs terminated 50 Ω to VCC - 2 V Includes pullup/pulldown resistors For VEE = -3 to -3.8 V, IBB = -0.2 mA VBB Internally generated bias voltage VEE = -2.375 to -2.75 V, IBB = -0.2 mA VIH High-level input voltage (CLK_SEL) MIN TYP MAX -40°C 40 78 25°C 45 82 85°C 48 UNIT mA 85 -40°C 343 25°C 370 85°C 380 -40°C, 25°C, 85°C 150 -40°C -1.38 -1.26 25°C -1.42 -1.26 85°C -1.45 -1.26 -40°C, 25°C, 85°C -1.38 -1.16 -40°C, 25°C, 85°C -1.165 -0.88 mA µA V V 3 CDCLVP110 www.ti.com SCAS683A – JUNE 2002 – REVISED AUGUST 2002 LVECL DC ELECTRICAL CHARACTERISTICS (continued) Vsupply: VCC = 0 V, VEE = -2.375 V to -3.8 V PARAMETER TEST CONDITIONS MIN VIL Low-level input voltage (CLK_SEL) VINPP Input amplitude (CLK0, CLK0) Difference of input 9 VIH-VIL , See Note VCM Common-mode voltage (CLK0, CLK0) Cross point of input 9 average (VIH, VIL) VOH High-level output voltage IOH = -21 mA VOL Low-level output voltage VOD (1) (1) IOL = -5 mA Differential output voltage swing Terminated with 50 Ω to VCC - 2 V, See Figure 3 TYP MAX UNIT -40°C, 25°C, 85°C -1.81 -1.475 V -40°C, 25°C, 85°C 0.5 1.3 V -40°C, 25°C, 85°C VEE + 1 -0.3 V -40°C -1.26 -0.9 25°C -1.2 -0.9 85°C -1.15 -0.9 -40°C -1.85 -1.5 25°C -1.85 -1.45 85°C -1.85 -1.4 -40°C, 25°C, 85°C 600 V V V VINPP minimum and maximum is required to maintain ac specifications, actual device function tolerates a minimum VINPP of 100 mV. LVPECL/HSTL DC ELECTRICAL CHARACTERISTICS Vsupply: VCC = 2.375 V to 3.8 V, VEE= 0 V PARAMETER IEE Supply internal current Output and internal supply current ICC IIN Input current TEST CONDITIONS MIN Absolute value of current MAX 40 78 25°C 45 82 85C 48 343 All outputs terminated 50 Ω to VCC - 2 V 25°C 370 85°C 380 Includes pullup/pulldown resistors -40°C, 25°C, 85°C 150 Internally generated bias voltage VEE = -2.375 to -2.75 V, IBB = -0.2 mA UNIT mA 85 -40°C VEE = -3 to -3.8 V, IBB= -0.2 mA VBB TYP -40°C -40°C VCC - 1.38 VCC - 1.26 25°C VCC - 1.42 VCC - 1.26 85°C VCC - 1.45 VCC - 1.26 -40°C, 25°C, 85°C VCC - 1.38 VCC - 1.16 mA µA V VIH High-level input voltage (CLK_SEL) -40°C, 25°C, 85°C VCC - 1.165 VCC - 0.88 V VIL Low-level input voltage (CLK_SEL) -40°C, 25°C, 85°C VCC - 1.81 VCC - 1.475 V VINPP Input amplitude (CLK0, CLK0) Difference of input 9 VIH-VIL, see Note -40°C, 25°C, 85°C 0.5 1.3 V VIC Common-mode voltage (CLK0, CLK0) Cross point of input 9 average (VIH, VIL) -40°C, 25°C, 85°C 1 VCC - 0.3 V (1) 4 (1) VINPP minimum and maximum is required to maintain ac specifications, actual device function tolerates a minimum VINPP of 100 mV. CDCLVP110 www.ti.com SCAS683A – JUNE 2002 – REVISED AUGUST 2002 LVPECL/HSTL DC ELECTRICAL CHARACTERISTICS (continued) Vsupply: VCC = 2.375 V to 3.8 V, VEE= 0 V PARAMETER TEST CONDITIONS MIN TYP MAX VID Differential input voltage (CLK1, CLK1) Difference of input VIH-VIL, See Note (1) -40°C, 25°C, 85°C VI(x) Input crossover voltage (CLK1, CLK1) Cross point of input 9 average (VIH, VIL) -40°C, 25°C, 85°C 0.68 0.9 -40°C High-level output voltage VCC - 1.26 VCC - 0.9 VOH IOH = -21 mA 25°C VCC - 1.2 VCC - 0.9 VCC - 0.9 VOL VOD Low-level output voltage Differential output voltage swing UNIT 0.4 1.9 V V 85°C VCC - 1.15 -40°C VCC - 1.85 VCC - 1.5 IOL = -5 mA 25°C VCC - 1.85 VCC - 1.45 85°C VCC - 1.85 VCC - 1.4 Terminated with 50 Ω to VCC - 2 V, See Figure 4 -40°C, 25°C, 85°C 600 V V mV AC ELECTRICAL CHARACTERISTICS Vsupply: VCC = 2.375 V to 3.8 V, VEE = 0 V or LVECL/LVPECL input VCC = 0 V, VEE = -2.375 V to -3.8 V PARAMETER TEST CONDITIONS MIN tpd Differential propagation delay CLK0, CLK0 to all Q0, Q0… Q9, Q9 Input condition: VCM = 1 V, VPP = 0.5 V tsk(pp) Part-to-part skew See Note B and Figure 1 -40°C, 25°C, 85°C tsk(o) Output-to-output skew See Note A and Figure 1 -40°C, 25°C, 85°C t(JITTER) Cycle-to-cycle RMS jitter f(max) Maximum frequency tr/tf Output rise and fall time (20%, 80%) Functional up to 3.5 GHz, timing specifications apply at 1 GHz, see Figure 3 -40°C, 25°C, 85°C TYP 230 MAX UNIT 350 ps 70 ps 30 ps -40°C, 25°C, 85°C <1 ps -40°C, 25°C, 85°C 3500 MHz 200 ps MAX UNIT 370 ps 70 ps 30 ps <1 ps -40°C, 25°C, 85°C 15 100 HSTL INPUT Vsupply: VCC = 2.375 V to 3.8 V, VEE = 0 V PARAMETER TEST CONDITIONS MIN tpd Differential propagation delay CLK0, CLK0 to all Q0, Q0… Q9, Q9 Input condition: Vx = 0.68 V, Vdif = 0.4 V -40°C, 25°C, 85°C tsk(pp) Part-to-part skew See Note B and Figure 1 -40°C, 25°C, 85°C tsk(o) Output to output skew See Note A and Figure 1 -40°C, 25°C, 85°C t(JITTER) Cycle-to-cycle RMS jitter -40°C, 25°C, 85°C TYP 290 10 5 CDCLVP110 www.ti.com SCAS683A – JUNE 2002 – REVISED AUGUST 2002 HSTL INPUT (continued) Vsupply: VCC = 2.375 V to 3.8 V, VEE = 0 V PARAMETER TEST CONDITIONS f(max) Maximum frequency Functional up to 3.5 GHz, timing specifications apply at 1 GHz, See Figure 4 tr/tf Output rise and fall time (20%, 80%) MIN -40°C, 25°C, 85°C -40°C, 25°C, 85°C 100 TYP MAX UNIT 3500 MHz 200 ps CLKn CLKn Q0 tPLH0 tPLH0 tPLH1 tPLH1 Q0 Q1 Q1 Q2 tPLH2 tPLH2 Q2 tPLH9 Q9 o o o o o tPLH9 Q9 A. Output skew is calculated as the greater of: The difference between the fastest and the slowest tPLHn (n = 0, 1,...9) or the difference between the fastest and the slowest tPHLn (n = 0, 1,...9). B. Part-to-part skew, is calculated as the greater of: The difference between the fastest and the slowest tPLHn (n = 0, 1,...9) across multiple devices or the difference between the fastest and the slowest tPHLn (n = 0, 1,...9) across multiple devices. Figure 1. Waveform for Calculating Both Output and Part-to-Part Skew 6 CDCLVP110 www.ti.com SCAS683A – JUNE 2002 – REVISED AUGUST 2002 VCC ZO = 50 Ω Yn CDCLVP110 Driver LVPECL Receiver ZO = 50 Ω Yn 50 Ω 50 Ω VEE VT = VCC - 2 V VOUT(PP)min- Differential Output Voltage Swing - mV Figure 2. Typical Termination for Output Driver (See the Interfacing Between LVPECL, LVDS, and CML Application Note, Literature Number SCAA056) DIFFERENTIAL OUTPUT VOLTAGE SWING vs FREQUENCY 900 800 VCC = 2.375 V TA = -40°C to 85°C 700 600 500 400 300 200 100 0 1 1.5 2 2.5 3 3.5 f - Frequency - GHz Figure 3. LVPECL Input Using CLK0 Pair, VCM = 1 V, VINdif = 0.5 V 7 CDCLVP110 www.ti.com VOUT(PP)min- Differential Output Voltage Swing - mV SCAS683A – JUNE 2002 – REVISED AUGUST 2002 DIFFERENTIAL OUTPUT VOLTAGE SWING vs FREQUENCY 1000 900 VCC = 2.375 V TA = -40°C to 85°C 800 700 600 500 400 300 200 100 0 1 1.5 2 2.5 3 f - Frequency - GHz Figure 4. HSTL Input Using CLK1 Pair, VCM = 0.68 V, VINdif = 0.4 V 8 3.5 PACKAGE OPTION ADDENDUM www.ti.com 4-Mar-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty CDCLVP110VF ACTIVE LQFP VF 32 250 None CU NIPDAU Level-2-220C-1 YEAR CDCLVP110VFR ACTIVE LQFP VF 32 1000 None CU NIPDAU Level-2-220C-1 YEAR Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. None: Not yet available Lead (Pb-Free). Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens, including bromine (Br) or antimony (Sb) above 0.1% of total product weight. (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder temperature. 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Addendum-Page 1 MECHANICAL DATA MTQF002B – JANUARY 1995 – REVISED MAY 2000 VF (S-PQFP-G32) PLASTIC QUAD FLATPACK 0,45 0,25 0,80 24 0,20 M 17 25 16 32 9 0,13 NOM 1 8 5,60 TYP 7,20 SQ 6,80 9,20 SQ 8,80 Gage Plane 0,05 MIN 0,25 0°– 7° 1,45 1,35 Seating Plane 0,75 0,45 0,10 1,60 MAX 4040172/D 04/00 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. 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