Intersil CDP1824/3 High-reliability cmos 32-word x 8-bit static random-access memory Datasheet

CDP1824/3,
CDP1824C/3
TM
High-Reliability CMOS 32-Word x 8-Bit
Static Random-Access Memory
March 1997
Features
Description
• Access Time
- 610ns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . at VDD = 5V
- 320ns . . . . . . . . . . . . . . . . . . . . . . . . . . . . at VDD = 10V
The CDP1824/3 and CDP1824C/3 types are high-reliability
CMOS 32-word x 8-bit fully static random-access memories
for use in CDP1800-series microprocessor systems. These
parts are compatible with the CDP1802 microprocessor and
will interface directly without additional components.
• No Precharge or Clock Required
Ordering Information
5V
10V
PACKAGE
CDP1824CD3 CDP1824D3 SBDIP
TEMP. RANGE
-55oC to
+125oC
The CDP1824/3 is fully decoded and does not require a precharge or clocking signal for proper operation. It has common input and output and is operated from a single voltage
supply. The MRD signal (output disable control) enables the
three-state output drivers, and overrides the MWR signal. A
CS input is provided for memory expansion.
PKG.
NO.
D18.3
The CDP1824C/3 is functionally identical to the CDP1824/3.
The CDP1824/3 has a recommended operating voltage
range of 4V to 10.5V, and the CDP1824C/3 has an operating
voltage range of 4V to 6.5V.
Pinout
Functional Diagram
CDP1824/3, CDP1824C/3 (SBDIP)
TOP VIEW
MA4
1
18 VDD
MA3
2
17 MWR
MA2
3
16 MRD
MA1
4
15 CS
MA0
5
14 BUS0
BUS7
6
13 BUS1
BUS6
7
12 BUS2
BUS5
8
11 BUS3
VSS
9
10 BUS4
MA4
MA3
MA2
MA1
MA0
2
3
4
5
1
32 X 8-BIT
ARRAY
ADDRESS
DECODER
SENSE
AMPL
MWR
16
17
MRD
I/O BUFFERS
CS
15
VDD = 18
VSS = 9
6
7
8
10
11
12
13
14
BUS BUS BUS BUS BUS BUS BUS BUS
7
6
5
4
3
2
1
0
OPERATIONAL MODES
FUNCTION
CS
MRD
MWR
READ
0
0
X
Output: High/Low Dependent on Data
WRITE
0
1
0
Input: Output Disabled
Not Selected
1
X
X
Output Disabled: High-Impedance State
Standby
0
1
1
Output Disabled: High-Impedance State
Logic 1 = High
Logic 0 = Low
DATA PINS STATUS
X = Don’t Care
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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Copyright © Intersil Americas Inc. 2001. All Rights Reserved
42
File Number
1717.2
CDP1824/3, CDP1824C/3
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage Range, (V DD)
(All Voltages Referenced to VSS Terminal)
CDP1824/3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +11V
CDP1824C/3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5 to +7V
Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to V DD +0.5V
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . . ±10mA
Thermal Resistance (Typical, Note 1)
θJA ( oC/W) θJC (oC/W)
SBDIP Package. . . . . . . . . . . . . . . . . .
75
20
Device Dissipation Per Output Transistor
TA = Full Package Temperature Range
(All Package Types) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mW
Operating Temperature Range (TA)
Package Type D . . . . . . . . . . . . . . . . . . . . . . . . .-55oC to +125oC
Storage Temperature Range (TSTG) . . . . . . . . . . .-65oC to +150oC
Lead Temperature (During Soldering)
At distance 1/16 ± 1/32 In. (1.59 ± 0.79mm)
from case for 10s max . . . . . . . . . . . . . . . . . . . . . . . . . . . . +265oC
Recommended Operating Conditions
TA = Full Package-Temperature Range. For maximum reliability, nominal operating
conditions should be selected so that operation is always within the following ranges:
LIMITS
CDP1824/3
PARAMETER
DC Operating Voltage Range
Input Voltage Range
CDP1824C/3
MIN
MAX
MIN
MAX
UNITS
4
10.5
4
6.5
V
V SS
VDD
VSS
VDD
V
Static Electrical Specifications
CONDITIONS
SYMBOL
VO
(V)
Quiescent Device Current
(Note 1)
IDD
-
0, 5
5
-
50
-
0, 10
10
-
500
Output Voltage Low-Level
(Note 2)
VOL
-
0, 5
Output Voltage High-Level
(Note 2)
V OH
PARAMETER
Input Low Voltage
Input High Voltage
V IL
VIH
IOL
Output High Drive (Source)
Current
IOH
Input Current
IIN
Input Capacitance
Output Capacitance
VDD
(V)
-
Output Low Drive (Sink)
Current
Three-State Output
Leakage Current
VIN
(V)
LIMITS
-55oC, +25oC
IOUT
MIN
MAX
+125oC
MAX
UNITS
-
500
µA
-
1000
µA
MIN
5
-
0.1
-
0.2
V
10
-
0.1
-
0.2
V
-
0, 5
5
4.9
-
4.8
-
V
-
-
10
9.9
-
4.8
-
V
0.5, 4.5
-
5
-
1.5
-
1.5
V
1, 9
-
10
-
3
-
-
V
0.5, 4.5
-
5
3.5
-
3.5
-
V
1, 9
-
10
7
-
7
-
V
0.4
0, 5
5
4
-
1.5
-
mA
0.5
0, 10
10
4
-
2.9
-
mA
4.6
0, 5
5
-
-1
-
-0.75
mA
9.5
0, 10
10
-
-2
-
-1.5
mA
0, 5
5
-
±1
-
±5
µA
0, 10
10
-
±1
-
±5
µA
Any
Input
0, 5
0, 5
5
-
±2
-
±5
µA
0, 10
0, 10
10
-
±2
-
±5
µA
CIN
(Note 2)
-
10
-
10
pF
COUT
(Note 2)
-
15
-
15
pF
NOTES:
1. The CDP1824C/3 meets all 5V Static Electrical Characteristics of the CDP1824/3 except Quiescent Device Current for which the limits
are IDD = 200µA at +25oC/-55oC; IDD = 1000µA at +125oC.
2. Guaranteed, but not tested.
43
CDP1824/3, CDP1824C/3
Read Cycle Dynamic Electrical Specifications
Input tR, tF ≤ 15ns, CL = 50pF
LIMITS
TEST
CONDITIONS
PARAMETER
Access Time From Address Change
Access Time From Chip Select
VDD
(V)
MIN
MAX
MIN
MAX
UNITS
tAA
5
-
610
-
825
ns
10
-
320
-
375
ns
5
-
610
-
825
ns
10
-
320
-
375
ns
5
-
610
-
825
ns
10
-
320
-
375
ns
tAM
tAM
(NOTE 1)
MRD
tAA
MA
CS
tDOA
(NOTE 1)
DATA OUT
+125oC
SYMBOL
tDOA
Output Active From MRD
-55oC, +25oC
HIGH IMPEDANCE
NOTE:
1. Minimum timing for valid data output longer times will initiate an earlier, but invalid output.
FIGURE 1. READ CYCLE TIMING DIAGRAM
44
CDP1824/3, CDP1824C/3
Write Cycle Dynamic Electrical Specifications
Input tR, tF ≤ 15ns, CL = 50pF
LIMITS
TEST
CONDITIONS
PARAMETER
Write Pulse Width
Data Setup Time
VDD
(V)
(NOTE 1)
MIN
MAX
(NOTE 1)
MIN
MAX
UNITS
tWRW
5
350
-
475
-
ns
10
180
-
220
-
ns
5
400
-
560
-
ns
10
190
-
260
-
ns
5
70
-
90
-
ns
10
35
-
45
-
ns
5
550
-
775
-
ns
10
340
-
475
-
ns
5
550
-
775
-
ns
10
340
-
475
-
ns
tDH
Chip Select Setup Time
tCS
Address Setup Time
+125oC
SYMBOL
tDS
Data Hold Time
-55oC, +25oC
tAS
NOTE:
1. Time required by a device to allow for the indicated function.
MA
tAS
CS
tCS
tWRW
MWR
tDS
tDH
BUS
FIGURE 2. WRITE CYCLE TIMING DIAGRAM
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Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
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45
CDP1824/3, CDP1824C/3
Data Retention Specifications
At TA = +25oC
LIMITS
TEST
CONDITIONS
CDP1824/3
CDP1824C/3
SYMBOL
VDR
(V)
VDD
(V)
MIN
MAX
MIN
MAX
UNITS
Data Retention Voltage
VDR
-
-
2.5
-
2.5
-
V
Data Retention Quiescent Current
IDD
2.5
-
-
10
-
40
µA
tCDR
2.5
5
600
-
600
-
ns
2.5
10
300
-
-
-
ns
2.5
5
600
-
600
-
ns
2.5
10
300
-
-
-
ns
PARAMETER
Chip Deselect to Data Retention Time
Recovery to Normal Operation Time
tRC
DATA RETENTION
MODE
0.95 VDD
VDD
0.95 VDD
VDD
tCDR
tF
tF
(NOTE 1)
tRC
(NOTE 1)
VIH
VIH
CS
VIL
VIL
NOTE: tr, tf > 1µs.
FIGURE 3. LOW VDD DATA RETENTION WAVEFORMS AND TIMING DIAGRAM
Static Burn-In Circuit
VDD
VSS
TYPE
CDP1824
CDP1824C
1
18
2
17
3
16
4
15
5
14
6
13
7
12
8
11
9
10
VDD
All Resistors 47kΩ (±±20%)
VSS
VDD
TEMPERATURE
11V
+125oC
160 Hrs., Min.
7V
+125oC
160 Hrs., Min.
46
TIME
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