Intersil CDP1854A/3 Programmable universal asynchronous receiver/transmitter (uart) Datasheet

CDP1854A,
CDP1854AC
Programmable Universal Asynchronous
Receiver/Transmitter (UART)
March 1997
Features
Description
• Two Operating Modes
- Mode 0 - Functionally Compatible with Industry
Types Such as the TR1602A and CDP6402
- Mode 1 - Interfaces Directly with CDP1800-Series
Microprocessors without Additional Components
The CDP1854A and CDP1854AC are silicon-gate CMOS
Universal Asynchronous Receiver/Transmitter (UART) circuits. They are designed to provide the necessary formatting
and control for interfacing between serial and parallel data.
For example, these UARTs can be used to interface between
a peripheral or terminal with serial I/O ports and the 8-bit
CDP1800-series microprocessor parallel data bus system.
The CDP1854A is capable of full duplex operation, i.e.,
simultaneous conversion of serial input data to parallel output data and parallel input data to serial output data.
• Full or Half Duplex Operation
• Parity, Framing and Overrun Error Detection
• Baud Rate
- DC to 200K Bits/s at VDD . . . . . . . . . . . . . . . . . . . . 5V
- DC to 400K Bits/s at VDD . . . . . . . . . . . . . . . . . . . . 10V
• Fully Programmable with Externally Selectable Word
Length (5-8 Bits), Parity Inhibit, Even/Odd Parity, and
1, 1-1/2, or 2 Stop Bits
• False Start Bit Detection
Ordering Information
PACKAGE
PDIP
Burn-In
TEMP.
RANGE
5V/200K
BAUD
-40oC to +85oC CDP1854ACE
CDP1854ACEX
10V/400K
BAUD
CDP1854AE
PKG.
NO.
E40.6
CDP1854AEX E40.6
PLCC
-40oC to +85oC CDP1854ACQ
CDP1854AQ
N44.65
SBDIP
-40oC to +85oC CDP1854ACD
CDP1854AD
D40.6
Burn-In
CDP1854ACDX
-
The CDP1854A UART can be programmed to operate in one
of two modes by using the mode control input. When the
input is high (MODE = 1), the CDP1854A is directly compatible with the CDP1800-series microprocessor system without
additional interface circuitry. When the mode input is low
(MODE = 0), the device is functionally compatible with industry standard UART’s such as the TR1602A and CDP6402. It
is also pin compatible with these types, except that pin 2 is
used for the mode control input.
The CDP1854A and the CDP1854AC are functionally identical. The CDP1854A has a recommended operating voltage
range of 4V to 10.5V, and the CDP1854AC has a recommended operating voltage range of 4V to 6.5V.
D40.6
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
5-42
File Number
1193.2
CDP1854A, CDP1854AC
Pinouts
40 LEAD SBDIP, PDIP (MODE 0)
TOP VIEW
40 LEAD SBDIP, PDIP (MODE 1)
TOP VIEW
40 T CLOCK
VDD 1
VDD 1
39 EPE
MODE (VSS) 2
40 T CLOCK
MODE (VDD) 2
39 CTS
VSS 3
38 WLS 1
VSS 3
38 ES
RRD 4
37 WLS 2
CS2 4
37 PS1
R BUS 7 5
36 SBS
R BUS 7 5
36 NC
R BUS 6 6
35 PI
R BUS 6 6
35 CS3
R BUS 5 7
34 CRL
R BUS 5 7
34 RD/WR
R BUS 4 8
33 T BUS 7
R BUS 4 8
33 T BUS 7
R BUS 3 9
32 T BUS 6
R BUS 3 9
32 T BUS 6
R BUS 2 10
31 T BUS 5
R BUS 2 10
31 T BUS 5
R BUS 1 11
30 T BUS 4
R BUS 1 11
30 T BUS 4
R BUS 0 12
29 T BUS 3
R BUS 0 12
29 T BUS 3
PE 13
28 T BUS 2
INT 13
28 T BUS 2
FE 14
27 T BUS 1
FE 14
27 T BUS 1
OE 15
26 T BUS 0
PE/OE 15
26 T BUS 0
25 SD0
SFD 16
RSEL 16
25 SD0
R CLOCK 17
24 TSRE
R CLOCK 17
24 RTS
DAR 18
23 THRL
TPB 18
23 CS1
DA 19
22 THRE
DA 19
22 THRE
SDI 20
21 MR
SDI 20
21 CLEAR
NC = NO CONNECT
SBS (NC)
WLS2 (PSI)
EPE (CTS)
WLS1 (ES)
T CLOCK
NC
4
MODE
5
VDD
RRD (CS2)
6
VSS
R BUS 7
44 LEAD PLCC (Q SUFFIX)
TOP VIEW
3
2
1 44 43 42 41 40
R BUS 6
7
39
PI (CS3)
R BUS 5
8
38
CRL(RD/WR)
R BUS 4
9
37
T BUS 7
R BUS 3
10
36
T BUS 6
R BUS 2
11
35
T BUS 5
NC
12
34
NC
R BUS 1
13
33
T BUS 4
R BUS 0
14
32
T BUS 3
PE(INT)
15
31
T BUS 2
FE
16
30
T BUS 1
OE(PE/OE)
17
29
T BUS 0
18 19 20 21 22 23 24 25 26 27 28
5-43
SD0
THRL(CS1)
TSRE(RTS)
THRE(THRE)
NC
MR(CLEAR)
SDI
DA(DA)
(TPB)DAR
R CLOCK
SFD (RSEL)
NOTE:
MODE 0(MODE 1)
CDP1854A, CDP1854AC
Block Diagram
Mode Input High (Mode = 1)
24
39
34
18
1, 2 = VDD
3 = VSS
21 = CLEAR
36 = NC
PSI
ES
16
38
R CLOCK
RECEIVER SECTION
RSEL
RD/WR
CTS
RTS
T CLOCK
40
TPB
CDP1802
INTERFACE
TRANSMITTER SECTION
37
17
SDO
TRANSMITTER
TIMING &
CONTROL
25
RECEIVER
TIMING &
CONTROL
SHIFT
REGISTER
RECEIVER
HOLDING
REGISTER
PARITY
GEN
TRANSMITTER
SHIFT
REGISTER
TRANSMITTER BUS
(26 - 33)
(SEE NOTE 1)
22
14
15
THREE-STATE
DRIVERS
19
DA
13
PE/OE
35
THRE
4
INT
CS1
23
STATUS
REGISTER
INT
FE
SELECT
LOGIC
CS3
CONTROL
REG
CS2
TRANSMITTER
HOLDING
REGISTER
MUX
RECEIVER BUS
(5-12)
(SEE NOTE 1)
(SEE NOTE 1)
NOTE: 1. User Interconnect
FIGURE 1. MODE 1 BLOCK DIAGRAM (CDP1800-SERIES MICROPROCESSOR COMPATIBLE)
5-44
20
SDI
CDP1854A, CDP1854AC
Absolute Maximum Ratings
Thermal Information
DC Supply-Voltage Range, (VDD)
(Voltages Referenced to VSS Terminal)
CDP1854A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5 to +11V
CDP1854AC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5 to +7V
Input Voltage Range, All Inputs . . . . . . . . . . . . . .-0.5 to VDD + 0.5V
DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . . . . .±10mA
Device Dissipation Per Output Transistor
TA = Full Package-Temperature Range . . . . . . . . . . . . . . 100mW
Operating-Temperature Range (TA)
Package Type D . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC
Package Type E and Q . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC
Thermal Resistance (Typical, Note 1)
θJA (oC/W) θJC (oC/W)
SBDIP Package . . . . . . . . . . . . . . . . . .
55
15
PDIP Package . . . . . . . . . . . . . . . . . . .
50
N/A
PLCC Package . . . . . . . . . . . . . . . . . .
46
N/A
Maximum Junction Temperature
Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150oC
Ceramic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
Maximum Storage Temperature Range (TSTG) . . .-65oC to +150oC
Maximum Lead Temperature (Soldering 10s):
At Distance 1/16 ±1/32 inch (1.59 ±0.79mm) . . . . . . . . . . +265oC
NOTE: Printed circuit board mount: 57mm x 57mm minimum area x
1.6mm thick G10 epoxy glass, or equivalent.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of
the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
at TA = -40oC to +85oC, Unless Otherwise Noted
Static Electrical Specifications
CONDITIONS
LIMITS
CDP1854A
PARAMETER
Quiescent Device
Current
IDD
Output Low Drive
(Sink) Current
(Except pins 24 and
25)
IOL
Output High Drive
(Source) Current
IOH
Output Low Drive
(Sink) Current
(Pins 24 and 25)
IOL
Output Voltage
Low-Level (Note 2)
VOL
Output Voltage
High-Level (Note 2)
Input Low Voltage
Input High Voltage
Input Current
VOH
VIL
VIH
IIN
CDP1854AC
VO
(V)
VIN
(V)
VDD
(V)
MIN
(NOTE 1)
TYP
MAX
MIN
(NOTE 1)
TYP
MAX
UNITS
-
0, 5
5
-
0.01
50
-
0.02
200
µA
-
0, 10
10
-
1
200
-
-
-
µA
0.4
0, 5
5
1
2
-
1
2
-
mA
0.5
0, 10
10
2
4
-
-
-
-
mA
4.6
0, 5
5
-0.55
-1.1
-
-0.55
-1.1
-
mA
9.5
0, 10
10
-1.3
-2.6
-
-
-
-
mA
0.4
0, 5
5
1.6
3.5
-
1.6
3.5
-
mA
0.5
0, 10
10
3.2
7
-
-
-
-
mA
-
0, 5
5
-
0
0.1
-
0
0.1
V
-
0, 10
10
-
0
0.1
-
-
-
V
-
0, 5
5
4.9
5
-
4.9
5
-
V
-
0, 10
10
9.9
10
-
-
-
-
V
0.5, 4.5
-
5
-
-
1.5
-
-
1.5
V
0.5, 9.5
-
10
-
-
3
-
-
-
V
0.5, 4.5
-
5
3.5
-
-
3.5
-
-
V
0.5, 9.5
-
10
7
-
-
-
-
-
V
-
0, 5
5
-
-
±1
-
-
±1
µA
-
0, 10
10
-
-
±2
-
-
-
µA
5-45
CDP1854A, CDP1854AC
at TA = -40oC to +85oC, Unless Otherwise Noted (Continued)
Static Electrical Specifications
CONDITIONS
LIMITS
CDP1854A
VO
(V)
VIN
(V)
VDD
(V)
MIN
(NOTE 1)
TYP
MAX
MIN
(NOTE 1)
TYP
MAX
UNITS
0, 5
0, 5
5
-
-
±1
-
-
±1
µA
0, 10
0, 10
10
-
-
±10
-
-
-
µA
-
0, 5
5
-
1.5
-
-
1.5
-
mA
-
0, 10
10
-
6
-
-
-
-
mA
CIN
-
-
-
-
5
7.5
-
5
7.5
pF
COUT
-
-
-
-
10
15
-
10
15
pF
PARAMETER
Three-State Output
Leakage Current
Operating Current
(Note 3)
IOUT
IDD1
Input Capacitance
Output Capacitance
CDP1854AC
NOTES:
1. Typical values are for TA = 25oC.
2. IOL = IOH = 1µA.
3. Operating current is measured at 200kHz or VDD = 5V and 400kHz for VDD = 10V in a CDP1800-series microprocessor system, with
open outputs.
Operating Conditions
At TA = Full Package-Temperature Range. For maximum reliability, operating conditions should be selected so
that operation is always within the following ranges:
CONDITIONS
LIMITS
CDP1854A
CDP1854AC
VDD
(V)
MIN
MAX
MIN
MAX
UNITS
DC Operating Voltage Range
-
4
10.5
4
6.5
V
Input Voltage Range
-
VSS
VDD
VSS
VDD
V
Baud Rate (Receive or Transmit)
5
-
200
-
200
K bits/s
10
-
400
-
-
K bits/s
PARAMETER
5-46
CDP1854A, CDP1854AC
Functional Definitions for CDP1854A
Terminals Mode 1 CDP1800-Series
Microprocessor Compatible
SERIAL DATA IN (SDl):
SIGNAL: FUNCTION
Serial data received on this input line enters the Receiver
Shift Register at a point determined by the character length.
A high-level input voltage must be present when data is not
being received.
VDD:
CLEAR (CLEAR):
Positive supply voltage.
A low-level voltage at this input resets the Interrupt FlipFlop, Receiver Holding Register, Control Register, and
Status Register, and sets SERIAL DATA OUT (SDO) high.
MODE SELECT (MODE):
A high-level voltage at this input selects CDP1800-series
microprocessor Mode operation.
TRANSMlTTER HOLDING REGISTER EMPTY (THRE):
A low-level voltage at this output indicates that the
Transmitter Holding Register has transferred its contents to
the Transmitter Shift Register and may be reloaded with a
new character.
VSS:
Ground
CHIP SELECT 2 (CS2):
A low-level voltage at this input together with CS1 and CS3
selects the CDP1854A UART.
RECEIVER BUS (R BUS 7 - R BUS 0):
Receiver parallel data outputs (may be externally connected
to corresponding transmitter bus terminals).
INTERRUPT (INT):
A low-level voltage at this output indicates the presence of
one or more of the interrupt conditions listed in Table 1.
FRAMlNG ERROR (FE):
CHIP SELECT 1 (CS1):
A high-level voltage at this input together with CS2 and CS3
selects the UART.
REQUEST TO SEND (RTS):
This output signal tells the peripheraI to get ready to receive
data. CLEAR TO SEND (CTS) is the response from the
peripheral. RTS is set to a low-level voltage when data is
latched in the Transmitter Holding Register or TR is set high,
and is reset high when both the Transmitter Holding Register
and Transmitter Shift Register are empty and TR is low.
SERAL DATA OUTPUT (SDO):
A high-level voltage at this output indicates that the received
character has no valid stop bit, i.e., the bit following the parity
bit (if programmed) is not a high-level voltage. This output is
updated each time a character is transferred to the Receiver
Holding Register.
PARITY ERROR or OVERRUN ERROR (PE/OE):
A high-level voltage at this output indicates that either the PE
or OE bit in the Status Register has been set (see Status
Register Bit Assignment, Table 2).
REGISTER SELECT (RSEL):
The contents of the Transmitter Shift Register [start bit, data
bits, parity bit, and stop bit(s)] are serially shifted out on this
output. When no character is being transmitted, a high level
is maintained. Start of transmission is defined as the
transition of the start bit from a high-level to a low-level
output voltage.
TRANSMlTTER BUS (T BUS 0 - T BUS 7):
Transmitter parallel data input. These may be externally
connected to corresponding Receiver bus terminals.
RD/WR:
This input is used to choose either the Control/Status
Registers (high input) or the transmitter/receiver data
registers (low input) according to the truth table in Table 3.
RECEIVER CLOCK (RCLOCK):
Clock input with a frequency 16 times the desired receiver
shift rate.
TPB:
A low-level voltage at this input gates data from the transmitter
bus to the Transmitter Holding Register or the Control Register as chosen by register select. A high-level voltage gates
data from the Receiver Holding Register or the Status Register, as chosen by register select, to the receiver bus.
CHIP SELECT 3 (CS3):
A positive input pulse used as a data load or reset strobe.
With high-level voltage at this input together with CS1 and
CS2 selects the UART.
DATA AVAILABLE (DA):
PERIPHERAL STATUS INTERRUPT (PSI):
A low-level voltage at this output indicates that an entire
character has been received and transferred to the Receiver
Holding Register.
A high-to-low transition on this input line sets a bit in the
Status Register and causes an INTERRUPT (INT = low).
EXTERNAL STATUS (ES):
A low-level voltage at this input sets a bit in the Status
Register.
5-47
CDP1854A, CDP1854AC
CLEAR TO SEND (CTS):
TRANSMITTER CLOCK (TCLOCK):
When this input from peripheral is high, transfer of a
character to the Transmitter Shift Register and shifting of
serial data out is inhibited.
Clock input with a frequency 16 times the desired transmitter
shift rate.
TABLE 1. INTERRUPT SET AND RESET CONDITIONS
(NOTE 1)
SET (INT = LOW)
RESET (INT = HIGH)
CAUSE
CONDITION
TIME
DA (Receipt of Data)
Read of Data
TPB Leading Edge
THRE (Note 2)
(Ability to Reload)
Read of Status or Write of Character
TPB Leading Edge
THRE • TSRE
(Transmitter Done)
Read of Status or Write of Character
TPB Leading Edge
PSI
(Negative Edge)
Read of Status
TPB Trailing Edge
CTS
(Positive Edge when THRE • TSRE)
Read of Status
TPB Leading Edge
NOTES:
1. Interrupts will occur only after the IE bit in the Control Register (see Table 4) has been set.
2. THRE will cause an interrupt only after the TR bit in the Control Register (see Table 4) has been set.
TABLE 2. STATUS REGISTER BIT ASSIGNMENT
BIT
SIGNAL
ALSO AVAILABLE AT TERMINAL
† Polarity reversed at output terminal.
7
6
5
4
3
2
1
0
THRE
TSRE
PSI
ES
FE
PE
OE
DA
22†
-
-
-
14
15
15
19†
BIT SIGNAL: FUNCTION
0
DATA AVAILABLE (DA): When set high, this bit indicates that an entire character has been received and transferred to the Receiver
Holding Register. This signal is also available at Term. 19 but with its polarity reversed.
1
OVERRUN ERROR (OE): When set high, this bit indicates that the Data Available bit was not reset before the next character was
transferred to the Receiver Holding Register. This signal OR’ed with PE is output at Term. 15.
2
PARITY ERROR (PE): When set high, this bit indicates that the received parity bit does not compare to that programmed by the EVEN
PARITY ENABLE (EPE) control. This bit is updated each time a character is transferred to the Receiver Holding Register. This signal
OR’ed with OE is output at Term. 15.
3
FRAMlNG ERROR (FE): When set high, this bit indicates that the received character has no valid stop bit, i.e., the bit following the
parity bit (if programmed) is not a high-level voltage. This bit is updated each time a character is transferred to the Receiver Holding
Register. This signal is also available at Term. 14.
4
EXTERNAL STATUS (ES): This bit is set high by a low-level input at Term. 38 (ES).
5
PERIPHERAL STATUS INTERRUPT (PSI): This bit is set high by a high-to-low voltage transition of Term. 37 (PSI). The INTERRUPT
output (Term. 13) is also asserted (lNT = Iow) when this bit is set.
6
TRANSMlTTER SHIFT REGISTER EMPTY (TSRE): When set high, this bit indicates that the Transmitter Shift Register has completed serial transmission of a full character including stop bit(s). It remains set until the start of transmission of the next character.
7
TRANSMlTTER HOLDING REGISTER EMPTY (THRE): When set high, this bit indicates that the Transmitter Holding Register has
transferred its contents to the Transmitter Shift Register and may be reloaded with a new character. Setting this bit also sets the THRE
output (Term. 22) low and causes an INTERRUPT (lNT = low), if TR is high.
5-48
CDP1854A, CDP1854AC
Initialization and Controls
In the CDP1800-series microprocessor compatible mode,
the CDP1854A is configured to receive commands and send
status via the microprocessor data bus. The register
connected to the transmitter bus or the receiver bus is
determined by the RD/WR and RSEL inputs as follows:
TABLE 3. REGISTER SELECTION SUMMARY
RSEL
RD/WR
FUNCTION
Low
Low
Load Transmitter Holding Register from
Transmitter Bus
Low
High
Read Receiver Holding Register from
Receiver Bus
High
Low
Load Control Register from Transmitter
Bus
High
High
Read Status Register from Receiver Bus
In this mode the CDP1854A is compatible with a
bidirectional bus system. The receiver and transmitter buses
are connected to the bus. CDP1800-series microprocessor
I/O control output signals can be connected directly to the
CDP1854A inputs as shown in Figure 2. The CLEAR input is
pulsed, resetting the Control, Status, and Receiver Holding
Registers and setting SERIAL DATA OUT (SDO) high. The
Control Register is loaded from the Transmitter Bus in order
to determine the operating configuration for the UART. Data
is transferred from the Transmitter Bus inputs to the Control
Register during TPB when the UART is selected (CS1• CS2
• CS3 = 1) and the Control Register is designated (RSEL =
H, RD/WR = L). The CDP1854A also has a Status Register
which can be read onto the Receiver Bus (R BUS 0 - R BUS
7) in order to determine the status of the UART. Some of
these status bits are also available at separate terminals as
indicated in Table 2.
will be loaded from the Transmitter Holding Register and
data transmission will begin. If CTS is always low, the Transmitter Shift Register will be loaded on the first high-to-low
edge of the clock which occurs at least 1/2 clock period after
the trailing edge of TPB and transmission of a start bit will
occur 1/2 clock period later (see Figure 3). Parity (if programmed) and stop bit(s) will be transmitted following the
last data bit. If the word length selected is less than 8 bits,
the most significant unused bits in the transmitter shift register will not be transmitted.
One transmitter clock period after the Transmitter Shift Register is loaded from the Transmitter Holding Register, the
THRE signal will go low and an interrupt will occur (INT goes
low). The next character to be transmitted can then be
loaded into the Transmitter Holding Register for transmission
with its start bit immediately following the last stop bit of the
previous character. This cycle can be repeated until the last
character is transmitted, at which time a final THRE • TSRE
interrupt will occur. This interrupt signals the microprocessor
that TR can be turned off. This is done by reloading the original control byte in the Control Register with the TR bit 0,
thus terminating the REQUEST TO SEND (RTS) signal.
SERIAL DATA OUT (SDO) can be held low by setting the
BREAK bit in the Control Register (see Table 4). SDO is held
low until the BREAK bit is reset.
N0
N1
VSS
T CLOCK R CLOCK
RSEL
CS1
RTS
CS2
N2
CTS
VDD
MRD
TPB
CPU
CS3
RD/WR
TPB
ES
INT
INT
UART
CDP1854A
THRE
DA
EFX
EFX
EFX
PSI
PERIPHERAL
Description of Mode 1 Operation
CDP1800-Series Microprocessor
Compatible (Mode Input = VDD)
FE
Transmitter Operation
EFX
Before beginning to transmit, the TRANSMlT REQUEST
(TR) bit in the Control Register (see bit assignment, Table 4)
is set. Loading the Control Register with TR = 1 (bit 7 = high)
inhibits changing the other control bits. Therefore two loads
are required: one to format the UART, the second to set TR.
When TR has been set, a TRANSMlTTER HOLDING REGISTER EMPTY (THRE) interrupt will occur, signalling the
microprocessor that the Transmitter Holding Register is
empty and may be loaded. Setting TR also causes assertion
of a low-level on the REQUEST TO SEND (RTS) output to
the peripheral. It is not necessary to set TR for proper operation for the UART. If desired, it can be used to enable THRE
interrupts and to generate the RTS signal. The Transmitter
Holding Register is loaded from the bus by TPB during execution of an output instruction. The CDP1854A is selected
by CS1 • CS2 • CS3 = 1, and the Holding Register is
selected by RSEL = L and RD/WR = L. When the CLEAR
TO SEND (CTS) input, which can be connected to a peripheral device output, goes low, the Transmitter Shift Register
PE/OE
SDI
SDO
BUS
(8)
T BUS
R BUS
CLEAR
CLEAR
MODE
VDD
FIGURE 2. RECOMMENDED CDP1800-SERIES CONNECTION,
MODE 1 (NON-INTERRUPT DRIVEN SYSTEM)
Receiver Operation
The receive operation begins when a start bit is detected at
the SERlAL DATA IN (SDl) input. After detection of the first
high-to-low transition on the SDl line, a valid start bit is
verified by checking for a low-level input 7-1/2 receiver clock
periods later. When a valid start bit has been verified, the following data bits, parity bit (if programmed) and stop bit(s) are
shifted into the Receiver Shift Register by clock pulse 7-1/2
5-49
CDP1854A, CDP1854AC
in each bit time. The parity bit (if programmed) is checked
and receipt of a valid stop bit is verified. On count 7-1/2 of
the first stop bit, the received data is loaded into the
Receiver Holding Register. If the word length is less than 8
bits, zeros (low output level) are loaded into the unused most
significant bits. If DATA AVAILABLE (DA) has not been reset
by the time the Receiver Holding Register is loaded, the
OVERRUN ERROR (OE) status bit is set. One half clock
period later, the PARITY ERROR (PE) and FRAMlNG
ERROR (FE) status bits become valid for the character in
the Receiver Holding Register. At this time, the Data
Available status bit is also set and the DATA AVAILABLE
(DA) and INTERRUPT (INT) outputs go low, signalling the
microprocessor that a received character is ready. The
microprocessor responds by executing an input instruction.
The UART’s three-state bus drivers are enabled when the
UART is selected (CS1 • CS2 • CS3 = 1) and RD/WR =
high. Status can be read when RSEL = high. Data is read
when RSEL = Iow. When reading data, TPB latches data in
the microprocessor and resets DATA AVAILABLE (DA) in the
UART. The preceding sequence is repeated for each serial
character which is received from the peripheral.
Peripheral Interface
In addition to serial data in and out, four signals are provided
for communication with a peripheral. The REQUEST TO
SEND (RTS) output signal alerts the peripheral to get ready
to receive data. The CLEAR TO SEND (CTS) input signal is
the response, signalling that the peripheral is ready. The
EXTERNAL STATUS (ES) input latches a peripheral status
level, and the PERIPHERAL STATUS INTERRUPT (PSI)
input senses a status edge (high-to-low) and also generates
an interrupt. For example, the modem DATA CARRIER
DETECT line could be connected to the PSI input on the
UART in order to signal the microprocessor that
transmission failed because of loss of the carrier on the
communications line. The PSI and ES bits are stored in the
Status Register (see Table 2).
TABLE 4. CONTROL REGISTER BIT ASSIGNMENT
BIT
SIGNAL
7
6
5
4
3
2
1
0
TR
BREAK
IE
WLS2
WLS1
SBS
EPE
PI
BIT SIGNAL: FUNCTION
0
PARITY INHIBIT (PI): When set high parity generation and verification are inhibited and the PE Status bit is held low. If parity is
inhibited the stop bit(s) will immediately follow the last data bit on transmission, and EPE is ignored.
1
EVEN PARITY ENABLE (EPE): When set high, even parity is generated by the transmitter and checked by the receiver. When low,
odd parity is selected.
2
STOP BIT SELECT (SBS): See table below.
3
WORD LENGTH SELECT 1 (WLS1): See table below.
4
WORD LENGTH SELECT 2 (WLS2): See table below.
5
INTERRUPT ENABLE (lE): When set high THRE, DA, THRE • TSRE, CTS, and PSI interrupts are enabled (see Interrupt Conditions,
Table 1).
6
TRANSMlT BREAK (BREAK): Holds SDO low when set. Once the break bit in the control register has been set high, SDO will stay
low until the break bit is reset low and one of the following occurs: CLEAR goes low; CTS goes high; or a word is transmitted. (The
transmitted word will not be valid since there can be no start bit if SDO is already low. SDO can be set high without intermediate
transitions by transmitting a word consisting of all zeros).
7
TRANSMlT REQUEST (TR): When set high, RTS is set low and data transfer through the transmitter is initiated by the initial THRE
interrupt. (When loading the Control Register from the bus, this (TR) bit inhibits changing of other control flip-flops).
BIT 4
WLS2
BIT 3
WLS1
BIT 2
SBS
0
0
0
5 data bits, 1 stop bit
0
0
1
5 data bits, 1.5 stop bits
0
1
0
6 data bits, 1 stop bit
0
1
1
6 data bits, 2 stop bits
1
0
0
7 data bits, 1 stop bit
1
0
1
7 data bits, 2 stop bits
1
1
0
8 data bits, 1 stop bit
1
1
1
8 data bits, 2 stop bits
FUNCTION
5-50
CDP1854A, CDP1854AC
Dynamic Electrical Specifications
TA = -40oC to +85oC, VDD ±5%, tR, tF = 20ns, VIH = 0.7 VDD , VIL = 0.3 VDD , CL = 100pF,
(See Figure 3)
LIMITS
CDP1854A
PARAMETER
CDP1854AC
VDD
(V)
(NOTE 1)
TYP
(NOTE 2)
MAX
(NOTE 1)
TYP
(NOTE 2)
MAX
UNITS
5
250
310
250
310
ns
10
125
155
-
-
ns
5
100
125
100
125
ns
TRANSMITTER TIMING - MODE 1
Minimum Clock Period
tCC
Minimum Pulse Width
Clock Low Level
tCL
Clock High Level
10
75
100
-
-
ns
5
100
125
100
125
ns
10
75
100
-
-
ns
5
100
150
100
150
ns
10
50
75
-
-
ns
5
175
225
175
225
ns
10
90
150
-
-
ns
5
300
450
300
450
ns
tCH
TPB
tTT
Minimum Setup Time
TPB to Clock
tTC
Propagation Delay Time
Clock to Data Start Bit
tCD
TPB to THRE
10
150
225
-
-
ns
5
200
300
200
300
ns
10
100
150
-
-
ns
5
200
300
200
300
ns
10
100
150
-
-
ns
tTTH
Clock to THRE
tCTH
NOTES:
1. Typical values for TA = 25oC and nominal voltages.
2. Maximum limits of minimum characteristics are the values above which all devices function.
TRANSMITTER HOLDING
REGISTER LOADED
(NOTE 1)
TRANSMITTER SHIFT
REGISTER LOADED
(NOTE 2)
tCC
tCH
T CLOCK
1
2
tCL
3
4
5
6
7
14
15
16
THRE
2
3
4
tCD
tTC
WRITE (TPB)
(NOTE 3)
1
tTT
tCTH
tTTH
tCD
1ST DATA BIT
SDO
NOTES:
1. The holding register is loaded on the trailing edge of TPB.
2. The Transmitter Shift Register is loaded on the first high-to-low transition of the clock which occurs at least 1/2 clock period + tTC after
the trailing edge of TPB and transmission of a start bit occurs 1/2 clock period + tCD later.
3. Write is the overlap of TPB, CS1, and CS3 = 1 and CS3, RD/WR = 0.
FIGURE 3. TRANSMITTER TIMING DIAGRAM - MODE 1
5-51
CDP1854A, CDP1854AC
Dynamic Electrical Specifications
TA = -40oC to +85oC, VDD ±5%, t R, t F = 20ns, VIH = 0.7 VDD , VIL = 0.3 VDD , CL = 100pF,
(See Figure 4)
LIMITS
CDP1854A
PARAMETER
CDP1854AC
VDD
(V)
(NOTE 1)
TYP
(NOTE 2)
MAX
(NOTE 1)
TYP
(NOTE 2)
MAX
UNITS
5
250
310
250
310
ns
10
125
155
-
-
ns
5
100
125
100
125
ns
10
75
100
-
-
ns
5
100
125
100
125
ns
10
75
100
-
-
ns
5
100
150
100
150
ns
10
50
75
-
-
ns
5
100
150
100
150
ns
10
50
75
-
-
ns
5
220
325
220
325
ns
10
110
175
-
-
ns
5
220
325
220
325
ns
10
110
175
-
-
ns
5
210
300
210
300
ns
10
105
150
-
-
ns
5
240
375
240
375
ns
10
120
175
-
-
ns
5
200
300
200
300
ns
10
100
150
-
-
ns
RECEIVER TIMING - MODE 1
Minimum Clock Period
tCC
Minimum Pulse Width
Clock Low Level
Clock High Level
TPB
tCL
tCH
tTT
Minimum Setup Time
Data Start Bit to Clock
tDC
Propagation Delay Time
TPB to DATA AVAILABLE
Clock to DATA AVAILABLE
Clock to Overrun Error
Clock to Parity Error
Clock to Framing Error
tTDA
tCDA
tCOE
tCPE
tCFE
NOTES:
1. Typical values for TA = 25oC and nominal voltages.
2. Maximum limits of minimum characteristics are the values above which all devices function.
5-52
CDP1854A, CDP1854AC
CLOCK 7 1/2
SAMPLE
tCC
tCH
R CLOCK
CLOCK 7 1/2 LOAD
HOLDING REGISTER
tCL
1
2
3
4
5
6
7
16
1
2
3
4
5
6
7
8
9
tDC
(NOTE 1)
START BIT
SDI
PARITY
STOP BIT 1
tCDA
tTDA
DA
READ
(NOTE 2)
tTT
TPB
tCOE
OE
(NOTE 3)
tCPE
PE
(NOTE 3)
tCFE
FE
NOTES:
1. If a start bit occurs at a time less than tDC before a high-to-low transition of the clock, the start bit may not be recognized until the next
high-to-low transition of the clock. The start bit may be completely asynchronous with the clock.
2. Read is the overlap of CS1, CS3, RD/WR = 1 and CS2 = 0. If a pending DA has not been cleared by a read of the Receiver Holding
Register by the time a new word is loaded into the Receiver Holding Register, the OE signal will come true.
3. OE and PE share terminal 15 and are also available as two separate bits in the status register.
FIGURE 4. MODE 1 RECEIVER TIMING DIAGRAM
tTT
TPB
(NOTE 1)
tRSW
tWRS
tDW
tWD
RSEL
T BUS 0T BUS 7
CS3, CS1
(NOTE 1)
RD/WR, CS2
(NOTE 1)
NOTE:
1. Write is the overlap of TPB, CS1, CS3 = 1 and CS2, RD/WR = 0.
FIGURE 5. MODE 1 CPU INTERFACE (WRITE) TIMING DIAGRAM
5-53
CDP1854A, CDP1854AC
Dynamic Electrical Specifications
TA = -40oC to +85oC, VDD ±5%, t R, t F = 20ns, VIH = 0.7 VDD , VIL = 0.3 VDD , CL = 100pF,
(See Figure 5)
LIMITS
CDP1854A
PARAMETER
CDP1854AC
VDD
(V)
(NOTE 1)
TYP
(NOTE 2)
MAX
(NOTE 1)
TYP
(NOTE 2)
MAX
UNITS
5
100
150
100
150
ns
10
50
75
-
-
ns
5
50
75
50
75
ns
10
25
40
-
-
ns
CPU INTERFACE - WRITE TIMING - MODE 1
Minimum Pulse Width
TPB
tTT
Minimum Setup Time
RSEL to Write
tRSW
Data to Write
tDW
Minimum Hold Time
RSEL after Write
tWRS
Data after Write
tWD
5
-30
0
-30
0
ns
10
-15
0
-
-
ns
5
50
75
50
75
ns
10
25
40
-
-
ns
5
75
125
75
125
ns
10
40
60
-
-
ns
NOTES:
1. Typical values for TA = 25oC and nominal voltages.
2. Maximum limits of minimum characteristics are the values above which all devices function.
Dynamic Electrical Specifications
TA = -40oC to +85oC, VDD ±5%, t R, t F = 20ns, VIH = 0.7 VDD , VIL = 0.3 VDD , CL = 100pF,
(See Figure 6)
LIMITS
CDP1854A
PARAMETER
VDD
(V)
CDP1854AC
MIN
(NOTE 1)
TYP
(NOTE 2)
MAX
MIN
(NOTE 1)
TYP
(NOTE 2)
MAX
UNITS
CPU INTERFACE - READ TIMING - MODE 1
Minimum Pulse Width
TPB
Minimum Setup Time
RSEL to TPB
Minimum Hold Time
RSEL after TPB
Read to Data Access Time
Read to Data Valid Time
RESEL to Data Valid Time
Hold Time
Data after Read
tTT
tRST
tTRS
tRDDA
tRDV
tRSDV
tRDH
5
-
100
150
-
100
150
ns
10
-
50
75
-
-
-
ns
5
-
50
75
-
50
75
ns
10
-
25
40
-
-
-
ns
5
-
50
75
-
50
75
ns
10
-
25
40
-
-
-
ns
ns
5
-
200
300
-
200
300
10
-
100
150
-
-
-
ns
5
-
200
300
-
200
300
ns
10
-
100
150
-
-
-
5
-
150
225
-
150
225
ns
10
-
75
125
-
-
-
ns
5
50
150
-
50
150
-
ns
10
25
75
-
-
-
-
ns
NOTES:
1. Typical values for TA = 25oC and nominal voltages.
2. Maximum limits of minimum characteristics are the values above which all devices function.
5-54
CDP1854A, CDP1854AC
tTT
TPB
tTRS
tRST
RSEL
tRSDV
R BUS 0R BUS 7
tRDDA
tRDH
tRDV
RD/WR, CS1, CS3
(NOTE 1)
CS2
NOTE:
1. Read is the overlap of CS1, CS3, RD/WR = 1 and CS2 = 0.
FIGURE 6. MODE 1 CPU INTERFACE (READ) TIMING DIAGRAM
Mode Input Low (Mode = 0)
1 = VDD
2, 3 = VSS
21 = MR
R CLOCK
T CLOCK
40
17
SDO
TRANSMITTER
TIMING AND
CONTROL
RECEIVER
SHIFT
REGISTER
RECEIVER
TIMING AND
CONTROL
TRANSMITTER
SHIFT
REGISTER
7
8
9 10 11 12
R BUS 4
R BUS 3
RECEIVER BUS
TRANSMITTER BUS
TRANSMITTER SECTION
RECEIVER SECTION
FIGURE 7. MODE 0 BLOCK DIAGRAM (INDUSTRY STANDARD COMPATIBLE)
5-55
R BUS 0
6
R BUS 1
5
R BUS 5
DAR
4
R BUS 6
DA
FE
OE
PE
TSRE
SFD
THRE
22 24 13 14 15 19
CRL
THREE-STATE
DRIVERS
18
R BUS 2
STATUS
REGISTER
16
R BUS 7
34
WLS2
EPE
WLS1
PI
23
THRL
SBS
T BUS 7
T BUS 6
T BUS 5
T BUS 4
35 36 39 38 37
T BUS 3
26 27 28 29 30 31 32 33
T BUS 2
CONTROL
REGISTER
T BUS 1
TRANSMITTER
HOLDING REGISTER
T BUS 0
SDI
RECEIVER
HOLDING
REGISTER
PARITY
GEN
25
20
RRD
CDP1854A, CDP1854AC
Functional Definitions for CDP1854A
Terminals Standard Mode 0
DATA AVAILABLE (DA):
SIGNAL: FUNCTION
A high-level voltage at this output indicates that an entire
character has been received and transferred to the Receiver
Holding Register.
VDD:
SERIAL DATA IN (SDl):
Positive supply voltage.
Serial data received at this input enters the receiver shift
register at a point determined by the character length. A
high-level voltage must be present when data is not being
received.
MODE SELECT (MODE):
A low-level voltage at this input selects Standard Mode 0
Operation.
VSS:
MASTER RESET (MR):
A high-level voltage at this input resets the Receiver Holding
Register, Control Register, and Status Register, and sets the
serial data output high.
Ground.
RECEIVER REGISTER DISCONNECT (RRD):
A high-level voltage applied to this input disconnects the
Receiver Holding Register from the Receiver Bus.
TRANSMlTTER HOLDING REGISTER EMPTY (THRE):
Receiver parallel data outputs.
A high-level voltage at this output indicates that the Transmitter Holding Register has transferred its contents to the
Transmitter Shift Register and may be reloaded with a new
character.
PARITY ERROR (PE):
TRANSMlTTER HOLDING REGISTER LOAD (THRL):
A high-level voltage at this output indicates that the received
parity does not compare to that programmed by the EVEN
PARITY ENABLE (EPE) control. This output is updated each
time a character is transferred to the Receiver Holding Register. PE lines from a number of arrays can be bused
together since an output disconnect capability is provided by
the STATUS FLAG DISCONNECT (SFD) line.
A low-level voltage applied to this input enters the character
on the bus into the Transmitter Holding Register. Data is
latched on the trailing edge of this signal.
RECEIVER BUS (R BUS 7 - R BUS 0):
FRAMING ERROR (FE):
A high-level voltage at this output indicates that the received
character has no valid stop bit, i.e., the bit following the parity
bit (if programmed) is not a high-level voltage. This output is
updated each time a character is transferred to the Receiver
Holding Register. FE lines from a number of arrays can be
bused together since an output disconnect capability is provided by the STATUS FLAG DISCONNECT (SFD) line.
OVERRUN ERROR (OE):
A high-level voltage at this output indicates that the DATA
AVAILABLE (DA) flag was not reset before the next character was transferred to the Receiver Holding Register. OE
lines from a number of arrays can be bused together since
an output disconnect capability is provided by the STATUS
FLAG DISCONNECT (SFD) line.
STATUS FLAG DISCONNECT (SFD):
A high-level voltage applied to this input disables the threestate output drivers for PE, FE, OE, DA, and THRE, allowing
these status outputs to be bus connected.
RECEIVER CLOCK (RCLOCK):
Clock input with a frequency 16 times the desired receiver
shift rate.
DATA AVAILABLE RESET (DAR):
A low-level voltage applied to this input resets the DA flipflop.
TRANSMlTTER SHIFT REGISTER EMPTY (TSRE):
A high-level voltage at this output indicates that the Transmitter Shift Register has completed serial transmission of a full
character including stop bit(s). It remains at this level until
the start of transmission of the next character.
SERIAL DATA OUTPUT (SDO):
The contents of the Transmitter Shift Register (start bit, data
bits, parity bit, and stop bit(s)) are serially shifted out on this
output. When no character is being transmitted, a high-level
is maintained. Start of transmission is defined as the
transition of the start bit from a high-level to a low-level
output voltage.
TRANSMlTTER BUS (T BUS 0 - T BUS 7):
Transmitter parallel data inputs.
CONTROL REGISTER LOAD (CRL):
A high-level voltage at this input loads the Control Register
with the control bits (PI, EPE, SBS, WLS1, WLS2). This line
may be strobed or hardwired to a high-level input voltage.
PARITY INHIBIT (PI):
A high-level voltage at this input inhibits the parity generation
and verification circuits and will clamp the PE output low. If
parity is inhibited the stop bit(s) will immediately follow the
last data bit on transmission.
STOP BIT SELECT (SBS):
This input selects the number of stop bits to be transmitted
after the parity bit. A high-level selects two stop bits, a lowlevel selects one stop bit. Selection of two stop bits with five
data bits programmed selects 1.5 stop bits.
5-56
CDP1854A, CDP1854AC
VDD) instead of being dynamically set and CRL may be
hardwired to VDD. The CDP1854A is then ready for
transmitter and/or receiver operation.
T CLOCK R CLOCK
TPA
PI
DAR
Transmitter Operation
SBS
SCI
WLS1
RRD
WLS2
CPU
CDP1800
EPE
TPB
N0
THRL
UART
CDP1854A
TSRE
EF3
DMAI
DA
SDI
SDO
BUS
(8)
T BUS
R BUS
CLEAR
MR
MODE
VSS
FIGURE 8. MODE 0 CONNECTION DIAGRAM
WORD LENGTH SELECT 2 (WLS2):
WORD LENGTH SELECT 1 (WLS1):
These two inputs select the character length (exclusive of
parity) as follows:
WLS2
WLS1
WORD LENGTH
Low
Low
5 Bits
Low
High
6 Bits
High
Low
7 Bits
High
High
8 Bits
For the transmitter timing diagram refer to Figure 10. At the
beginning of a typical transmitting sequence the Transmitter
Holding Register is empty (THRE is HIGH). A character is
transferred from the transmitter bus to the Transmitter Holding Register by applying a low pulse to the TRANSMITTER
HOLDING REGISTER LOAD (THRL) input causing THRE to
go low. If the Transmitter Shift Register is empty (TSRE is
HIGH) and the clock is low, on the next high-to-low transition
of the clock the character is loaded into the Transmitter Shift
Register preceded by a start bit. Serial data transmission
begins 1/2 clock period later with a start bit and 5-8 data bits
followed by the parity bit (if programmed) and stop bit(s). The
THRE output signal goes high 1/2 clock period later on the
high-to-low transition of the clock. When THRE goes high,
another character can be loaded into the Transmitter Holding
Register for transmission beginning with a start bit immediately following the last stop bit of the previous character. This
process is repeated until all characters have been transmitted. When transmission is complete, THRE and Transmitter
Shift Register Empty (TSRE) will both be high. The format of
serial data is shown in Figure 12. Duration of each serial output data bit is determined by the transmitter clock frequency
(fCLOCK) and will be 16/f CLOCK.
Receiver Operation
EVEN PARITY ENABLE (EPE):
A high-level voltage at this input selects even parity to be
generated by the transmitter and checked by the receiver. A
low-level input selects odd parity.
TRANSMITTER CLOCK (TCLOCK):
Clock input with a frequency 16 times the desired transmitter
shift rate.
Description of Standard Mode 0 Operation
(Mode Input = VSS)
Initialization and Controls
The MASTER RESET (MR) input is pulsed, resetting the
Control, Status, and Receiver Holding Registers and setting
the SERlAL DATA OUTPUT (SDO) signal high. Timing is
generated from the clock inputs, Transmitter Clock
(TCLOCK) and Receiver Clock (RCLOCK), at a frequency
equal to 16 times the serial data bit rate. When the receiver
data input rate and the transmitter data output rate are the
same, the TCLOCK and RCLOCK inputs may be connected
together. The CONTROL REGISTER LOAD (CRL) input is
pulsed to store the control inputs PARITY INHIBIT (PI),
EVEN PARITY ENABLE (EPE), STOP BIT SELECT (SBS),
and WORD LENGTH SELECTs (WLS1 and WLS2). These
inputs may be hardwired to the proper voltage levels (VSS or
The receive operation begins when a start bit is detected at
the SERIAL DATA IN (SDl) input. After the detection of a
high-to-low transition on the SD line, a divide-by-16 counter
is enabled and a valid start bit is verified by checking for a
low-level input 7-1/2 receiver clock periods later. When a
valid start bit has been verified, the following data bits, parity
bit (if programmed), and stop bit(s) are shifted into the
Receiver Shift Register at clock pulse 7-1/2 in each bit time.
If programmed, the parity bit is checked, and receipt of a
valid stop bit is verified. On count 7-1/2 of the first stop bit,
the received data is loaded into the Receiver Holding Register. If the word length is less than 8 bits, zeros (low output
voltage level) are loaded into the unused most significant
bits. If DATA AVAILABLE (DA) has not been reset by the time
the Receiver Holding Register is loaded, the OVERRUN
ERROR (OE) signal is raised. One-half clock period later,
the PARITY ERROR (PE) and FRAMlNG ERROR (FE) signals become valid for the character in the Receiver Holding
Register. The DA signal is also raised at this time. The threestate output drivers for DA, OE, PE and FE are enabled
when STATUS FLAG DISCONNECT (SFD) is low. When
RECEIVER REGISTER DISCONNECT (RRD) goes low, the
receiver bus three-state output drivers are enabled and data
is available at the RECEIVER BUS (R BUS 0 - R BUS 7) outputs. Applying a negative pulse to the DATA AVAILABLE
RESET (DAR) resets DA. The preceding sequence of operation is repeated for each serial character received. A receiver
timing diagram is shown in Figure 11.
5-57
CDP1854A, CDP1854AC
Dynamic Electrical Specifications
TA = -40oC to +85oC, VDD ±5%, t R, t F = 20ns, VIH = 0.7 VDD , VIL = 0.3 VDD , CL = 100pF,
(See Figure 9)
LIMITS
CDP1854A
PARAMETER
CDP1854AC
VDD
(V)
(NOTE 1)
TYP
(NOTE 2)
MAX
(NOTE 1)
TYP
(NOTE 2)
MAX
UNITS
INTERFACE TIMING - MODE 0
Minimum Pulse Width
CRL
tCRL
MR
tMR
Minimum Setup Time
Control Word to CRL
tCWC
Minimum Hold Time
Control Word after CRL
tCCW
Propagation Delay Time
SFD High to SOD
tSFDH
SFD Low to SOD
tSFDL
RRD High to Receiver Register
High Impedance
tRRDH
RRD Low to Receiver Register Active
tRRDL
5
100
150
100
150
ns
10
50
75
-
-
ns
5
200
400
200
400
ns
10
100
200
-
-
ns
5
40
80
40
80
ns
10
20
50
-
-
ns
5
100
150
100
150
ns
10
50
75
-
-
ns
5
200
300
200
300
ns
10
100
150
-
-
ns
5
75
120
75
120
ns
10
40
60
-
-
ns
5
200
300
200
300
ns
10
100
150
-
-
ns
5
100
150
100
150
ns
10
50
75
-
-
ns
NOTES:
1. Typical values for TA = 25oC and nominal voltages.
2. Maximum limits of minimum characteristics are the values above which all devices function.
CONTROL INPUT WORD TIMING
CONTROL WORD INPUT
tCWC
tCCW
CRL
tCRL
STATUS OUTPUT TIMING
STATUS OUTPUTS
tSFDH
tSFDL
SFD
RECEIVER REGISTER DISCONNECT TIMING
R BUS 0
R BUS 7
tRRDH
tRRDL
RRD
FIGURE 9. MODE 0 INTERFACE TIMING DIAGRAM
5-58
CDP1854A, CDP1854AC
Dynamic Electrical Specifications
TA = -40oC to +85oC, VDD ±5%, t R, t F = 20ns, VIH = 0.7 VDD , VIL = 0.3 VDD , CL = 100pF,
(See Figure 10)
LIMITS
CDP1854A
PARAMETER
CDP1854AC
VDD
(V)
(NOTE 1)
TYP
(NOTE 2)
MAX
(NOTE 1)
TYP
(NOTE 2)
MAX
UNITS
5
250
310
250
310
ns
10
125
155
-
-
ns
5
100
125
100
125
ns
10
75
100
-
-
ns
5
100
125
100
125
ns
10
75
100
-
-
ns
5
100
150
100
150
ns
10
50
75
-
-
ns
5
175
275
175
275
ns
10
90
150
-
-
ns
5
20
50
20
50
ns
10
0
40
-
-
ns
5
80
120
80
120
ns
10
40
60
-
-
ns
5
300
450
300
450
ns
10
150
225
-
-
ns
5
200
300
200
300
ns
10
100
150
-
-
ns
5
200
300
200
300
ns
10
100
150
-
-
ns
5
200
300
200
300
ns
10
100
150
-
-
ns
TRANSMITTER TIMING - MODE 0
Minimum Clock Period
tCC
Minimum Pulse Width
Clock Low Level
Clock High Level
THRL
tCL
tCH
tTHTH
Minimum Setup Time
THRL to Clock
Data to THRL
tTHC
tDT
Minimum Hold Time
Data after THRL
tTD
Propagation Delay Time
Clock to Data Start Bit
Clock to THRE
THRL to THRE
Clock to TSRE
tCD
tCT
tTTHR
tTTS
NOTES:
1. Typical values for TA = 25oC and nominal voltages.
2. Maximum limits of minimum characteristics are the values above which all devices function.
5-59
CDP1854A, CDP1854AC
Dynamic Electrical Specifications
TA = -40oC to +85oC, VDD ±5%, t R, t F = 20ns, VIH = 0.7 VDD , VIL = 0.3 VDD , CL = 100pF,
(See Figure 11)
LIMITS
CDP1854A
PARAMETER
CDP1854AC
VDD
(V)
(NOTE 1)
TYP
(NOTE 2)
MAX
(NOTE 1)
TYP
(NOTE 2)
MAX
UNITS
5
250
310
250
310
ns
10
125
155
-
-
ns
5
100
125
100
125
ns
10
75
100
-
-
ns
5
100
125
100
125
ns
10
75
100
-
-
ns
5
50
75
50
75
ns
10
25
40
-
-
ns
5
100
150
100
150
ns
10
50
75
-
-
ns
5
150
225
150
225
ns
10
75
125
-
-
ns
5
225
325
225
325
ns
10
110
175
-
-
ns
5
225
325
225
325
ns
10
110
175
-
-
ns
5
210
300
210
300
ns
10
100
150
-
-
ns
5
240
375
240
375
ns
10
120
175
-
-
ns
5
200
300
200
300
ns
10
100
150
-
-
ns
RECEIVER TIMING - MODE 0
Minimum Clock Period
tCC
Minimum Pulse Width
Clock Low Level
Clock High Level
DATA AVAILABLE RESET
tCL
tCH
tDD
Minimum Setup Time
Data Start Bit to Clock
tDC
Propagation Delay Time
DATA AVAILABLE RESET to
Data Available
tDDA
Clock to Data Valid
tCDV
Clock to Data Available
Clock to Overrun Error
Clock to Parity Error
Clock to Framing Error
tCDA
tCOE
tCPE
tCFE
NOTES:
1. Typical values for TA = 25oC and nominal voltages.
2. Maximum limits of minimum characteristics are the values above which all devices function.
5-60
CDP1854A, CDP1854AC
TRANSMITTER HOLDING
REGISTER LOADED
(NOTE 1)
tCC
tCH
TRANSMITTER SHIFT
REGISTER LOADED
(NOTE 2)
tCL
T CLOCK
1
2
3
4
5
6
7
14
15
16
1
2
3
tTHC
THRL
tTHTH
tCD
tCD
1ST DATA BIT
SDO
tTTHR
tCT
THRE
tTTS
TSRE
tDT
T BUS 0
T BUS 7
tTD
DATA
NOTES:
1. The holding register is loaded on the trailing edge of THRL.
2. The transmitter shift register, if empty, is loaded on the first high-to-low transition of the clock which occurs at least 1/2 clock period + tTHC
after the trailing edge of THRL and transmission of a start bit occurs 1/2 clock period + tCD later.
FIGURE 10. MODE 0 TRANSMITTER TIMING DIAGRAM
CLOCK 7 1/2
SAMPLE
tCC
tCH
R CLOCK
CLOCK 7 1/2 LOAD
HOLDING REGISTER
tCL
1
2
3
4
5
6
7
16
1
2
3
4
5
6
7
8
9
tDC
(NOTE 1)
SDI
START BIT
PARITY
STOP BIT 1
tCDV
R BUS 0 R BUS 7
DA
tDDA
tCDA
DAR
tCOE
tDD
OE
(NOTE 2)
tCPE
PE
tCFE
FE
NOTES:
1. If a start bit occurs at a time less than tDC before a high-to-low transition of the clock, the start bit may not be recognized until the next
high-to-low transition of the clock. The start bit may be completely asynchronous with the clock.
2. If a pending DA has not been cleared by a read of the receiver holding register by the time a new word is loaded into the receiver holding
register, the OE signal will come true.
FIGURE 11. MODE 0 RECEIVER TIMING DIAGRAM
16 / fCLOCK
NEXT DATA WORD
5 - 8 DATA BITS
START BIT
DATA
LSB
STOP BITS 1, 1-1/2 OR 2
DATA
MSB
PARITY BIT
FIGURE 12. SERIAL DATA WORD FORMAT
5-61
CDP1854A, CDP1854AC
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5-62
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