CET CEP830G N-channel enhancement mode field effect transistor Datasheet

CEP830G/CEB830G
CEF830G
N-Channel Enhancement Mode Field Effect Transistor
PRELIMINARY
FEATURES
Type
VDSS
RDS(ON)
ID
@VGS
CEP830G
500V
1.5Ω
5A
10V
CEB830G
500V
1.5Ω
5A
10V
CEF830G
500V
1.5Ω
5A e
10V
D
Super high dense cell design for extremely low RDS(ON).
High power and current handing capability.
Lead free product is acquired.
G
D
G
D
S
G
S
CEB SERIES
TO-263(DD-PAK)
G
CEP SERIES
TO-220
ABSOLUTE MAXIMUM RATINGS
Parameter
D
S
Tc = 25 C unless otherwise noted
Limit
Symbol
TO-220/263
Drain-Source Voltage
VDS
Gate-Source Voltage
VGS
Drain Current-Continuous
Drain Current-Pulsed
S
CEF SERIES
TO-220F
ID
IDM
a
Maximum Power Dissipation @ TC = 25 C
f
PD
- Derate above 25 C
TO-220F
500
Units
V
±30
V
A
5
5
20
20
83
42
W
0.33
W/ C
0.66
e
e
A
TJ,Tstg
-55 to 150
C
Symbol
Limit
Units
Operating and Store Temperature Range
Thermal Characteristics
Parameter
Thermal Resistance, Junction-to-Case
RθJC
1.5
3.6
C/W
Thermal Resistance, Junction-to-Ambient
RθJA
62.5
65
C/W
This is preliminary information on a new product in development now .
Details are subject to change without notice .
1
Rev 1. 2009.Nov.
http://www.cetsemi.com
CEP830G/CEB830G
CEF830G
Electrical Characteristics
Parameter
Tc = 25 C unless otherwise noted
Symbol
Test Condition
Min
Drain-Source Breakdown Voltage
BVDSS
VGS = 0V, ID = 250µA
500
Zero Gate Voltage Drain Current
IDSS
Gate Body Leakage Current, Forward
Gate Body Leakage Current, Reverse
Typ
Max
Units
VDS = 500V, VGS = 0V
1
µA
IGSSF
VGS = 30V, VDS = 0V
100
nA
IGSSR
VGS = -30V, VDS = 0V
-100
nA
4
V
1.5
Ω
Off Characteristics
V
On Characteristics b
Gate Threshold Voltage
Static Drain-Source
On-Resistance
Forward Transconductance
Dynamic Characteristics
VGS(th)
VGS = VDS, ID = 250µA
2.5
RDS(on)
VGS = 10V, ID = 2.5A
1.2
gFS
VDS = 50V, ID = 4.8A
7
S
595
pF
90
pF
20
pF
c
Input Capacitance
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance
Crss
VDS = 25V, VGS = 0V,
f = 1.0 MHz
Switching Characteristics c
Turn-On Delay Time
td(on)
Turn-On Rise Time
tr
Turn-Off Delay Time
td(off)
VDD = 250V, ID = 5A,
VGS = 10V, RGEN = 14Ω
15
30
ns
8
16
ns
30
60
ns
Turn-Off Fall Time
tf
7
14
ns
Total Gate Charge
Qg
13
17
nC
Gate-Source Charge
Qgs
Gate-Drain Charge
Qgd
VDS = 400V, ID = 5A,
VGS = 10V
2.5
nC
5
nC
Drain-Source Diode Characteristics and Maximun Ratings
Drain-Source Diode Forward Current
Drain-Source Diode Forward Voltage
IS f
b
VSD
VGS = 0V, IS = 3.1A
Notes :
a.Repetitive Rating : Pulse width limited by maximum junction temperature .
b.Pulse Test : Pulse Width < 300µs, Duty Cycle < 2% .
c.Guaranteed by design, not subject to production testing.
d.Limited only by maximum temperature allowed .
e.Pulse width limited by safe operating area .
f.Full package IS(max) = 4A .
2
5
A
1.6
V
CEP830G/CEB830G
CEF830G
12
VGS=10,9,8,7V
10
8
ID, Drain Current (A)
ID, Drain Current (A)
12
VGS=6V
6
4
VGS=4V
2
0
0
2
4
6
8
10
TJ=125C
1
2
-55 C
3
4
5
6
Figure 1. Output Characteristics
Figure 2. Transfer Characteristics
RDS(ON), Normalized
RDS(ON), On-Resistance(Ohms)
450
300
Coss
150
Crss
0
5
10
15
20
25
2.2
1.9
ID=2.5A
VGS=10V
1.6
1.3
1.0
0.7
0.4
-100
-50
0
50
100
150
200
VDS, Drain-to-Source Voltage (V)
TJ, Junction Temperature( C)
Figure 3. Capacitance
Figure 4. On-Resistance Variation
with Temperature
VDS=VGS
ID=250µA
IS, Source-drain current (A)
C, Capacitance (pF)
VTH, Normalized
Gate-Source Threshold Voltage
25 C
2
VGS, Gate-to-Source Voltage (V)
Ciss
1.1
1.0
0.9
0.8
0.7
0.6
-50
4
VDS, Drain-to-Source Voltage (V)
600
1.2
6
12
750
1.3
8
0
900
0
10
-25
0
25
50
75
100
125
10
0
10
-1
10
-2
VGS=0V
0.4
150
0.6
0.8
1.0
1.2
TJ, Junction Temperature( C)
VSD, Body Diode Forward Voltage (V)
Figure 5. Gate Threshold Variation
with Temperature
Figure 6. Body Diode Forward Voltage
Variation with Source Current
3
10
VDS=400V
ID=5A
RDS(ON)Limit
8
ID, Drain Current (A)
VGS, Gate to Source Voltage (V)
CEP830G/CEB830G
CEF830G
6
4
2
0
0
3
6
9
12
10
1
10
0
DC
10
15
100ms
1ms
10ms
TC=25 C
TJ=150 C
Single Pulse
-1
10
0
10
1
10
2
10
Qg, Total Gate Charge (nC)
VDS, Drain-Source Voltage (V)
Figure 7. Gate Charge
Figure 8. Maximum Safe
Operating Area
VDD
t on
RL
V IN
D
VGS
RGEN
toff
tr
td(on)
td(off)
tf
90%
90%
VOUT
VOUT
10%
INVERTED
10%
G
90%
S
VIN
50%
50%
10%
PULSE WIDTH
Figure 10. Switching Waveforms
Figure 9. Switching Test Circuit
r(t),Normalized Effective
Transient Thermal Impedance
10
0
D=0.5
10
0.2
0.1
-1
0.05
0.02
0.01
10
10
PDM
t1
Single Pulse
-2
1. RθJC (t)=r (t) * RθJC
2. RθJC=See Datasheet
3. TJM-TC = P* RθJC (t)
4. Duty Cycle, D=t1/t2
-3
10
t2
-5
10
-4
10
-3
10
-2
10
-1
Square Wave Pulse Duration (sec)
Figure 11. Normalized Thermal Transient Impedance Curve
4
10
0
10
1
3
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