ETC CL7128ATC100-4

CL7128A
CL7128AE
Laser Processed Logic Device Family
u Laser Processed Logic Device (LPLD™) technology offers
the ultimate combination of performance, flexibility, and
low cost
u Functionally, architecturally, and electrically compatible
with industry-standard Altera® MAX® 7000
u High Density
-
2,500 Usable gates
-
128 Macrocells
-
100 Maximum user I/O pins
u Laser fuse technology provides very fast, dense
interconnect routing
u Low current consumption
u Supports 3.3 volt operation
u Alpha particle immune
CL7000 Product Family Overview
CL7128A
CL7128AE
CL7256A
CL7256AE
CL7512A
2,500
5,000
10,000
128
256
512
Logic array Blocks
8
16
32
Max user I/O pins
100
164
212
-4, -5, -6, -7, -10, -12
-4, -5, -6, -7, -10, -12
-6, -7, -10, -12
84-Pin PLCC
100-Pin TQFP
100-Pin TQFP
100-Pin BGA
144-Pin TQFP
208-Pin PQFP
100-Pin BGA
144-Pin TQFP
256-Pin BGA
144-Pin TQFP
208-Pin PQFP
Feature
Useable Gates
Macrocells
Speed Grades
Packages
256-Pin BGA
7KA tbl 01A
December 2000
Page 1
CL7128A and CL7128AE Laser Processed Logic Devices
Description
The Clear Logic CL7000 Laser Processed Logic Device (LPLD®)
family offers the ultimate combination of performance,
flexibility, and cost. This family is a system level second source
to Altera MAX® 7000A products. For designs not requiring insystem reprogrammability, design verification can be performed
using the programmable Altera devices, and Clear Logic LPLDs
can be used for low cost, high volume production.
Clear Logic’s innovative laser-based technology eliminates NRE
costs, test vector development, ordering minimums and long lead
times. No re-simulation or re-layout is required, as the device
uses a cell-based, PLD-like architecture. Clear Logic’s NoFault®
technology ensures complete test coverage through the use of
specialized testing modes which are transparent to the user.
The Clear Logic CL7000 Laser Processed Logic Device family is
based upon a large array of macrocells. Each macrocell
contains a logic array with five product terms, a product-term
select matrix, and a configurable register. A group of sixteen
macrocells forms a block.
Laser-configured metal fuses
implement logical functions and control signal routing.
Laser configuration provides reduced cost and enhanced
performance. These inherent performance benefits include
extremely consistent propagation delays, reduced power
consumption, and improved immunity to noise and upset events.
Additional
Information
For further information on designing with the CL7000 LPLD
family, please consult the following documents:
u AN-01: Requesting a First Article. This document provides
instructions on how to submit a bitstream file for
generation of first articles.
u AN-02: Clear Logic Packaging Guide. This document provides
specifications and drawings for packages used by the CL7000
family.
u AN-09: CL7000 Technology White Paper. This document
outlines the technologies employed by the CL7000 LPLD
family.
u AN-10: Calculating CL7000 Power Consumption. This
document provides guidelines for calculating power
consumption based on design characteristics.
u AN-11: CL7000 Test Methodology. This document discribes
how Clear Logic provides 100% stuck-at fault coverage.
Page 2
CL7128A and CL7128AE Laser Processed Logic Devices
u AN-12: CL7000 LPLD Timing and Function Compatability.
This document shows how a seamless conversion from CPLD
to ASIC can be achieve with no additional engineering with
Clear Logic.
Block Diagram
INPUT/GCLK1
INPUT/OE2/GCLK2
INPUT/OE1
INPUT/GCLRn
6 Output Enables
6 to 16
3 to 16 I/O Pins
I/O
Control
Block
6 to 16
6 - 10 Output Enables
Block A
Macrocells
1 - 16
Block B
36
36
6 to 16
Block C
Macrocells
33 - 48
Block D
36
16
6 to 16
6
6 to 16
3 to 16 I/O Pins
I/O
Control
Block
6 to 16
Block E
Macrocells
65 - 80
36
16
6 to 16
6
I/O
Control
Block
36
Macrocells
49 - 64
6 to 16
6 to 16
I/O
Control
Block
3 to 16 I/O Pins
16
6 to 16
6
Block F
36
Macrocells
81 - 96
6 to 16
6 to 16
I/O
Control
Block
3 to 16 I/O Pins
16
6 to 16
6
6 to 16
3 to 16 I/O Pins
3 to 16 I/O Pins
6
Laser-Configured Interconnect Array (LIA)
I/O
Control
Block
I/O
Control
Block
6 to 16
6 to 16
6 to 16
3 to 16 I/O Pins
6 to 16
16
16
6
Macrocells
17 - 32
6 to 16
6 to 16
Block H
Block G
Macrocells
97 - 112
36
16
6 to 16
36
Macrocells
113 - 128
6 to 16
6 to 16
I/O
Control
Block
3 to 16 I/O Pins
16
6 to 16
7128A drw 01
Page 3
CL7128A and CL7128AE Laser Processed Logic Devices
Macrocell Diagram
Global Global
Clear Clocks
Local Array
Fast Input
Select
2
Configurable
Register
Parallel Logic
Expanders
Register
Bypass
D
Clock/
Enable
Select
Product
Term
Select
Matrix
Clear
Select
Shared Logic
Expanders
36 Signals
from LIA
Page 4
16 Expander
Product Terms
from
I/O pin
PRN
to I/O
Control
Block
Q
ENA
CLRN
VCC
to LIA
7K drw 01
CL7128A and CL7128AE Laser Processed Logic Devices
Pin Configuration
Pin Name
84 pin PLCC 100 pin TQFP 100 pin FBGA 144 pin TQFP
256 pin FBGA
INPUT/GCLK1
83
87
A6
125
D9
INPUT/GCLRn
1
89
B5
127
E8
INPUT/OE1
84
88
B6
126
E9
INPUT/OE2/GCLK2
2
90
A5
128
D8
TDI
14
4
A1
4
D4
TMS
23
15
F3
20
J6
TCK
62
62
F8
89
J11
TDO
71
73
A10
104
D13
42, 82
38, 86
D6, G5
52, 57, 124, 129
A8, C9, G9, K8, P9
GNDINT
GND
VCCINT
VCCIO
NC (No Connect)
Total user I/O pins
7, 19, 32, 47, 59, 11, 26, 43, 59, 74,
72
95
3, 43
39, 91
13, 26, 38, 53, 66, 3, 18, 34, 51, 66,
78
82
C3, D7, E5, F6,
G4, H8
D5, G6
A3, B10, C2, D14, F6,
3, 13, 17, 33, 59, G10, H8, J9, K7, L11,
64, 85, 105, 135 M3, P6, P10, R2, R3,
T1, T15
51, 58, 123, 130
B9, C8, G8, K9, P8
C8, D4, E6, F5,
G7, H3
B3, B5, C14, E15,
24, 50, 73, 76, 95, F11, G3, G7, G15, H9,
115, 144
J8, K10, L3, L6, M15,
P14, T2, T3
A1, A2, A4, A5, A6, A7,
A9, A10, A11, A12,
A13, A14, A15, A16,
B1, B2, B4, B6, B7,
B8, B11, B12, B13,
B14, B15, B16, C1,
C3, C4, C6, C11,
C13, C15, C16, D1,
D2, D3, D15, D16,
E1, E2, E3, E14, E16,
F1, F2, F15, F16, G1,
1, 2, 12, 19, 34,
G2, G14, G16, H1,
35, 36, 43, 46, 47,
H2, H15, H16, J1, J2,
48, 49, 66, 75, 90,
J15, J16, K1, K2, K3,
103, 108, 120,
K14, K15, K16, L1,
121, 122
L2, L15, L16, M1,
M14, M16, N1, N2,
N3, N14, N15, N16,
P1, P2, P3, P4, P12,
P13, P15, P16, R1,
R4, R5, R6, R7, R8,
R9, R11, R12, R13,
R14, R15, R16, T4,
T5, T6, T7, T8, T9,
T10, T11, T12, T13,
T14, T16
-
-
-
68
84
84
100
100
7128A tbl 01
Page 5
CL7128A and CL7128AE Laser Processed Logic Devices
DC Electrical Specifications
Recommended Operating Conditions
Symbol
Parameter
VCCINT
VCCIO
VI
VO
TA
TJ
tR
tF
tRVCC
Conditions
Min
Max
Unit
Supply voltage, internal logic and input buffers
3.0
3.6
V
Supply voltage for output drivers
3.3 volt operation
2.5 volt operation
Input voltage
3.0
2.3
-0.5
3.6
2.7
5.75
V
V
V
0
VCCIO
V
0
-40
70
85
°C
°C
0
-40
90
105
40
40
°C
°C
ns
ns
100
ms
Output voltage
Ambient Operating temperature
Commercial temperature range
Industrial temperature range
Ambient Operating temperature
Commercial temperature range
Industrial temperature range
Input signal rise time
Input signal fall time
VCC rise time
7KA tbl 02
Absolute Maximum Ratings
Symbol
VCC
VI
Parameter
Conditions
Min
Max
Unit
Supply voltage
With respect to ground
-0.5
4.6
V
DC input voltage[1]
With respect to ground
-2.0
5.8
V
-25
25
mA
IOUT
DC output current, per pin
TSTG
Storage temperature
No bias
-65
150
°C
TA
Ambient temperature
Under bias
-65
135
°C
TJ
Junction temperature
Fineline BGA, PQFP,
and TPFP packages,
Under bias
135
°C
7KA tbl 03
Page 6
CL7128A and CL7128AE Laser Processed Logic Devices
DC Electrical Specifications cont.
DC Electrical Characteristics (over the operating range)
Symbol
Parameter
Conditions
Min
Max
Unit
VIH
High-level input Voltage
1.7
5.75
V
VIL
Input LOW Voltage [1]
-0.5
0.8
V
3.3-V high-level TTL output Voltage
IOH = -8 mA DC, VCCIO = 3.00 V
2.4
V
VCCIO-0.2
V
IOH = -100 mA DC, VCCIO = 2.30 V
2.1
V
IOH = -1 mA DC, VCCIO = 2.30 V
2.0
IOH = -2 mA DC, VCCIO = 2.30 V
1.7
3.3-V high-level CMOS output Voltage IOH = -0.1 mA DC, VCCIO = 3.00 V
VOH
2.5-V high-level output Voltage
3.3-V high-level TTL output Voltage
0.45
V
3.3-V high-level CMOS output Voltage IOH = 0.1 mA DC, VCCIO = 3.00 V
0.2
V
IOH = 100 mA DC, VCCIO = 2.30 V
0.2
V
IOH = 1 mA DC, VCCIO = 2.30 V
0.4
V
IOH = 2 mA DC, VCCIO = 2.30 V
0.7
V
VOL
2.5-V high-level output Voltage
IOH = 8 mA DC, VCCIO = 3.00 V
IIN
Input Leakage Current
VI = VCC or GND
-10
10
µA
IOZ
Output Leakage Current
VO = VCC or GND
-10
10
µA
7KA tbl 04
Capacitance
Symbol
Parameter
Conditions
C IN
Input Capacitance
COUT
Output Capacitance
Min
Max
Unit
VIN = 0 V, f = 1.0 MHz
8
pF
VOUT = 0 V, f = 1.0 MHz
8
pF
7KA tbl 05
Page 7
CL7128A and CL7128AE Laser Processed Logic Devices
AC Electrical Specifications
I/O Element Timing Parameters
Symbol
Parameter
Conditions
Speed: -4
Min
Max
Speed: -5
Min
Max
Speed: -6
Min
Max Unit
tPD1
Input to non-registered output
C L = 35 pF
4.5
5.0
6.0
ns
tPD2
I/O input to non-registered output
C L = 35 pF
4.5
5.0
6.0
ns
tSU
Global clock setup time
3.0
3.2
3.7
ns
tH
Global clock hold time
0.0
0.0
0.0
ns
tFSU
Global clock setup time of fast input
2.5
2.5
2.5
ns
tFH
Global clock hold time of fast input
0.0
0.0
0.5
ns
tCO1
Global clock to output delay
tCH
Global clock high time
2.0
2.0
3.0
ns
tCL
Global clock low time
2.0
2.0
3.0
ns
tASU
Array clock setup time
1.4
1.0
0.8
ns
tAH
Array clock hold time
0.8
0.8
1.9
ns
tACO1
Array clock to output delay
tACH
Array clock high time
2.0
2.0
3.0
ns
tACL
Array clock low time
2.0
2.0
3.0
ns
tCNT
Minimum global clock period
fCNT
Max. internal global clock frequency
tACNT
Minimum array clock period
fACNT
Max. internal array clock frequency
C L = 35 pF
1.0
C L = 35 pF
2.8
1.0
4.4
5.2
5.2
192.3
1.0
1.0
5.5
181.8
5.2
192.3
3.0
6.2
6.4
156.3
5.5
181.8
3.3
ns
ns
MHz
6.4
156.3
ns
ns
MHz
7KA tbl 06A1
Page 8
CL7128A and CL7128AE Laser Processed Logic Devices
AC Electrical Specifications cont.
External Timing Parameters
Symbol
Parameter
Speed: -7
Conditions
Min
Max
Speed: -10
Min
Max
Speed: -12
Min
Max Unit
tPD1
Input to non-registered output
C L = 35 pF
7.5
10.0
12.0
ns
tPD2
I/O input to non-registered output
C L = 35 pF
7.5
10.0
12.0
ns
tSU
Global clock setup time
4.9
6.6
7.8
ns
tH
Global clock hold time
0.0
0.0
0.0
ns
tFSU
Global clock setup time of fast input
3.0
3.0
3.0
ns
tFH
Global clock hold time of fast input
0.0
0.0
0.0
ns
tCO1
Global clock to output delay
tCH
Global clock high time
3.0
4.0
5.0
ns
tCL
Global clock low time
3.0
4.0
5.0
ns
tASU
Array clock setup time
1.6
2.1
2.4
ns
tAH
Array clock hold time
2.1
3.4
4.4
ns
tACO1
Array clock to output delay
tACH
Array clock high time
3.0
4.0
5.0
ns
tACL
Array clock low time
3.0
4.0
5.0
ns
tCNT
Minimum global clock period
fCNT
Max. internal global clock frequency
tACNT
Minimum array clock period
fACNT
Max. internal array clock frequency
C L = 35 pF
1.0
C L = 35 pF
4.5
1.0
7.8
89.3
ns
13.3
75.2
11.2
89.3
7.1
12.5
11.2
8.4
119.0
1.0
10.4
8.4
119.0
5.9
ns
MHz
13.3
75.2
ns
ns
MHz
7KA tbl 06A2
Page 9
CL7128A and CL7128AE Laser Processed Logic Devices
AC Electrical Specifications cont.
Internal Timing Parameters[4]
Symbol
Parameter
Conditions
Speed: -4
Min
Max
Speed: -5
Min
Max
Speed: -6
Min
Max Unit
tiN
Input pad and buffer delay
0.3
0.3
0.3
ns
tIO
I/O input pad and buffer delay
0.3
0.3
0.3
ns
tFIN
Fast input delay
2.6
2.6
2.4
ns
tSEXP
Shared expander delay
1.9
2.4
2.8
ns
tPEXP
Parallel expander delay
0.6
0.6
0.5
ns
tLAD
Logic array delay
1.9
2.5
2.5
ns
tLAC
Logic control array delay
1.8
2.3
2.5
ns
tIOE
Internal output enable delay
0.0
0.0
0.2
ns
C L = 35 pF
0.3
0.4
0.3
ns
C L = 35 pF
0.8
0.9
0.8
ns
C L = 35 pF
5.3
5.4
5.3
ns
C L = 35 pF
4.0
4.0
4.0
ns
C L = 35 pF
4.5
4.5
4.5
ns
C L = 35 pF
9.0
9.0
9.0
ns
C L = 5 pF[3]
4.0
4.0
4.0
ns
tOD1
tOD2
Output buffer and pad delay
Slow slew rate = off, VCCIO = 5.0 V
Output buffer and pad delay
Slow slew rate = off, VCCIO = 3.3 V
Output buffer and pad delay
tOD3
Slow slew rate = on,
VCCIO = 5.0 V or 3.3 V
tZX1
tZX2
Output buffer enable delay
Slow slew rate = off, VCCIO = 5.0 V
Output buffer enable delay
Slow slew rate = off, VCCIO = 3.3 V
Output buffer enable delay
tZX3
Slow slew rate = on,
VCCIO = 5.0 V or 3.3 V
tXZ
Output buffer disable delay
tSU
Register setup time
1.4
0.8
1.0
ns
tH
Register hold time
0.8
1.0
1.7
ns
tFSU
Register setup time of fast input
0.9
0.8
1.2
ns
tFH
Register hold time of fast input
1.6
1.7
1.3
ns
tRD
Register delay
1.2
1.4
1.6
ns
tCOMB
Combinatorial delay
1.3
1.0
1.6
ns
tIC
Array clock delay
1.9
2.3
2.7
ns
tEN
Register enable time
1.8
2.3
2.5
ns
tGLOB
Global control delay
1.0
0.9
1.1
ns
tPRE
Register preset time
2.3
2.6
2.3
ns
tCLR
Register clear time
2.3
2.6
2.3
ns
tLIA
LIA delay
0.7
0.8
1.3
ns
7KA tbl 07A1
Page 10
CL7128A and CL7128AE Laser Processed Logic Devices
AC Electrical Specifications cont.
Internal Timing Parameters[4]
Symbol
Parameter
Conditions
Speed: -7
Min
Max
Speed: -10
Min
Max
Speed: -12
Min
Max Unit
tiN
Input pad and buffer delay
0.4
0.6
0.7
ns
tIO
I/O input pad and buffer delay
0.4
0.6
0.7
ns
tFIN
Fast input delay
3.3
3.7
4.1
ns
tSEXP
Shared expander delay
3.6
4.9
5.9
ns
tPEXP
Parallel expander delay
0.8
1.1
1.3
ns
tLAD
Logic array delay
3.7
5.0
6.0
ns
tLAC
Logic control array delay
3.4
4.6
5.6
ns
tIOE
Internal output enable delay
0.0
0.0
0.0
ns
C L = 35 pF
0.6
0.7
0.9
ns
C L = 35 pF
1.1
1.2
0.4
ns
C L = 35 pF
5.6
5.7
5.9
ns
C L = 35 pF
4.0
5.0
5.0
ns
C L = 35 pF
4.5
5.5
5.5
ns
C L = 35 pF
9.0
10.0
10.0
ns
C L = 5 pF[3]
4.0
5.0
5.0
ns
tOD1
tOD2
Output buffer and pad delay
Slow slew rate = off, VCCIO = 5.0 V
Output buffer and pad delay
Slow slew rate = off, VCCIO = 3.3 V
Output buffer and pad delay
tOD3
Slow slew rate = on,
VCCIO = 5.0 V or 3.3 V
tZX1
tZX2
Output buffer enable delay
Slow slew rate = off, VCCIO = 5.0 V
Output buffer enable delay
Slow slew rate = off, VCCIO = 3.3 V
Output buffer enable delay
tZX3
Slow slew rate = on,
VCCIO = 5.0 V or 3.3 V
tXZ
Output buffer disable delay
tSU
Register setup time
1.3
1.7
2.0
ns
tH
Register hold time
2.4
3.8
4.8
ns
tFSU
Register setup time of fast input
1.1
1.1
1.1
ns
tFH
Register hold time of fast input
1.9
1.9
1.9
ns
tRD
Register delay
2.1
2.8
3.3
ns
tCOMB
Combinatorial delay
1.5
2.0
2.4
ns
tIC
Array clock delay
3.4
4.6
5.6
ns
tEN
Register enable time
3.4
4.6
5.6
ns
tGLOB
Global control delay
1.4
1.8
2.2
ns
tPRE
Register preset time
3.9
5.2
6.2
ns
tCLR
Register clear time
3.9
5.2
6.2
ns
tLIA
LIA delay
1.3
1.7
2.0
ns
7KA tbl 07A2
Page 11
CL7128A and CL7128AE Laser Processed Logic Devices
AC Test Conditions
(A)
VCCIO
(B)
464 Ω
VCCIO
OUTPUT
Includes jig
capacitance
All Input Pulses
464 Ω
3.0V
90%
90%
OUTPUT
35 pF
250 Ω
Includes jig
capacitance
5 pF
250 Ω
GND
10%
10%
≤ 3ns
≤ 3ns
7K drw 02A
Notes to Tables
1. During transitions, inputs may undershoot to -2.0V for periods shorter than
20ns. Otherwise, minimum DC input voltage is 0.3V.
2. Typical values are at VCC of 5.0 volts and ambient temperature of 25 ºC.
3. Guaranteed but not tested. Characterized initially, and after any design
changes which may affect these parameters.
4. Internal timing delays are based on characterization, and cannot be explicitly
tested. Internal timing parameters should be used for performance estimation
only.
Revision History
Page 12
11 Jan. 1999:
Created preliminary document.
31 July 1999:
Created full document.
13 Oct. 1999:
Corrected typographical error in AC Test Condition diagram (W
changed to W) also corrected timing in 10ns External Timing
Paramiters
1 Dec. 2000:
Updated application note reference.
CL7128A and CL7128AE Laser Processed Logic Devices
Ordering Information
Part Number
CL7128ALC84-12
Temperature Range
Commercial
Package Type
Altera Equivalent
-12
EPM7128ALC84-12
CL7128ALC84-10
-10
EPM7128ALC84-10
CL7128ALC84-7
-7
EPM7128ALC84-7
CL7128ALC84-6
-6
EPM7128ALC84-6
CL7128ALC84-5
-5
EPM7128ALC84-5
CL7128ALC84-4
-4
CL7128ATC100-12
84-pin Plastic LCC
Speed
100-pin Thin QFP
N/A
-12
EPM7128ATC100-12
CL7128ATC100-10
-10
EPML7128ATC100-10
CL7128ATC100-7
-7
EPM7128ATC100-7
CL7128ATC100-6
-6
EPM7128ATC100-6
CL7128ATC100-5
-5
EPM7128ATC100-5
CL7128ATC100-4
-4
CL7128ATI100-10
Industrial
CL7128AFC100-12
Commercial
N/A
-10
EPML7128ATI100-10
-12
EPM7128AFC100-12
CL7128AFC100-10
-10
EPM7128AFC100-10
CL7128AFC100-7
-7
EPM7128AFC100-7
CL7128AFC100-6
-6
EPM7128AFC100-6
CL7128AFC100-5
-5
EPM7128AFC100-5
CL7128AFC100-4
-4
CL7128ATC144-12
100-pin FBGA
144-pin Thin QFP
N/A
-12
EPM7128ATC144-12
CL7128ATC144-10
-10
EPM7128ATC144-10
CL7128ATC144-7
-7
EPM7128ATC144-7
CL7128ATC144-6
-6
EPM7128ATC144-6
CL7128ATC144-5
-5
EPM7128ATC144-5
CL7128ATC144-4
-4
CL7128ATI144-10
Industrial
CL7128ATC144-12
Commercial
N/A
-10
EPM7128ATI144-10
-12
EPM7128ATC144-12
CL7128ATC144-10
-10
EPM7128ATC144-10
CL7128ATC144-7
-7
EPM7128ATC144-7
CL7128ATC144-6
-6
EPM7128ATC144-6
CL7128ATC144-5
-5
EPM7128ATC144-5
CL7128ATC144-4
-4
256-pin FBGA
N/A
7128A tbl 02
Page 13
CL7128A and CL7128AE Laser Processed Logic Devices
Ordering Information (cont.)
Part Number
CL7128AELC84-10
Temperature Range
Commercial
Package Type
Altera Equivalent
-10
EPM7128AELC84-10
CL7128AELC84-7
-7
EPM7128AELC84-7
CL7128AELC84-6
-6
EPM7128AELC84-6
CL7128AELC84-5
-5
EPM7128AELC84-5
CL7128AELC84-4
-4
CL7128AETC100-10
84-pin Plastic LCC
Speed
100-pin Thin QFP
-10
N/A
EPML7128AETC100-10
CL7128AETC100-7
-7
EPM7128AETC100-7
CL7128AETC100-6
-6
EPM7128AETC100-6
CL7128AETC100-5
-5
EPM7128AETC100-5
CL7128AETC100-4
-4
CL7128AETI100-7
Industrial
CL7128AEFC100-10
Commercial
N/A
-7
EPML7128AETI100-7
-10
EPM7128AEFC100-10
CL7128AEFC100-7
-7
EPM7128AEFC100-7
CL7128AEFC100-6
-6
EPM7128AEFC100-6
CL7128AEFC100-5
-5
EPM7128AEFC100-5
CL7128AEFC100-4
-4
CL7128AEFI100-7
Industrial
CL7128AETC144-10
Commercial
100-pin FBGA
-7
EPM7128AEFI100-7
-10
EPM7128AETC144-10
CL7128AETC144-7
-7
EPM7128AETC144-7
CL7128AETC144-6
-6
EPM7128AETC144-6
CL7128AETC144-5
-5
EPM7128AETC144-5
CL7128AETC144-4
-4
CL7128AETI144-7
Industrial
CL7128AETC144-10
Commercial
144-pin Thin QFP
N/A
-7
256-pin FBGA
N/A
EPM7128AETI144-7
-10
EPM7128AETC144-10
CL7128AETC144-7
-7
EPM7128AETC144-7
CL7128AETC144-6
-6
EPM7128AETC144-6
CL7128AETC144-5
-5
EPM7128AETC144-5
CL7128AETC144-4
-4
N/A
7128A tbl 03
Page 14