NSC CLC440

N
CLC440
High-Speed, Low-Power, Voltage Feedback Op Amp
General Description
Features
The CLC440 is a wideband, low-power, voltage feedback op amp
that offers 750MHz unity-gain bandwidth, 1500V/µs slew rate, and
90mA output current. For video applications, the CLC440 sets new
standards for voltage feedback monolithics by offering the impressive combination of 0.015% differential gain and 0.025° differential phase errors while dissipating a mere 70mW.
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The CLC440 incorporates the proven properties of Comlinear’s
current feedback amplifiers (high bandwidth, fast slewing, etc.) into a
“classical” voltage feedback architecture. This amplifier possesses
truly differential and fully symmetrical inputs both having a high
900kΩ impedance with matched low input bias currents.
Furthermore, since the CLC440 incorporates voltage feedback, a
specific Rf is not required for stability. This flexibility in choosing Rf
allows for numerous applications in wideband filtering and integration.
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Applications
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Unlike several other high-speed voltage feedback op amps, the
CLC440 operates with a wide range of dual or single supplies
allowing for use in a multitude of applications with limited supply
availability. The CLC440’s low 3.5nV/√Hz(en) and 2.5pA/√Hz(in)
noise sets a very low noise floor.
Typical Application
Unity-gain stable
High unity-gain bandwidth: 750MHz
Ultra-low differential gain: 0.015%
Very low differential phase: 0.025°
Low power: 70mW
Extremely fast slew rate: 1500V/µs
High output current: 90mA
Low noise: 3.5nV/√Hz
Dual ±2.5V to ±6V or single 5V to 12V supplies
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Professional video
Graphics workstations
Test equipment
Video switching & routing
Communications
Medical imaging
A/D drivers
Photo diode transimpedance amplifiers
Improved replacement for CLC420 or OPA620
Frequency Response (AV = +2V/V)
CLC440
High-Speed, Low-Power, Voltage Feedback Op Amp
June 1999
Generator Waveforms
10MHz to 40MHz Square and Triangular Wave Generator
Pinout
DIP & SOIC
© 1999 National Semiconductor Corporation
Printed in the U.S.A.
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CLC440 Electrical Characteristics (AV = +2, Rf = Rg = 250Ω: Vcc = + 5V, RL = 100Ω unless specified)
PARAMETERS
Ambient Temperature
CONDITIONS
CLC440
TYP
+25˚C
FREQUENCY DOMAIN RESPONSE
-3dB bandwidth AV =+2
Vout < 0.2Vpp
Vout < 4.0Vpp
-3dB bandwidth AV =+1
Vout < 0.2Vpp
gain bandwidth product
Vout < 0.2Vpp
gain flatness
Vout < 2.0Vpp DC to 75MHz
linear phase deviation
Vout < 2.0Vpp DC to 75MHz
differential gain
4.43MHz, RL=150Ω
differential phase
4.43MHz, RL=150Ω
TIME DOMAIN RESPONSE
rise and fall time
2V step
4V step
2V step
4V step
4V step, ±0.5V crossing
settling time to 0.05%
overshoot
slew rate
DISTORTION AND NOISE RESPONSE
2nd harmonic distortion
2Vpp, 5MHz
2Vpp, 20MHz
3rd harmonic distortion
2Vpp, 5MHz
2Vpp, 20MHz
equivalent input noise
voltage
>1MHz
current
>1MHz
STATIC DC PERFORMANCE
input offset voltage
average drift
input bias current
average drift
input offset current
average drift
power supply rejection ratio
common-mode rejection ratio
supply current
DC
DC
RL= ∞
MISCELLANEOUS PERFORMANCE
input resistance
common-mode
input capacitance
common-mode
differential-mode
input voltage range
common-mode
output voltage range
RL= 100Ω
output voltage range
RL= ∞
output current
MIN/MAX RATINGS
+25˚C
0 to 70˚C -40 to 85˚C
UNITS
260
190
750
230
0.05
0.8
0.015
0.025
165
150
165
135
135
130
0.15
1.2
0.03
0.05
0.20
1.5
0.04
0.06
0.20
1.5
0.04
0.06
MHz
MHz
MHz
MHz
dB
deg
%
deg
1.5
3.2
10
7
1500
2.0
4.2
14
13
900
2.2
4.5
16
13
750
2.5
5.0
16
13
600
ns
ns
ns
%
V/µs
-64
-52
-70
-51
-59
-46
-65
-45
-59
-46
-64
-43
-59
-46
-64
-43
dBc
dBc
dBc
dBc
3.5
2.5
4.5
3.5
5.0
4.0
5.0
4.0
nV/√Hz
pA/√Hz
4.0
10
40
60
3.0
10
58
60
8.0
mV
µV/°C
µA
nA/°C
µA
nA/°C
dB
dB
mA
300
2.0
1.0
±2.7
±2.2
±2.7
±45
kΩ
pF
pF
V
V
V
mA
1.0
5.0
10
30
0.5
3.0
65
80
7.0
3.0
2.0
58
65
7.5
3.5
10
35
50
2.0
10
58
60
8.0
900
1.2
0.5
±3.0
±2.5
±3.0
±80
500
2.0
1.0
±2.8
±2.3
±2.8
±72
400
2.0
1.0
±2.7
±2.2
±2.7
±65
30
NOTES
A
A
A
A
Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are
determined from tested parameters.
Absolute Maximum Ratings
voltage supply
Iout is short circuit protected to ground
common-mode input voltage
maximum junction temperature
storage temperature range
lead temperature (soldering 10 sec)
ESD rating (human bodey model)
Ordering Information
±6V
Model
CLC440AJP
CLC440AJE
CLC440A8B
±Vcc
+150˚C
-65˚C to +150˚C
+300˚C
<1000V
Plastic (AJP)
Surface Mount (AJE)
CerDip
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θjc
θja
70˚/W
60˚/W
40˚/W
125˚/W
140˚/W
130˚/W
-40˚C to +85˚C
-40˚C to +85˚C
-55˚C to +125˚C
Description
8-pin PDIP
8-pin SOIC
8-pin hermetic CerDIP,
MIL-STD-883
Contact factory for SMD number.
Notes
Package Thermal Resistance
Package
Temperature Range
A) J-level: spec is 100% tested at +25˚C.
Transitor Count
2
46
CLC440 Typical Performance Characteristics (AV = +2, Rf = 250Ω:Vcc = + 5V, RL = 100Ω unless specified)
Non-Inverting Frequency Response
Inverting Frequency Response
AV = 1(Rf = 0)
AV = -1
RL=1K
AV = 2
0
AV = 1
-45
AV = 10
-90
AV = 5
-135
AV = -5
AV -1
Phase
-180
-225
AV -10
AV -5
-270
AV -2
-315
-180
10
100
1
1000
10
100
10
Magnitude (1dB/div)
-45
Vout = 5Vpp
-90
-135
Vout = 200mVpp
CL = 100pF
Rs = 30
CL = 1000pF
Rs = 5
CL = 10pF
CL = 100pF
Phase
0
CL = 1000pF
+
-45
-90
Rs
-135
1k
CL
-
-180
100
1000
Gain
Phase (1.0deg/div)
0
100
Gain Flatness and Linear Phase
Phase (deg)
Vout = 2Vpp
-135
Frequency (MHz)
CL = 10pF
Rs = 50
Gain
Vout = 2Vpp
Phase (deg)
Magnitude (1dB/div)
-90
1
1000
Vout = 200mVpp
Gain
10
-45
-180
Frequency Response vs. Capacitive Load
Vout = 5Vpp
0
RL=50
Frequency (MHz)
Frequency Response vs. Vout
1
RL=1K
Phase
-360
Frequency (MHz)
Phase
RL=50
RL=100
Magnitude (0.05dB/div)
1
RL=100
Phase (deg)
AV = 2
Phase
AV = -2
AV = -10
(Rf = 500Ω)
Phase (deg)
Phase (deg)
AV = 5
AV = 10
Gain
Magnitude (1dB/div)
Gain
Magnitude (1dB/div)
Gain
Magnitude (1dB/div)
Frequency Response vs. Load
Phase
-180
1
1000
10
Frequency (MHz)
100
0
1000
75
Frequency (MHz)
Open Loop Gain and Phase
Frequency (7.5MHz/div)
BW vs. Gain for Transimpedance Configuration
80
0
Equivalent Input Noise
400
10
10
Cf
4
320
Phase
Cf (pF)
0
40
8
-90
0
-180
16
-270
100M
20
10k
1k
100k
1M
10M
Cf
BW
1.6
123
240
160
12
80
Cd = 20pF
BW
100
0
10000
1000
Frequency (Hz)
Voltage = 3.5nV/√Hz
Current = 2.5pA/√Hz
1
100M
1
100
1k
10k
Rf
Harmonic Distortion vs. Frequency
-45
Rf
1000
See dashed lines
20
-20
Cd = 5pF
Bandwidth (MHz)
Example
Phase (deg)
Open Loop Gain (dB)
60
Noise Current (pA/√Hz)
Cd = 1pF
Noise Voltage (nV/√Hz)
Gain
100k
1M
10M
Frequency (Hz)
PSRR, CMRR, and Closed Loop Rout
1dB Compression
45
Vo = 2Vpp
100
5MHz
CMRR
-75
2nd RL = 100
3rd RL = 100
-85
PSRR/CMRR (dB)
Gain (1dB/div)
-65
20MHz
50MHz
+
2nd RL = 1k
100MHz
50Ω
-
250Ω
3rd RL = 1k
Pout
50Ω
35
80
PSRR
25
60
15
40
5
20
Rout
250Ω
-95
0
0.1
1
50
10
-4
16
10k
10M
100M
Frequency (Hz)
Differential Gain and Phase
Intercept Point (+dBm)
Output
Output
1.4
Input
1.0
30
20
+
50Ω
-
10
250Ω
Pout
120
160
Frequency (20MHz/div)
200
1
0.04
Phase
Negative Sync
50Ω
250Ω
80
0.08
Gain
Negative Sync
Gain
Positive Sync
0
40
0.12
Phase
Positive Sync
40
10
Frequency (MHz)
3
100
1
0
2
3
Differential Gain (%), Phase (deg)
50Ω
50Ω
0
1M
100k
Output Power (Pout)
-
250Ω
1.8
12
50
+
50Ω
8
2-Tone, 3rd Order Intermodulation Intercept
Input
2.2
4
0
Frequency (MHz)
Input and Output VSWR
VSWR
Rout (Ω)
Distortion (dBc)
-55
4
Number of 150Ω Loads
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CLC440 Typical Performance Characteristics (AV = +2, Rf = 250Ω:Vcc = + 5V, RL = 100Ω unless specified)
Input Offset Voltage, Vio (mV)
Output Voltage (0.5V/div)
0
-1.0
AV = -2
-2.0
2
0
los
-2
-0.4
lb
-0.8
-6
Vio
-10
-1.2
-1.6
Time (5ns/div)
-14
-60
20
-20
60
100
0.05% Settling Time vs. Capacitive Load
80
55
Rs
60
45
+
40
25
Ts
0
10
140
-0.1
-0.2
Ib and Ios vs. Common-Mode Voltage
0.2
Offset Current, Ios (5nA/div)
Settling Error % of Output Step
0
15
1000
100
Load Capacitance CL (pF)
Long Term Settling Time
0.1
35
1k
0.1
0
-0.1
20
2.0
10
1.0
Ib
0
0
los
-10
-1.0
-20
-2.0
Bias Current, Ib (0.5µA/div)
Settling Error % of Output Step
Short Term Settling Time
CL
20
Temperature (C°)
0.2
Rs
-
Recommended Rs (Ω)
AV = +2
1.0
6
Settling Time, Ts(ns) to 0.05%
Typical DC Errors vs. Temperature
0.4
Input Bias, Offset Current, lb los (µA)
Pulse Response
2.0
-0.2
0
20
40
60
10-9 10-8 10-7 10-6
100
80
Time (ns)
10-5 10-4 10-3 10-2 10-1 100
-4.0
Time (s)
-2.4
-0.8
0.8
2.4
4.0
Common-Mode Input Voltage (V)
APPLICATION INFORMATION
General Design Equations
The CLC440 is a unity gain stable voltage feedback
amplifier. The matched input bias currents track well over
temperature. This allows the DC offset to be minimized
by matching the impedance seen by both inputs.
Output Drive and Settling Time Performance
The CLC440 has large output current capability. The
90mA of output current makes the CLC440 an excellent
choice for applications such as:
• Video Line Drivers
• Distribution Amplifiers
Gain
The non-inverting and inverting gain equations for the
CLC440 are as follows:
Non-inverting Gain: 1 +
Inverting Gain: −
When driving a capacitive load or coaxial cable, include a
series resistance Rs to back match or improve settling
time. Refer to the “Settling Time vs. Capacitive Load” plot
in the typical performance section to determine the
recommended resistance for various capacitive loads.
Rf
Rg
Rf
Rg
When driving resistive loads of under 500Ω, settling time
performance diminishes. This degradation occurs
because a small change in voltage on the output causes
a large change of current in the power supplies. This
current creates ringing on the power supplies. A small
resistor will dampen this effect if placed in series with the
6.8µF bypass capacitor.
Gain Bandwidth Product
The CLC440 is a voltage feedback amplifier, whose
closed-loop bandwidth is approximately equal to the
gain-bandwidth product (GBP) divided by the gain (Av).
For gains greater than 5, Av sets the closed-loop bandwidth of the CLC440.
Closed Loop Bandwidth =
Av =
(Rf + Rg )
Noise Figure
Noise Figure (NF) is a measure of noise degradation
caused by an amplifier.
GBP
Av
e 2
 S /N 
NF = 10LOG  i i  = 10LOG  ni2 
 So /No 
 et 
where,
Rg
GBP = 230MHz
eni = Total Equivalent Input Noise Density
Due to the Amplifier
et = Thermal Voltage Noise ( 4kTR seq)
For gains less than 5, refer to the frequency response
plots to determine maximum bandwidth.
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4
Figure 1 shows the noise model for the non-inverting
amplifier configuration. The model includes all of the
following noise sources:
Noise Figure vs. Source Resistance
25
Noise Figure (dB)
Rs(Ω) NF Unterminated NF Terminated
• Input voltage noise (en)
• Input current noise (in = in+ = in-)
• Thermal Voltage Noise (et) associated with each
external resistor
en
4kTRseq
*
15
-
10
Ropt = 1400Ω
100
4kTRf
Rg
1k
10k
100k
Source Resistance (Ω)
*
*
6.15dB
Ropt = 2800Ω
10
Rf
in-
17.90dB
3.13dB
Unterminated
0
*
*
12.03dB
Terminated
CLC440
in+
50
ROPT
5
+
*
Rseq
20
Figure 2: Noise Figure vs. Source Resistance
These boards were laid out for optimum, high-speed
performance. The ground plane was removed near the
input and output pins to reduce parasitic capacitance.
And all trace lengths were minimized to reduce series
inductances.
4kTRg
Rseq = Rs for Unterminated Systems
Rseq = Rs II RT for Terminated Systems
Figure 1: Non-inverting Amplifier Noise Model
Supply bypassing is required for the amplifiers
performance. The bypass capacitors provide a low
impedance return current path at the supply pins. They
also provide high frequency filtering on the power supply
traces. 6.8µF tantalum, 0.01µF ceramic, and 500pF
ceramic capacitors are recommended on both supplies.
Place the 6.8µF capacitors within 0.75 inches of the
power pins, and the 0.01µF and 500pF capacitors less
than 0.1 inches from the power pins.
The total equivalent input noise density is calculated
by using the noise model shown. Equations 1 and 2
represent the noise equation and the resulting equation
for noise figure.
(
)
(
)
(
) 
2
eni = en2 + in2  R seq2 + R fIIRg  + 4kTRseq + 4kT R fIIRg


Equation 1: Noise Equation
(
)
2
 2
e + in2  R seq2 + R fIIRg  + 4kTRseq + 4kT R fIIRg


 n
NF = 10LOG 
4kTR
seq


Dip sockets add parasitic capacitance and inductance
which can cause peaking in the frequency response and
overshoot in the time domain response. If sockets are
necessary, flush-mount socket pins are recommended.
The device holes in the 730055 evaluation board are
sized for Cambion P/N 450-2598 socket pins, or their
functional equivalent.



Equation 2: Noise Figure Equation
The noise figure is related to the equivalent source
resistance (Rseq) and the parallel combination of Rf and
Rg. To minimize noise figure, the following steps are
recommended:
Applications Circuits
• Minimize RfIIRg
• Choose the optimum Rs (ROPT)
Transimpedance Amplifier
The low 2.5pA/√Hz input current noise and unity gain
stability make the CLC440 an excellent choice for
transimpedance applications. Figure 3 illustrates a
low noise transimpedance amplifier that is commonly
implemented with photo diodes. Rf sets the transimpedance gain. The photo diode current multiplied by Rf
determines the output voltage.
ROPT is the point at which the NF curve reaches a
minimum and is approximated by:
e
ROPT ≅ n
in
Figure 2 is a plot of NF vs Rs with Rf = 0, Rg = ∞ (Av = +1).
The NF curves for both Unterminated and Terminated
systems are shown. The Terminated curve assumes Rs
= RT. The table indicates the NF for various source resistances including Rs = ROPT.
Cf
Rf
Photo Diode
Representation
Layout Considerations
A proper printed circuit layout is essential for achieving
high frequency performance. National provides
evaluation boards for the CLC440 (CLC730055-DIP,
CLC730060-SOIC) and suggests their use as a guide for
high frequency layout and as an aid in device testing and
characterization.
Iin
Cd
-
Vout
CLC440
+
Vout = -Iin*Rf
Figure 3: Transimpedance Amplifier Configuration
5
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The capacitances are defined as:
Rectifier
The large bandwidth of the CLC440 allows for high speed
rectification. A common rectifier topology is shown in
Figure 6. R1 and R2 set the gain of the rectifier. Vout for
a 5MHz, 2Vpp sinusoidal input is shown in Figure 7.
• Cin = Internal Input Capacitance of the CLC440
•
•
(typ 1.2pF)
Cd = Equivalent Diode Capacitance
Cf = Feedback Capacitance
D1
The transimpedance plot in the typical performance
section provides the recommended Cf and expected
bandwidth for different gains and diode capacitances.
The feedback capacitances indicated on the plot
give optimum gain flatness and stability. If a smaller
capacitance is used, then peaking will occur. The
frequency response shown in Figure 4 illustrates the
influence of the feedback capacitance on gain flatness.
D2
R2
R1
Vin
Vout
CLC440
+
Transimpedance Amplifier
Frequency Response
Figure 6: Rectifier Topology
80
Cf = 0
Rectifier Output
Cf = 1pF
2.0
Cf = 2pF
60
1.6
1.2
Cf = 2.5pF
50
0.8
Cf = 5pF
Cf
40
Vout (V)
Gain (dB)
70
1k
-
30
+
100Ω
-0.8
20
100k
10k
0
-0.4
CLC440
5pF
Iin
0.4
10M
1M
100M
-1.2
1G
-1.6
Frequency (Hz)
-2.0
0
100
400
500
Time (ns)
The total input current noise density (ini) for the basic
transimpedance configuration is shown in Equation 3.
The plot of current noise density versus feedback
resistance is shown in Figure 5.
Figure 7: Rectifier Output
Tunable Low Pass Filter
The center frequency of the low pass filter (LPF) can be
adjusted by varying the CLC522 gain control voltage, Vg.
Current Noise Density vs.
Feedback Resistance
Current Noise Density (pA/√Hz)
300
200
Figure 4
40
Ra
Rf
-
35
Rg
CLC522
30
+
(Total)
ini
20Ω
25
RT
Vg
20
en
Rf
15
R1
if
Vin
10
Rin
5
C2
C1
R
CLC440
R2
+
CLC440
Vout
+
in
0
1.0
0.1
10
ωo =
Feedback Resistance (kΩ)
k
R1R 2C1C2


RC2
Q= k 

 R1R2C1C2 
Rg =
Vin (max)
1.8mA
A v (max) = k = 1.85
Figure 5
Figure 8: Tunable Low Pass Filter
2
e 2 
4kT
ini = in +  n  +
Rf
 Rf 
Equation 3: Total Equivalent Input Referred Current
Noise Density
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6
Rf
Rg
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CLC440
High-Speed, Low-Power, Voltage Feedback Op Amp
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