N Comlinear CLC503 180MHz, Differential-Output Amplifier General Description Features The Comlinear CLC503 is a single-ended to differential amplifier. It utilizes a pair of closed-loop transconductance amplifiers to provide wideband, high fidelity, differential output signals. Internal resistors set the differential gain to 2V/V. With a ground-centered 2Vpp input signal, the CLC503 will produce a 4Vpp differential output signal. This differential output signal is centered around an adjustable common mode voltage. An independent input controls the common mode output voltage. The CLC503 has harmonic distortion products of -77dBc or less, and a signal to noise ratio of 72dB. The output stage is optimized for loads with signal ranges between +0.7 and +3.9 volts, such as those found on single supply CMOS ADCs. Overdrive recovery time of the CLC503 and following circuitry is optimized by the output limiting of the CLC503. The power down pin (PDN) allows for power savings in applications where unused circuitry is placed in a low power mode. ■ ■ ■ ■ -77dBc distortion (10MHz, 4Vpp) 72dB SNR (4Vpp) 15ns settling (0.1%) 180MHz bandwidth Applications ■ ■ Single-to-differential conversion Single supply ADC signal conditioner Harmonic Distortion vs. Amplitude -60 Comlinear CLC503 180MHz, Differential-Output Amplifier August 1996 RL = 2kΩ Distortion (dBc) -65 The CLC503 is an ideal amplifier to drive the differential inputs of the Comlinear CLC949, 12-bit, 20MSPS, analog-to-digital converter. It is tailored for driving single supply, differential input, analog-to-digital converters which require fast settling, high fidelity inputs. -70 10MHz 5MHz -75 -80 1MHz -85 2MHz -90 0 1 2 3 4 5 Output Amplitude (Vpp) Typical Application Diagram Pinout SOIC ADC Clock PDN 74AC04 Power Down Vin CLC503 Vin VREFMO 0.1µF PDN Vcm Vin +Vo VINP GND -Vo VINN VEE VCC CLK AMP 2K CORE +Vo GND -Vo VEE VCC CLC949 12b/20MSPS ADC 0.1µF 6.8µF 0.1µF 6.8µF BIASC Vcm 2K VCC GND 0.1µF -5V © 1996 National Semiconductor Corporation Printed in the U.S.A. +5V http://www.national.com Electrical Characteristics (VCC = + 5V, VEE = - 5V, Vcm = 2.25V, CL = 5pF, Vo = 4Vpp unless specified) PARAMETERS Ambient Temperature CONDITIONS CLC503 TYP +25˚C FREQUENCY DOMAIN RESPONSE Differential Amp large signal bandwidth gain flatness Common-Mode Amp -3dB bandwidth Vo < 4.0Vpp DC to 10MHz 180 0.3 80 0.5 70 0.5 MHz dB Vo < 4.0Vpp 15 10 10 MHz TIME DOMAIN RESPONSE Differential Amp rise and fall time settling time to 0.1% overshoot slew rate Common-Mode Amp recovery from power down 2V step 2V step 2V step 2V step 2.1 15 0 800 2.5 22 3.0 25 500 500 ns ns % V/µs 0.1% output settling 40 100 100 ns 4Vpp, 1MHz 4Vpp, 10MHz 4Vpp, 1MHz 4Vpp, 10MHz 4Vpp Rs = 50Ω 10kHz – 500MHz -78 -75 -85 -77 72 -74 -71 -80 -72 71 -70 -71 -79 -72 70 dBc dBc dBc dBc dB 325 380 460 µVrms Vo(Diff)/Vin Vin = 0 2 10 0.015 2 1.75 - 2.25 90 0.03 1.6 - 2.4 1.75 - 2.25 100 0.05 1.6 - 2.4 V/V mV % kΩ Vocm/Vcm 0.97 100 10 1.5 - 3.5 50 25 4.5 0.9 - 1.1 200 5 0.9 - 1.1 200 5 30 30 6 30 30 6 V/V mV MΩ V dB mA mA 60 0.9 - 3.5 375 - 625 V V V mW V Ω DISTORTION AND NOISE RESPONSE 2nd harmonic distortion 3rd harmonic distortion SNR integrated output noise voltage STATIC DC PERFORMANCE Differential Amp gain output offset voltage INL Rin Common-Mode Amp gain output offset voltage Rin input voltage range power supply rejection ratio supply current supply current, power down MISCELLANEOUS PERFORMANCE power down input VIL VIH power down dissipation output voltage range differential output resistance DC RL= ∞ CMOS levels on off PDN = “Hi” single output 0.5 - 4.8 1 4.5 45 0.7 - 3.9 500 MIN/MAX RATINGS +25˚C -40 to 85˚C 60 0.85 - 3.7 400 - 600 UNITS NOTES B B B B A A A A A A A C C A Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined from tested parameters. Notes Absolute Maximum Ratings supply voltage maximum input range maximum output range (±V) maximum operating temperature range maximum junction temperature maximum storage temperature range maximum lead temperature (soldering 10 sec) ESD rating (human body model) A) J-level: spec is 100% tested at +25˚C, sample tested at +85˚C. LC/MC-level: spec is 100% wafer probed at +25˚C. B) J-level: spec is sample tested at +25˚C. C) POWER DOWN must be 1V higher than Vcm. ±6V ±6V 0 to VCC -40˚C to +85˚C +175˚C -65˚C to +150˚C +300˚C 500V Ordering Information Model CLC503AJE Recommended Operating Conditions supply voltage input voltage output voltage ambient temperature range http://www.national.com Temperature Range Description -40˚C to +85˚C 8-pin SOIC Package Thermal Resistance ±4.5 to ±5.5Vdc ±1V +0.8 to +3.75V -40°C to +85°C Package SOIC (AJE) 2 qJC qJA 65˚C/W 90˚C/W Typical Performance Characteristics (VCC = + 5V, VEE = - 5V, Vcm = 2.25V, CL = 5pF, Vo = 4Vpp unless specified)( Frequency Response vs. Vo RL = 1kΩ RL = 500Ω RL = Open 10M Vo = 1Vpp 10M Frequency (Hz) -82 Vin = 1.2Vpp Vo = 2Vpp Vcm = 2.25 Vcm = 1.75 -80 Distortion (dBc) -82 2nd Harmonic Distortion vs. Amplitude -60 RL = 2kΩ Vcm = 2.75 -65 -86 -88 Vcm = 1.75 -90 Vcm = 1.25 -92 -94 -80 2MHz -90 0.1M 0 10M 1 Frequency (Hz) Frequency (Hz) 3 4 5 Settling Time vs. Capacitive Load 0.7 1.0 10MHz 0.6 5pf Error (%) 2MHz -85 Positive 0 Negative -90 1MHz 10pf 20pf 40pf 0.5 0.5 5MHz -80 2 Output Amplitude (Vpp) Pulse Response CLC949 Driven By CLC503 3rd Harmonic Distortion vs. Amplitude -70 5MHz 10MHz -75 1MHz -98 10M -70 -85 -96 -84 10M Frequency (Hz) Vcm = 2.25 Vcm = 1.25 Distortion (dBc) 1M Error (%) Distortion (dBc) Vcm = 2.75 RL = 2kΩ CLC949 driven by CLC503 -1dB full scale input 100M Vin = 1.2Vpp Vo = 2Vpp -84 -76 -75 SNR 60 3rd Harmonic Distortion vs. Frequency 2nd Harmonic Distortion vs. Frequency 0.1M 65 Frequency (Hz) -74 -78 70 55 1M 1G 100M Vo = 2Vpp 75 Distortion (dBc) 1M SFDR Vo = 3Vpp SFDR (dBc), SNR (dB) Vo = 1Vpp SNR and SFDR 80 Normalized Magnitude (1dB/div) Normalized Magnitude (1dB/div) Frequency Response vs. RL 0.4 0.3 0.2 -0.5 0.1 -1.0 -0.1 -95 0 -100 0 1 2 3 4 0 5 20 40 60 80 100 10 Time (ns) Output Amplitude (Vpp) Equivalent Input Noise 1000 Power Down (PDN) Response IB, VIO, vs. Temperature 100 100 Time (ns) -5 2.18 -10 2.175 5 2.17 2.165 -20 IB 2.16 -25 10 2.155 -30 10k 100k 1M 10M 100M -100 -50 Frequency (Hz) PDN 2 1 0 0 50 100 150 Output -2 Time (20ns/div) Temperature (°C) CLC949 Output When Driven By CLC503 3000 2500 Code Occurances 1k 3 -1 Voltage = 12nV/√Hz 0.1k Amplitude (1V/div) VIO (mV) VIO -15 IB (µA) Voltage Noise (nV/√Hz) 4 Input Grounded 2000 1500 1000 500 0 2012 2013 2014 2015 2016 2017 Output Code 3 http://www.national.com CLC503 APPLICATIONS APPLICATION CONSIDERATIONS Figure 2 depicts the differential output voltage limits of the CLC503. Theory of Operation Figure 1 is a simplified schematic of the CLC503. R1 R2 -Vo Output Voltage (V) Q4 +Vin PDN R4 +Vo B1 B2 Q4 +1 +Vo = Vcm +Vin 3.7 VCC Q1 -1 Q2 Vcm 2.25 3.25V Vcm 1.25V 0.8 -Vo = Vcm -Vin Q5 -1 0 R3 I I I3 Icm Figure 2: Differential Output Voltage Centered around Vcm, the outputs are derived from the following equations. VEE Current Mirror R1 = R2 2 R1 = R3 R4 = 16R1 +Vo = Vcm + Vin Figure 1: Simplified Block Diagram -Vo = Vcm − Vin The input voltage drives a unity gain buffer, B1, and an inverting buffer, B2. These buffers drive emitter followers, Q1 and Q2. Resistor, R3, is the gain set resistor. The combination of B1, B2, Q1, Q2 and R3 form a transconductance stage. The input voltage across R3 is converted to an in-phase and out-ofphase current through the collectors of Q1 and Q2. The current through R3 is: I3 = Vodiff = +Vo – (-Vo ) = 2Vin The input to output relationship is shown in Figure 3. 2Vin R3 Vodiff = I3R1 + I3R 2 Vodiff = I3 (2R1) Vodiff = 2Vin (2R1) R3 Vodiff ±1V 2Vpp ±1.4V max ±2V 4Vpp ±2.8V max Pulling the power down line (PDN) high decreases the quiescent supply current. This turns off the current flowing in Q5, and therefore Q1 and Q2, allowing the output voltages to drift high, to approximately 4.3V. Since the signal is not significantly attenuated, PDN does not effectively isolate the input from the output. This part is not recommended for use as a multiplexer. Refer to Pin Descriptions - Power Down pin section. No damage occurs to the device when PDN is high and the input is driven to the supply voltage. 2R1 = R 3 The common mode voltage across R4 is converted to a current. Transistor Q5 has a collector current equal to: VCC − Vcm − Vdiode R4 Vin Figure 3: Input vs. Output Relationship R1 = R 2 Vodiff = 2Vin Icm ≈ 1 Input Voltage (V) R 4 = 16R1 Pin Descriptions PDN VCC The common mode current is scaled and mirrored back to Q1 and Q2. These currents, I, are converted back to a voltage at the collector load resistors, R1 and R2. This forms the common-mode output voltage. Vin I = VCC − Vcm − Vdiode R1 Vocm = VCC – Vdiode – R1I I = 16Icm Vocm = Vcm 1 2 +Vo 5 7 8 4 3 6 -Vo VEE Vcm Figure 4: CLC503 Functional Pin Descriptions 4 ■ Pin 1 Power Down (PDN): The power down pin takes CMOS input levels. Use this to decrease the power from 250mW to 40mW. This is not a signal disable pin. A CMOS gate will drive this input. The quiescent supply current will be decreased when PDN is at least 1V higher than Vcm. When the current is turned off, the output voltage Vo, will go to approximately 4.3V. An internal pull down resistor of 10k allows PDN to be left open when not used. Design Information Load: The CLC503 is intended to drive high speed CMOS analog-to-digital converters, such as the CLC949. Resistive loading will affect the gain and common mode offset. It is not recommended to drive resistive loads below 10kΩ with this part. See Figure 5 for gain vs. load with specified range in device output resistance. 2.5 Ro = 600Ω = Romax Pin 2 Input Voltage (Vin): This is the signal input. The recommended input range is ±1V. The linear operating range is approximately ±1.4V This input controls the differential output voltage. Because of the closed loop nature of the transconductance stage, the transfer function is highly linear. Refer to Output Voltage pin for output signal limitations. 2 Gain (V/V) ■ 1.5 Ro = 400Ω = Romin 1 0.5 0 100 1000 10000 100000 Load Resistance (Ω) ■ ■ ■ Pin 3 Ground (GND): Tie to low impedance analog ground. 03 Fi Figure 5: Gain vs. Resistive Load Settling Time: The CLC503 settles to 0.1% in 15ns with a 5pF load, the input capacitance of the CLC949. Refer to the Settling Time vs. Capacitive Load plot in the Typical Performance Characteristics section. Pins 4 and 5 Power Supplies (VEE and VCC): For optimum performance, use linear ±5V power supplies. Use bypass capacitors of 0.1µF and 6.8µF on the power supply lines to decrease any noise that could be injected into the circuit by the power supplies. Place the bypass capacitors as close to the device pins as possible. Remove the ground plane from the board underneath the device to eliminate parasitic capacitance. Refer to Printed Circuit Board Layout section for more layout suggestions. Power Dissipation To calculate the power dissipation, PT, for the CLC503, use the following equation: PT = ICC (VCC − VEE ) Printed Circuit Board Layout Pins 6 and 7 Output Voltage (-Vo and +Vo): These are the differential signal output pins. The output voltage at these pins is limited to 0.7V to 3.9V. The output recovery time after exceeding these limits is approximately 40ns. The output voltage can be defined as: The performance of the CLC503 is strongly dependent on proper layout, and adequate power supply decoupling. The parasitic capacitance at the output of the CLC503 and the input to the CLC949, or any other analog-to-digital converter, must be kept to a minimum. Consider the following guidelines: +Vo = Vcm + Vin ■ Use a ground plane. ■ Bypass power supply pins with monolithic capacitors of 0.1µF and with 6.8µF tantalum capacitors. Place the capacitors less than 0.1" (3mm) from the pin. ■ Remove the ground plane underneath the device and 0.1" (3mm) from all input/output pads. -Vo = Vcm − Vin Vodiff = +Vo − (-Vo ) = 2Vin Vocm = ■ +Vo − (-Vo ) = Vcm 2 Pin 8 Common-Mode Voltage (Vcm): This input sets the common-mode output operating points. The common mode input voltage can range from 1.5V to 3.5V. Refer to Output Voltage pin discussion for limitations on the output range. Interfacing the CLC503 with the CLC949 The CLC503 can be easily interfaced with the CLC949 as shown in Figure 6. An evaluation board is available for proto-typing and measurements. 5 http://www.national.com Comlinear CLC503 180MHz, Differential-Output Amplifier 500Ω || RL A v new = A v old 500Ω ADC Clock 74AC04 Power Down CLC503 Vin VREFMO 0.1µF PDN Vcm Vin +Vo VINP GND -Vo VINN VEE VCC where RL equals the input resistance of the A/D. The impact of lower values of RL is shown in Figure 5. The tolerance on the 500Ω is ±20%. CLK CLC949 12b/20MSPS ADC 0.1µF 6.8µF 0.1µF 6.8µF BIASC VCC GND ■ 0.1µF -5V +5V Capacitive loading will affect the settling time. The settling time equation is: 100% t settle = R s ⋅ CL ⋅ ln %settling Figure 6: Interfacing the CLC503 with the CLC949 Extended Use Considerations Designed to drive the CLC949, the CLC503 can be used with other analog-to-digital converters. The user will want to consider the following parameters of the device that the CLC503 will drive. ■ ■ where Rs = 250Ω ±15% and %settling ≥ 0.1%. Refer to the Settling Time vs. Capacitive Load plot in the Typical Performance Characteristics section. Input impedance of the A/D. Refer to Figure 5 for the Gain vs. Resistive Load. The CLC503 operates best when driving resistive loads greater than 10kΩ and capacitive loads of less than 10pF. ■ Resistive loading will affect the gain and common mode offset. The gain setting resistors are fixed internally. The voltage gain equation is: Other considerations ■ Output signal swing must be within the specified output range. ■ Common mode range must meet the specified common mode range. ■ Distortion will be affected when Vin and Vcm drive the output out of the linear operating range. Customer Design Applications Support National Semiconductor is committed to design excellence. For sales, literature and technical support, call the National Semiconductor Customer Response Group at 1-800-272-9959 or fax 1-800-737-7018. Life Support Policy National’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of National Semiconductor Corporation. As used herein: 1. Life support devices or systems are devices or systems which, a) are intended for surgical implant into the body, or b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. N National Semiconductor Corporation National Semiconductor Europe National Semiconductor Hong Kong Ltd. National Semiconductor Japan Ltd. 1111 West Bardin Road Arlington, TX 76017 Tel: 1(800) 272-9959 Fax: 1(800) 737-7018 Fax: (+49) 0-180-530 85 86 E-mail: europe.support.nsc.com Deutsch Tel: (+49) 0-180-530 85 85 English Tel: (+49) 0-180-532 78 32 Francais Tel: (+49) 0-180-532 93 58 Italiano Tel: (+49) 0-180-534 16 80 13th Floor, Straight Block Ocean Centre, 5 Canton Road Tsimshatsui, Kowloon Hong Kong Tel: (852) 2737-1600 Fax: (852) 2736-9960 Tel: 81-043-299-2309 Fax: 81-043-299-2408 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. http://www.national.com 6 Lit #150503-002