ON CMPWR025 Dual input smart power switch Datasheet

CMPWR025
Dual Input SmartORt Power
Switch
Product Description
The SmartORt CMPWR025 is a dual input power switch that
selects between two different power inputs and delivers it to one
output. The device integrates two very low impedance power switches
and automatically implements an OR function that selects the higher
of the two inputs. Hysteresis is built in (and is user selectable) to
prevent switch chatter.
The CMPWR025 is a much−improved solution over simply ORing
two diodes, due to the greatly reduced losses of the CMPWR025 when
compared to low forward drop Schottky diodes.
The CMPWR025 is designed to operate above the 1 W (375 mA at
3.3 V) sleep mode rating stated in the PCI Rev 2.2 spec. In fact the
CMPWR025 current rating is dependent upon the power dissipation
resulting from the voltage drop across the internal switch elements.
See the Typical DC Characteristics section in this data sheet for
details.
For IAPC (Instantly Available Personal Computer) applications see
ON Semiconductor Application Note “Instantly Available PCI Card
Power Management”.
The CMPWR025 is housed in a 8−lead MSOP package and is
available with RoHS compliant lead−free finishing.
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MSOP 8
R SUFFIX
CASE 846AD
MARKING DIAGRAM
R025
R025
= CMPWR025R
Features









Implements Logical “Input VCC1 OR Input VCC2”
Integrated Low Impedance Switches (0.2 W TYP)
Operating Supply Range from 2.8 V to 5.5 V
Provides Up to 600 mA Output Current
Glitch−Free Output During Supply Switching Transitions
Low Operating Supply Current of 20 mA (TYP)
User−Selectable Hysteresis for Supply Selection
8−Pin MSOP Package
These Devices are Pb−Free and are RoHS Compliant
ORDERING INFORMATION
Device
Package
Shipping†
CMPWR025R
MSOP 8
(Pb−Free)
4000/Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Applications






PCI Cards for Wake−On−LAN/Wake−On−Ring
Dual Power Systems
Systems with Standby Capabilities
Battery Backup Systems
See also Application Note AP−211
USB Enabled Mobile Electronics such as MP3 Players, PDAs,
Digital Cameras and Wireless Handsets
 Semiconductor Components Industries, LLC, 2011
April, 2011 − Rev. 4
1
Publication Order Number:
CMPWR025/D
CMPWR025
TYPICAL APPLICATION CIRCUIT
SIMPLIFIED ELECTRICAL SCHEMATIC
SW1
0.2 W
CMPWR025
VCC1
VCC1
5V−
VOUT
VCC2
+
VCC2 +
5V −
HYS
GND
VCC1
VOUT
+
+
COUT
10 mF
-
SW2
0.2 W
VOUT
VCC2
GND
HYS
GND
PACKAGE / PINOUT DIAGRAM
Top View
1
8
HYS
VCC1
2
7
VOUT
VCC2
3
6
VOUT
VCC2
4
5
GND
R025
VCC1
8−Pin MSOP
CMPWR025R
Table 1. PIN DESCRIPTIONS
Pin(s)
Name
Description
1, 2
VCC1
VCC1 is the primary power source, which is given priority when present. If pin 8 (HYS) is unconnected, then
the hysteresis level is 75 mV (typ.). Whenever the primary power source drops below the secondary supply
VCC2 by more than 125 mV, it will immediately become deselected. When the primary power source is
restored to within 50 mV of the secondary supply, the primary power source will once again be selected and
provide all the output current. When VCC1 is selected, it will supply all the internal current requirements which
are typically 20 mA. When VCC1 is not selected, there will be no current loading on this input.
Pins 1 & 2 must be connected together externally.
3, 4
VCC2
VCC2 is the secondary power source and is selected when the primary source has fallen below it by more
than 125 mV (or 200 mV if pin 8 is grounded). The secondary source will be deselected immediately once the
primary source is restored to within 50 mV of VCC2. When VCC2 is selected, it will supply all the internal
current requirements which are typically 20 mA. When VCC2 is not selected, there will be no current loading on
this input.
Pins 3 & 4 must be connected together externally.
5
GND
Negative reference for all voltages.
6, 7
VOUT
Positive voltage output switched from VCC1 or VCC2 inputs. During normal operation the impedance from
VOUT to the selected supply is typically less than 0.28 W, which results in minimal voltage loss from input to
output. During the cold−start interval when both inputs are initially applied, the internal circuitry provides a soft
turn−on for the switches, which limits peak in−rush current.
Pins 6 & 7 must be connected together externally.
8
HYS
HYS is the user−selectable hysteresis input. The hysteresis level is set to 150 mV when pin 8 is grounded.
The default hysteresis level is set to 75 mV by leaving pin 8 unconnected. Using 150 mV hysteresis is
recommended, especially in environments with noisy power supplies, high power supply resistances or high
load currents. If the hysteresis level is set to 150 mV, the primary supply VCC1 must now fall 200 mV below
the secondary supply VCC2 before it becomes deselected.
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CMPWR025
SPECIFICATIONS
Table 2. ABSOLUTE MAXIMUM RATINGS
Parameter
ESD Protection (HBM)
Pin Voltages
VCC1
VCC2
Rating
Units
2000
V
V
[GND − 0.5] to [+6.0]
[GND − 0.5] to [+6.0]
Maximum DC Output Current
750
mA
Storage Temperature Range
−65 to +150
C
Operating Temperature Range
Ambient
Junction
−20 to +70
−20 to +125
Power Dissipation
C
0.3
W
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Table 3. STANDARD OPERATING CONDITIONS
Parameter
Rating
Units
VCC1 and VCC2 Input Voltage
2.8 to 5.5
V
Ambient Operating Temperature
0 to +70
C
ILOAD
0 to 600
mA
Table 4. ELECTRICAL OPERATING CHARACTERISTICS (Note 1)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
VCCDES1
VCC1 Deselect
VCC1 Deselect Level below VCC2;
HYS Input (Pin 8) Floating
50
125
200
mV
VCCDES2
VCC2 Deselect 2
VCC1 Deselect Level below VCC2;
HYS Input (Pin 8) Grounded
90
200
300
mV
VCC1SEL
VCC1 Select Preference
10
50
100
mV
40
80
75
150
100
200
VHYS1
VHYS2
Hysteresis
VCC1SEL−VCC1DES
VCC1SEL−VCC1DES
HYS Input (Pin 8) Floating (Note 2)
HYS Input (Pin 8) Grounded (Note 2)
mV
tDL
tDH
Switching Delay
VCC1,2 Falltime < 100 ns (Note 3)
VCC1,2 Risetime < 100 ns (Note 3)
200
200
RSW
Switch Resistance
ILOAD = 0 to 600 mA; VCC1,2 = 2.8 V
ILOAD = 0 to 600 mA; VCC1,2 = 5.0 V
0.28
0.21
0.4
0.3
W
VSW
Voltage Drop Across Switch
(VCC1,2 − VOUT)
IOUT = 100 mA; VCC1,2 = 2.8 V
IOUT = 200 mA; VCC1,2 = 2.8 V
IOUT = 600 mA; VCC1,2 = 2.8 V
IOUT = 100 mA; VCC1,2 = 5.0 V
IOUT = 200 mA; VCC1,2 = 5.0 V
IOUT = 600 mA; VCC1,2 = 5.0 V
28
56
168
21
42
125
40
80
240
30
60
180
mV
IRCC1
IRCC2
Reverse Leakage
VCC1 = 0 V; VCC2 = 5.0 V
VCC1 = 5.0 V; VCC2 = 0 V
100
100
mA
Supply Current
When Selected (IOUT = 0)
When NOT Selected
20
1
Ground Pin Current
VCC1 = VCC2 = 5.0 V;
ILOAD = 0 mA to 600 mA
20
ICC1, ICC2
IGND
ns
mA
50
mA
1. Operating Characteristics are over Standard Operating Conditions unless otherwise specified.
2. Hysteresis level defines the maximum level of acceptable noise on VCC during switching. Excessive parasitic inductance on VCC board traces
to the CMPWR025 may require an input capacitor to adequately filter the supply noise to below the hysteresis level. This will ensure that
precise switching occurs between VCC1 and VCC2 supply inputs.
3. This is the time, after the select/deselect threshold is reached, for the switches to react.
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CMPWR025
SELECTION THRESHOLD DIAGRAMS
Figure 1. Supply Threshold Diagram
(Hysteresis Input Pin Floating, See Typical Application Circuit, Page 2)
Figure 2. Supply Threshold Diagram
(Hysteresis Input Tied to Ground, See Typical Application Circuit, Page 2)
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CMPWR025
CMPWR025 TYPICAL DC CHARACTERISTICS
The Switch Resistance vs. Temperature curve shown in
Figure 3 illustrates the switch resistance measured at
600 mA load with VCC equal to 3.3 V and 5 V. The
resistance is shown at a temperatures range of −40C to
70C. When the temperature rises from 25 to 70C, the
switch resistance increases by about 20%.
Figure 5. Hysteresis Voltage vs. Temperature
Power Dissipation and Output Current
Considerations
The CMPWR025 is supplied in an MSOP package which
has a maximum power dissipation rating of 0.3 W. It is
important that the heat generated within the part does not
exceed this rating. The heat generated by the load current is
given by:
P DISS + V SW I LOAD
or
P DISS + R SW (I LOAD) 2
Figure 3. Switch Resistance vs. VCC
with Temperature
The Supply Current vs. Temperature curve shown in
Figure 4 illustrates the internal supply current with VCC
equal to 3.3 V and 5 V. This current is drawn from the
selected VCC input, and is dissipated through the ground pin
(pin 5). This current is independent of load current.
At a typical load of 375 mA the PDISS is just
0.4
(0.375) 2 + 56mW
A primary consideration is Maximum Junction
Temperature, TJ(max), which can be calculated using the
following formula:
T J(max) + T A ) q JA
P DISS
Where: TA = The Ambient Temperature
qJA = Thermal Resistance = 100 C/W
PDISS = Power Dissipation
In the above example operating at an ambient of 70C,
TJ(max) would be:
T J(max) + 70° C ) (0.056W)(100° CńW) + 75.6° C
Maximum power dissipation, including the power from
the other circuitry within the device, suggests a current
rating of approximately:
Figure 4. Supply Current vs. Temperature
ǸP
The Hysteresis Voltage vs. Temperature curve shown in
Figure 5 illustrates how the hysteresis voltages vary with
temperature. ‘VHYS1’ is the hysteresis value if pin 8 is left
unconnected, ‘VHYS2’ is the hysteresis value if pin 8 is
connected to ground. ‘VCC1sel’ is the voltage below VCC2
at which Vcc1 will be selected (refer to selection threshold
diagrams on page 4). These three voltages are independent
of the VCC operating voltage.
* P INT
+ I LOAD
R SW
DISS
Ǹ0.3W *0.4100mW + 865mA
Note that this is beyond the maximum current rating of the
device, which is 750 mA maximum.
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CMPWR025
Important note: The power supply source impedance
must be as low as possible to avoid chatter during power
transition. When operating in a high load and long rise time
power−up condition, we recommend not exceeding a value
of 0.15 W on both source resistances.
Typical Transient Characteristics
The circuit schematic in Figure 6 below shows the
transient characterization test setup. It includes the power
supply source impedances RS1 and RS2, which represent the
power supplies’ output impedances and interconnection
parasitics to the VCC1 and VCC2 input pins. In this test
set−up, the series resistances on VCC1 and VCC2 are
respectively RS1 = 0.16 W, and RS2 = 0.06 W, unless
specified otherwise. A load resistance RL of 11 W is used,
setting a load current of about 450 mA at 5 V.
The hysteresis level is increased by connecting pin 8 to
ground, which will improve the transient performance in
noisy environments. In the transient analysis, the rise time
and fall time of VCC1 is very long, in the 20 msec range,
providing a worst case situation.
V HYS u I(R S ) R T)
Where: VHYS = The Minimum Hysteresis
Voltage = 80 mV
RS = The Power Supply Output Impedance
RT = The PCB Trace Impedance
For a rated load of 600 mA, RS + RT < 0.15 W.
RS1
VCC1
5V
TR=20ms
TF=20ms
C1
+ C2
0.1 mF
10 mF
GND
CMPWR025
VCC1
RS2
+V
CC2
−5V
VOUT
VCC2
C3
+
0.1 mF
C4
HYS
GND
VOUT
C5
10 mF
0.1 mF
+ C6
10 mF
Load
11 W
GND
Figure 6. Transient Characterization Test Set−Up
Input and Output Capacitors
VOUT provides the power for the load. To ensure the
output is glitch−free during dynamic switching of the inputs,
it is recommended that an external capacitor of 10 mF or
greater is included. This will restrict any transient output
disturbances to less than 300 mV at 600 mA loading during
dynamic switching of the inputs.
The test set−up used in Figure 7 and Figure 8 is described
on page 5. The set−up for Figure 9 has larger series
resistances on VCC1 and VCC2.
VCC1 Rising from 0 V to 5 V/(VCC2 = 5 V). Figure 7
shows the primary supply VCC1 becoming selected during
a 0 V to 5 V transition. The secondary supply VCC2 is set to
5 V DC. The channel 1 switch is turned on when VCC1 rises
to within about 70 mV of VCC2. VCC1 drops when it is
selected due to power supply source resistance RS1.
A positive glitch appears on VCC2 when channel 2 switch is
Filtering is typically unnecessary on the inputs, however
power supply source impedance and parasitic resistance or
inductance on the interconnections may result in chattering
during the supply changeover. When an input is deselected
and the input current drops to zero, the voltage at the input
terminals will rise. If this voltage rise exceeds the hysteresis
(75 mV typical), the switch may chatter.
There are four ways to eliminate this chatter:
1. Connect pin 8 to GND to select 150 mV
hysteresis,
2. position the device as close as possible to the
power supply connectors,
3. use low−impedance PCB traces, or
4. include low−ESR input bypass capacitors at the
VCC1 and VCC2 input pins. Capacitors of 10ĂmF or
greater are recommended.
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CMPWR025
VCC1 Rising (VCC2 = 5 V). Figure 9 is a bad test set−up
that shows what may happen if either power supply source
resistance RS1 or RS2 is too large. In this example, RS2 is
increased to 0.3 W.
turned off, due to power supply inductance. This has no
effect on the output voltage.
Figure 7. VCC1 Rising form 0 V to 5 V, VCC2 = 5 V.
Ch1 and Ch2: VCC1 and VCC2, offset = 5 V.
Ch3: VOUT, offset = 5 V.
Figure 9. VCC1 Rising (VCC2@ = 5 V).
Ch1 and Ch2: VCC1 and VCC2@, offset = 5 V.
Ch3: VOUT, offset = 3.3 V.
VCC1 Falling from 5 V to 0 V (VCC2 = 5 V). Figure 8
shows the primary supply VCC1 becoming deselected during
a 5 V to 0 V transition. The test conditions are the same as
in Figure 7. Channel 2 switch is turned on as soon as VCC2
and VCC1 are about 200 mV. A negative glitch appears on
VCC2, when channel 2 is turned on. This has no effect on the
output voltage.
The oscillation during the power transition is caused by
the cumulative voltage change across RS1 and RS2 being
greater than the hysteresis. The behavior is exacerbated by:
 a high load current,
 too many parasitics on power lines, and
 noisy power sources.
To avoid such behavior, the solution is to reduce the load
or parasitic capacitance on power supply and layout, or use
a more stable power supply.
Parallel Operation
Two CMPWR025 devices may be symmetrically ganged
in parallel to increase total current capacity. Careful
attention must be paid to minimizing series resistance and
PCB parasitics during layout, both between the dual
CMPWR025’s inputs and also between the supplies and the
devices, as described above.
In a well designed layout, a pair of CMPWR025’s can
provide an output approaching twice that of a single device.
See Application Note AP−211 for more information.
Figure 8. VCC1 Falling form 0 V to 5 V (VCC2 = 5 V).
Ch1 and Ch2: VCC1 and VCC2, offset = 5 V.
Ch3: VOUT, offset = 5 V.
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CMPWR025
PACKAGE DIMENSIONS
MSOP 8, 3x3
CASE 846AD−01
ISSUE O
MIN
NOM
A1
0.05
0.10
0.15
A2
0.75
0.85
0.95
b
0.22
0.38
c
0.13
0.23
D
2.90
3.00
3.10
E
4.80
4.90
5.00
E1
2.90
3.00
3.10
SYMBOL
MAX
1.10
A
E
E1
0.65 BSC
e
L
0.60
0.40
0.80
L1
0.95 REF
L2
0.25 BSC
θ
0º
6º
TOP VIEW
D
A
DETAIL A
A2
A1
END VIEW
c
e
b
q
SIDE VIEW
L2
L
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-187.
L1
DETAIL A
SmartOR is a trademark of Semiconductor Components Industries, LCC (SCILLC).
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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CMPWR025/D