CS43L43
Low Voltage, Stereo DAC with Headphone Amp
Features
Description
16-Pin
The CS43L43 is a complete stereo digital-to-analog output system including interpolation, 1-bit D/A conversion,
analog filtering, volume control, and a headphone amplifier, in a 16-pin TSSOP package.
TSSOP Package
1.8 to 3.3 Volt Supply
24-Bit Conversion / 96 kHz Sample Rate
94 dB Dynamic Range at 3 V Supply
-85 dB THD+N at 1.8 V Supply
Low Power Consumption
Digital Volume Control
The CS43L43 is based on delta-sigma modulation,
where the modulator output controls the reference voltage input to an ultra-linear analog low-pass filter. This
architecture allows infinite adjustment of the sample rate
between 2 kHz and 100 kHz simply by changing the
master clock frequency.
• 96 dB Attenuation, 1 dB Step Size
Digital
Bass and Treble Boost
The CS43L43 contains on-chip digital bass and treble
boost, peak signal limiting and de-emphasis. The
CS43L43 operates from a +1.8 V to +3.3 V supply and
consumes only 16 mW of power with a 1.8 V supply.
These features are ideal for portable CD, MP3 and MD
players and other portable playback systems that require
extremely low power consumption.
• Selectable Corner Frequencies
• Up to 12 dB Boost in 1 dB Increments
Peak
Signal Limiting to Prevent Clipping
De-emphasis for 32 kHz, 44.1 kHz, and
48 kHz
Headphone Amplifier
• up to 22 mWrms Power Output into 16 Ω Load*
• 25 dB Analog Attenuation and Mute
• Zero Crossing Click-free Level Transitions
ATAPI
Mixing Functions
ORDERING INFORMATION
CS43L43-KZ
CS43L43-KZZ, Lead Free
CDB43L43
-10 to 70 °C
-10 to 70 °C
16-pin TSSOP
16-pin TSSOP
Evaluation Board
* 1 kHz sine wave at 3.3V supply
DIF1/SDA
DIF0/SCL
RST
CONTROL PORT INTERFACE
DIGITAL
VOLUME
CONTROL
LRCK
SCLK/DEM
SERIAL
AUDIO
INTERFACE
DEEMPHASIS
BASS/TREBLE
BOOST
LIMITING
∆Σ
DAC
ANALOG
FILTER
ANALOG
VOLUME
CONTROL
DIGITAL
FILTER
∆Σ
DAC
ANALOG
FILTER
ANALOG
VOLUME
CONTROL
HP_A
HEADPHONE
AMPLIFIER
HP_B
SDATA
MCLK
Preliminary Product Information
http://www.cirrus.com
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Copyright © Cirrus Logic, Inc. 2004
(All Rights Reserved)
JUL ‘04
DS479PP3
CS43L43
TABLE OF CONTENTS
1.0 PIN DESCRIPTION ..............................................................................................4
2.0 TYPICAL CONNECTION DIAGRAM .................................................................5
3.0 APPLICATIONS ...................................................................................................6
3.1 Sample Rate Range/Operational Mode Select ...........................................6
3.2 System Clocking .........................................................................................6
3.3 Digital Interface Format ..............................................................................7
3.4 De-Emphasis Control ..................................................................................8
3.5 Recommended Power-up Sequence ..........................................................9
3.6 Popguard® Transient Control .....................................................................9
3.7 Grounding and Power Supply Arrangements ...........................................12
3.8 Control Port Interface ................................................................................12
3.9 Memory Address Pointer (MAP) ...............................................................14
4.0 REGISTER QUICK REFERENCE .....................................................................14
5.0 REGISTER DESCRIPTION ...............................................................................15
5.1 Power and Muting Control (address 01h) .................................................15
5.2 Channel A Analog Attenuation Control (address 02h) (VOLA).................17
5.3 Channel B Analog Attenuation Control (address 03h) (VOLB).................17
5.4 Channel A Digital Volume Control (address 04h) (DVOLA) ......................18
5.5 Channel B Digital Volume Control (address 05h) (DVOLB) ......................18
5.6 Tone Control (address 06h).......................................................................18
5.7 Mode Control (address 07h) ......................................................................19
5.8 Limiter Attack Rate (address 08h) (ARATE)..............................................21
5.9 Limiter Release Rate (address 09h) (RRATE) ......................................21
5.10 Volume and Mixing Control (address 0Ah) ..............................................22
5.11 Mode Control 2 (address 0Bh).................................................................24
6.0 CHARACTERISTICS AND SPECIFICATIONS .................................................25
ANALOG CHARACTERISTICS (CS43L43-KZ)................................................25
COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE ..27
SWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACE ....................30
Contacting Cirrus Logic Support
For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:
http://www.cirrus.com/corporate/contacts
IMPORTANT NOTICE
"Preliminary" product information describes products that are in production, but for which full characterization data is not yet available. "Advance" product information describes products that are in development and subject to development changes. Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information
contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any
kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied
on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining
to warranty, patent infringement, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as
the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing
this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property
rights. Cirrus owns the copyrights of the information contained herein and gives consent for copies to be made of the information only for use within your organization
with respect to Cirrus integrated circuits or other parts of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising
or promotional purposes, or for creating any work for resale.
An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in this material
and controlled under the "Foreign Exchange and Foreign Trade Law" is to be exported or taken out of Japan. An export license and/or quota needs to be obtained
from the competent authorities of the Chinese Government if any of the products or technologies described in this material is subject to the PRC Foreign Trade Law
and is to be exported or taken out of the PRC.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE
SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH
APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK.
Purchase of I2C components of Cirrus Logic, Inc., or one of its sublicensed Associated Companies conveys a license under the Phillips I2C Patent Rights to use
those components in a standard I2C system.
Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks
or service marks of their respective owners.
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CS43L43
SWITCHING CHARACTERISTICS - INTERNAL SERIAL CLOCK.................. 31
SWITCHING SPECIFICATIONS - CONTROL PORT INTERFACE................. 32
DC ELECTRICAL CHARACTERISTICS .......................................................... 33
DIGITAL INPUT CHARACTERISTICS & SPECIFICATIONS .......................... 33
THERMAL CHARACTERISTICS AND SPECIFICATIONS.............................. 33
RECOMMENDED OPERATING SPECIFICATIONS ....................................... 34
ABSOLUTE MAXIMUM RATINGS ................................................................... 34
7.0 PARAMETER DEFINITIONS ............................................................................. 35
8.0 REFERENCES ................................................................................................... 35
9.0 PACKAGE DIMENSIONS ................................................................................. 36
LIST OF FIGURES
Figure 1. Typical Connection Diagram .............................................................................. 5
Figure 2. I2S Data .............................................................................................................. 8
Figure 3. Left Justified up to 24-Bit Data ........................................................................... 8
Figure 4. Right Justified Data ............................................................................................ 8
Figure 5. De-Emphasis Curve ........................................................................................... 8
Figure 6. Optional Headphone Mute Circuit .................................................................... 11
Figure 7. Timing for Headphone Mute ............................................................................. 11
Figure 8. Control Port Timing .......................................................................................... 13
Figure 9. ATAPI Block Diagram ....................................................................................... 23
Figure 10. Output Test Load ............................................................................................ 26
Figure 11. Single-Speed Stopband Rejection ................................................................. 28
Figure 12. Single-Speed Transition Band ........................................................................ 28
Figure 13. Single-Speed Transition Band (Detail) ........................................................... 28
Figure 14. Single-Speed Passband Ripple ...................................................................... 28
Figure 15. Double-Speed Stopband Rejection ................................................................ 28
Figure 16. Double-Speed Transition Band ...................................................................... 28
Figure 17. Double-Speed Transition Band (Detail) .......................................................... 29
Figure 18. Double-Speed Passband Ripple .................................................................... 29
Figure 19. External Serial Mode Input Timing ................................................................. 30
Figure 20. Internal Serial Mode Input Timing .................................................................. 31
Figure 21. Internal Serial Clock Generation .................................................................... 31
Figure 22. Control Port Timing - I2C Mode ..................................................................... 32
LIST OF TABLES
Table 1. CS43L43 Operational Mode ................................................................................ 6
Table 2. Single-Speed Mode Standard Frequencies ......................................................... 6
Table 3. Double-Speed Mode Standard Frequencies ....................................................... 6
Table 4. Internal SCLK/LRCK Ratio .................................................................................. 7
Table 5. Digital Interface Format - Stand-Alone Mode ...................................................... 7
Table 6. De-Emphasis Control .......................................................................................... 9
Table 7. Example Analog Volume Settings ..................................................................... 17
Table 8. Example Digital Volume Settings ...................................................................... 18
Table 9. Example Bass Boost Settings ........................................................................... 18
Table 10. Example Treble Boost Settings ....................................................................... 19
Table 11. Example Limiter Attack Rate Settings ............................................................. 21
Table 12. Example Limiter Release Rate Settings .......................................................... 21
Table 13. ATAPI Decode ................................................................................................. 23
Table 14. Digital Interface Format - Control Port Mode ................................................... 24
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CS43L43
1.0 PIN DESCRIPTION
LRCK
SDATA
SCLK/DEM
VL
MCLK
DIF0/SCL
VQ_HP
REF_GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
RST
DIF1/SDA
HP_B
VA_HP
VA
GND
HP_A
FILT+
Pin Name
#
Pin Description
LRCK
1
Left Right Clock (Input) - Determines which channel, Left or Right, is currently active on the
serial audio data line.
SDATA
2
Serial Audio Data (Input) - Input for two’s complement serial audio data.
SCLK
3
Serial Clock (Input) - Serial clock for the serial audio interface.
DEM
3
De-emphasis Control (Input) - Selects the standard 15µs/50µs digital de-emphasis filter
response for 44.1 kHz sample rates.
VL
4
Logic Power (Input) - Positive power for the serial audio & control port interface.
MCLK
5
Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters.
VQ_HP
7
Headphone Quiescent Voltage (Output) - Filter connection for internal headphone amp quiescent reference voltage.
REF_GND
8
Reference Ground (Input) - Ground reference for the internal sampling circuits.
FILT+
9
Positive Voltage Reference (Output) - Positive voltage reference for the internal sampling circuits.
HP_A
HP_B
10
14
Headphone Outputs (Output) - The full-scale analog headphone output level is specified in the
Analog Characteristics table.
GND
11
Ground (Input) - Ground reference.
VA
12
Power (Input) - Positive power for the analog & digital sections.
VA_HP
13
Headphone Amp Power (Input) - Positive power for the headphone amplifier.
RST
16
Reset (Input) - Powers down device and resets registers to default conditions when enabled.
6
15
Digital Interface Format (Input) - Defines the required relationship between the Left Right
Clock, Serial Clock, and Serial Audio Data.
SCL
6
Serial Control Port Clock (Input) - Serial clock for the control port interface.
SDA
15
Serial Control Data I/O (Input/Output) - Input/Output for I2C data.
Stand-Alone
Definitions
DIF0
DIF1
Control Port
Definitions
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DS479PP3
CS43L43
2.0 TYPICAL CONNECTION DIAGRAM
1.8 to 3.3 V
Supply
*Ferrite
bead
*Ferrite
bead
+
*1.0 µF
+
0.1 µF
0.1 µF
12
1.8 to 3.3 V
Supply
*Ferrite
bead
+
*1.0 µF
VA
4
HP_A
VL
HP_B
CS43L43
Serial Audio
Data
Processor
1
3
2
MCLK
µc/
Mode
Configuration
* Optional
6
15
10 220 µF
+
1 kΩ
14 220 µF
+
1 kΩ
47 µH
16 Ω
Headphones
47 µH
LRCK
SCLK/DEM
VQ_HP
SDATA
FILT+
16
*1.0 µF
13
VA_HP
0.1 µF
5
0.9 to 3.3 V
Supply
7
9
+
RST
DIF0/SCL
REF_GND
8
1.0 µF
+
1.0 µF
DIF1/SDA
GND
11
Figure 1. Typical Connection Diagram
DS479PP3
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CS43L43
3.0 APPLICATIONS
3.1 Sample Rate Range/Operational Mode Select
The device operates in one of two operational modes. Operation in either mode depends on the input sample rate and the ratio of the master clock to the left/right clock (see section 3.2). Sample rates outside the
specified range for each mode are not supported.
Input Sample Rate (FS)
2kHz - 50kHz
50kHz - 100kHz
MODE
Single Speed Mode
Double Speed Mode
Table 1. CS43L43 Operational Mode
3.2 System Clocking
The device requires external generation of the master (MCLK) and left/right (LRCK) clocks. The device
also requires external generation of the serial clock (SCLK) if the internal serial clock is not used. The
LRCK, defined also as the input sample rate Fs, must be synchronously derived from MCLK according to
specified ratios. The specified ratios of MCLK to LRCK, along with several standard audio sample rates
and the required MCLK frequency, are illustrated in Tables 2-3.
Sample Rate
(kHz)
32
44.1
48
256x
8.1920
11.2896
12.2880
384x
12.2880
16.9344
18.4320
MCLK (MHz)
512x
16.3840
22.5792
24.5760
768x*
24.5760
33.8688
36.8640
1024x*
32.768
45.1584
49.1520
Table 2. Single-Speed Mode Standard Frequencies
Sample Rate
(kHz)
64
88.2
96
MCLK (MHz)
128x
8.1920
11.2896
12.2880
192x
12.2880
16.9344
18.4320
256x*
16.3840
22.5792
24.5760
384x*
24.5760
33.8688
36.8640
Table 3. Double-Speed Mode Standard Frequencies
*Requires MCLKDIV bit = 1 in the Mode Control 2 register (address 0Bh).
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CS43L43
3.2.1 Internal Serial Clock Mode
The device will enter the Internal Serial Clock Mode if no low to high transitions are detected on the
SCLK pin for 2 consecutive periods of LRCK. In this mode, the SCLK is internally derived and synchronous with MCLK and LRCK. The SCLK/LRCK ratio is either 32, 48, or 64 depending upon the
MCLK/LRCK ratio and the Digital Interface Format selection (see Table 4).
The internal serial clock is utilized when de-emphasis control is required. Operation in the Internal
Serial Clock mode is identical to operation with an external SCLK synchronized with LRCK; however, External SCLK mode is the recommended system clocking application.
Input
MCLK/LRCK
Ratio
512, 256, 128
384, 192
512, 256, 128
Digital Interface Format Selection
Left Justified 24 Right Justified
I S 16
Bits
24, 20, or 18 Bits
Bits
X
2
2
I S up to 24
Bits
X
X
X
X
X
X
Right Justified
16 Bits
Internal
SCLK/LRCK
Ratio
X
32
X
48
64
Table 4. Internal SCLK/LRCK Ratio
3.2.2 External Serial Clock Mode
The device will enter the External Serial Clock Mode whenever 16 low to high transitions are detected on the SCLK pin during any phase of the LRCK period. The device will revert to Internal Serial
Clock Mode if no low to high transitions are detected on the SCLK pin for 2 consecutive periods of
LRCK.
3.3 Digital Interface Format
The device will accept audio samples in 1 of 4 digital interface formats in Stand-Alone mode, as illustrated
in Table 5, and 1 of 7 formats in Control Port mode, as illustrated in Table 14.
3.3.1 Stand-Alone Mode
The desired format is selected via the DIF0 and DIF1 pins. For an illustration of the required relationship between the LRCK, SCLK and SDATA, see Figures 2-4.
DIF1
0
0
1
1
DIF0
0
1
0
1
DESCRIPTION
I2S, up to 24-bit data
Left Justified, up to 24-bit data
Right Justified, 24-bit Data
Right Justified, 16-bit Data
FORMAT
0
1
2
3
FIGURE
2
3
4
4
Table 5. Digital Interface Format - Stand-Alone Mode
DS479PP3
7
CS43L43
3.3.2 Control Port Mode
The desired format is selected via the DIF0, DIF1 and DIF2 bits in the Mode Control 2 register (see
section 5.11.2) . For an illustration of the required relationship between LRCK, SCLK and SDATA,
see Figures 2-4.
L e ft C h a n n e l
LR C K
R ig h t C h a n n e l
SCLK
S D A TA
M SB
-1 -2 -3 -4 -5
+ 5 +4 +3 + 2 +1
LS B
M SB
-1 -2 -3 -4
+ 5 +4 +3 + 2 +1
LS B
Figure 2. I2S Data
L e ft C h a n n e l
LR C K
R ig h t C h a n n e l
SCLK
SDATA
M SB
-1 -2 -3 -4 -5
+5 +4 +3 +2 + 1
MSB
LS B
-1 -2 -3 -4
+5 +4 +3 +2 +1
LS B
Figure 3. Left Justified up to 24-Bit Data
LR C K
R ig h t C h a n n e l
L e ft C h a n n e l
S C LK
SDATA
M SB
LSB
+1 +2 +3 +4 +5
3 2 c lo ck s
-7 -6 -5 -4 -3 -2 -1
M SB
LSB
+1 +2 +3 +4 +5
-7 -6 -5 -4 -3 -2 -1
M SB
Figure 4. Right Justified Data
3.4 De-Emphasis Control
The device includes on-chip digital de-emphasis. Figure 5 shows the de-emphasis curve for Fs equal to
44.1 kHz. The frequency response of the de-emphasis curve will scale proportionally with changes in sample rate, Fs. De-emphasis is not available in double-speed mode.
Gain
dB
T1=50 µs
0dB
T2 = 15 µs
-10dB
F1
3.183 kHz
F2
Frequency
10.61 kHz
Figure 5. De-Emphasis Curve
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CS43L43
3.4.1 Stand-Alone Mode
When using Internal Serial Clock (see section 3.2.1), pin 3 is available for de-emphasis control and
selects the 44.1 kHz de-emphasis filter. Please see Table 6 for the desired de-emphasis control.
DEM
DESCRIPTION
0
1
Disabled
44.1 kHz
Table 6. De-Emphasis Control
3.4.2 Control Port Mode
The Mode Control bits select either the 32, 44.1, or 48 kHz de-emphasis filter. Please see section
5.7.4 for the desired de-emphasis control.
3.5 Recommended Power-up Sequence
3.5.1 Stand-Alone Mode
1. Hold RST low until the power supply and configuration pins are stable, and the master and
left/right clocks are locked to the appropriate frequences, as discussed in section 3.2. In this state, the
control port is reset to its default settings and VQ_HP will remain low.
2. Bring RST high. The device will remain in a low power state with VQ_HP low and will initiate
the Stand-Alone power-up sequence after approximately 1024 LRCK cycles.
3.5.2 Control Port Mode
1. Hold RST low until the power supply is stable, and the master and left/right clocks are locked to
the appropriate frequences, as discussed in section 3.2. In this state, the control port is reset to its default settings and VQ_HP will remain low.
2. Bring RST high. The device will remain in a low power state with VQ_HP low. The control port
will be accessible at this time.
3. Wait approximately 2 LRCK cycles and then perform an I2C write to the CP_EN bit prior to the
completion of approximately 1024 LRCK cycles. The desired register settings can be loaded while
keeping the PDN bit set to 1.
4. Set the PDN bit to 0. This will initiate the power-up sequence, which lasts approximately 50 µS
when the POR bit is set to 0. If the POR bit is set to 1, see Section 3.6 for for a complete description
of power-up timing.
3.6 Popguard® Transient Control
The CS43L43 uses Popguard® technology to minimize the effects of output transients during power-up
and power-down. This technology, when used with external DC-blocking capacitors in series with the audio outputs, minimizes the audio transients commonly produced by single-ended single-supply converters.
It is activated inside the DAC when the RST pin is enabled/disabled and requires no other external control,
aside from choosing the appropriate DC-blocking capacitors.
DS479PP3
9
CS43L43
3.6.1 Power-up
When the device is initially powered-up, the audio outputs, HP_A and HP_B, are clamped to GND.
Following a delay of approximately 1000 sample periods, each output begins to ramp toward the quiescent voltage. Approximately 10,000 LRCK cycles later, the outputs reach VQ and audio output begins. This gradual voltage ramping allows time for the external DC-blocking capacitors to charge to
the quiescent voltage, minimizing the power-up transient.
3.6.2 Power-down
To prevent transients at power-down, the device must first enter its power-down state by setting the
RST pin low. When this occurs, audio output ceases and the internal output buffers are disconnected
from HP_A and HP_B. In their place, a soft-start current sink is substituted which allows the
DC-blocking capacitors to slowly discharge. Once this charge is dissipated, the power to the device
may be turned off and the system is ready for the next power-on.
3.6.3 Discharge Time
To prevent an audio transient at the next power-on, the DC-blocking capacitors must fully discharge
before turning on the power or exiting the power-down state. If full discharge does not occur, a transient will occur when the audio outputs are initially clamped to GND. The time that the device must
remain in the power-down state is related to the value of the DC-blocking capacitance and the output
load. For example, with a 220 µF capacitor and a 16 Ω load, the minimum power-down time will be
approximately 0.4 seconds.
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CS43L43
3.6.4 Auxilliary Mute Control
For critical applications, the Popguard® Transient Control may not be sufficient in eliminating extraneous audible artifacts on the headphone outputs during power-up. For these applications, an optional external mute can be used to maintain an absolute minimum of extraneous clicks and pops. Please
see Figures 6 and 7 for the suggested headphone mute circuit.
The Mute Control will need to be generated externally from a DSP or Microcontroller. See Figure 7
for /RST and Mute Control timing.
T he M otorola M O SFET s show n have been
tested to w ork properly, how ever, an
equivalent device m ay be used.
M G S F1N H 02E LT
H eadphones
2 2 0uF
47u H
From C S 43L43 P in
1 0 (H P _A )
1k
16
M G S F1N H 02E LT
2 2 0uF
47u H
From C S 43L43 P in
1 4 (H P _B )
1k
16
M ute C ontrol from uC or D S P
100K
Figure 6. Optional Headphone Mute Circuit
H eadphone O utput at
pin of part
~ 3 0 0 m sec
/R ST
~ 9 0 0 m sec
M ute C ontrol from
D SP or
M icroC ontroller
Figure 7. Timing for Headphone Mute
DS479PP3
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CS43L43
3.7 Grounding and Power Supply Arrangements
As with any high resolution converter, the CS43L43 requires careful attention to power supply and grounding arrangements if its potential performance is to be realized. Figure 1 shows the recommended power
arrangements, with VA, VA_HP & VL connected to clean supplies. If the ground planes are split between
digital ground and analog ground, the GND pins of the CS43L43 should be connected to the analog ground
plane.
All signals, especially clocks, should be kept away from the FILT+ and VQ pins in order to avoid unwanted coupling into the modulators. The CDB43L43 evaluation board demonstrates the optimum layout and
power supply arrangements.
Notes: The headphone outputs may clip when the value of VA_HP is below VA. It is recommended that these two
supplies be tied together.
3.7.1 Capacitor Placement
Decoupling capacitors should be as close to the DAC as possible, with the low value ceramic capacitor being the closest. The FILT+ and VQ decoupling capacitors must be positioned to minimize the
electrical path from FILT+ to REF_GND (and VQ to REF_GND). To further minimze impedance,
these capacitors should be located on the same layer as the DAC.
3.8 Control Port Interface
The control port is used to load all the internal register settings. Data is clocked into and out of the bi-directional serial control data line, SDA, by the serial control port clock, SCL (see Figure 8 for the clock to
data relationship). The operation of the control port may be completely asynchronous with the audio sample rate. However, to avoid potential interference problems, the control port pins should remain static if no
operation is required.
Notes: LRCK & MCLK must always be applied to pins 1 & 5, respectively, during any communication with the
control port.
3.8.1 Enabling the Control Port
The control port pins are shared with the stand-alone configuration pins. To dedicate these pins to
control port functionality, enable the control port prior to the completion of the stand-alone power up
sequence (see section 3.5 for the Recommended Power-up Sequence). To enable the control port,
write 1 to the CP_EN bit using the I2C protocol (see section 3.8.3).
Notes: Setting the CP_EN bit after the Stand-Alone power-up sequence has completed can cause audible
artifacts.
3.8.2 MAP Auto Increment
The device has MAP (memory address pointer) auto increment capability enabled by the INCR bit
(also the MSB) of the MAP. If INCR is set to 0, MAP will stay constant for successive I2C writes or
reads. If INCR is set to 1, MAP will auto increment after each byte is written, allowing block reads
or writes of successive registers.
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CS43L43
3.8.3 I2C Write
To write to the device, follow the procedure below while adhering to the control port Switching Specifications in section 6.
1) Initiate a START condition to the I2C bus followed by the address byte, 00100000. The eighth bit
of the address byte is the R/W bit.
2) Wait for an acknowledge (ACK) from the part, then write to the memory address pointer, MAP.
This byte points to the register to be written.
3) Wait for an acknowledge (ACK) from the part, then write the desired data to the register pointed
to by the MAP.
4) If the INCR bit (see section 3.8.2) is set to 1, repeat the previous step until all the desired registers
are written, then initiate a STOP condition to the bus.
5) If the INCR bit is set to 0 and further I2C writes to other registers are desired, it is necessary to
initiate a repeated START condition and follow the procedure detailed from step 1. If no further
writes to other registers are desired, initiate a STOP condition to the bus.
3.8.4 I2C Read
To read from the device, follow the procedure below while adhering to the control port Switching
Specifications.
1) Initiate a START condition to the I2C bus followed by the address byte, 00100001. The eighth bit
of the address byte is the R/W bit.
2) After transmitting an acknowledge (ACK), the device will then transmit the contents of the register pointed to by the MAP. The MAP will contain the address of the last register written to the MAP,
or the default address (see section 3.9) if an I2C read is the first operation performed on the device.
3) Once the device has transmitted the contents of the register pointed to by the MAP, issue an ACK.
4) If the INCR bit is set to 1, the device will continue to transmit the contents of successive registers.
Continue providing a clock and issue an ACK after each byte until all the desired registers are read,
then initiate a STOP condition to the bus.
5) If the INCR bit is set to 0 and further I2C reads from other registers are desired, it is necessary to
initiate a repeated START condition and follow the procedure detailed from step 1. If no further reads
from other registers are desired, initiate a STOP condition to the bus.
NOTE
SDA
0010000
R /W
ACK
D ATA
1 -8
ACK
DATA
1 -8
ACK
SCL
S ta rt
S to p
N O T E : If o p e ra tio n is a w rite , th is b y te c o n ta in s th e M e m o ry A d d re s s P o in te r, M A P . If
o p e ra tio n is a re a d , th is b y te c o n ta in s th e d a ta o f th e re g is te r p o in te d to b y th e M A P .
Figure 8. Control Port Timing
DS479PP3
13
CS43L43
3.9 Memory Address Pointer (MAP)
7
INCR
0
6
Reserved
0
5
Reserved
0
4
Reserved
0
3
MAP3
0
2
MAP2
0
1
MAP1
0
0
MAP0
0
3.9.1 INCR (Auto Map Increment Enable)
Default = ‘0’
0 - Disabled
1 - Enabled
3.9.2 MAP0-3 (Memory Address Pointer)
Default = ‘0000’
4.0 REGISTER QUICK REFERENCE
Addr
0h
Function
Reserved
default
1h
Power and Muting
Control
default
2h
Channel A Analog
Attenuation Control
default
3h
Channel B Analog
Attenuation Control
default
4h
Channel A Digital
Volume Control
default
5h
Channel B Digital
Volume Control
default
6h
Tone Control
7h
Mode Control
default
default
8h
Limiter Attack Rate
default
9h
Limiter Release Rate
default
Ah
Volume and Mixing
Control
default
Bh
Mode Control 2
default
14
7
6
5
4
3
2
1
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0
0
0
0
0
0
0
0
AMUTE
SZC1
SZC0
POR
Reserved
Reserved
PDN
CP_EN
1
1
0
1
0
0
1
0
VOLA7
VOLA6
VOLA5
VOLA4
VOLA3
VOLA2
VOLA1
VOLA0
0
0
0
0
0
0
0
0
VOLB7
VOLB6
VOLB5
VOLB4
VOLB3
VOLB2
VOLB1
VOLB0
0
0
0
0
0
0
0
0
DVOLA7
DVOLA6
DVOLA5
DVOLA4
DVOLA3
DVOLA2
DVOLA1
DVOLA0
0
0
0
0
0
0
0
0
DVOLB7
DVOLB6
DVOLB5
DVOLB4
DVOLB3
DVOLB2
DVOLB1
DVOLB0
0
0
0
0
0
0
0
0
BB3
BB2
BB1
BB0
TB3
TB2
TB1
TB0
0
0
0
0
0
0
0
0
BBCF1
BBCF0
TBCF1
TBCF0
A=B
DEM1
DEM0
VCBYP
0
0
0
0
0
0
0
0
ARATE7
ARATE6
ARATE5
ARATE4
ARATE3
ARATE2
ARATE1
ARATE0
0
0
0
1
0
0
0
0
RRATE7
RRATE6
RRATE5
RRATE4
RRATE3
RRATE2
RRATE1
RRATE0
0
0
1
0
0
0
0
0
TC1
TC0
TC_EN
LIM_EN
ATAPI3
ATAPI2
ATAPI1
ATAPI0
0
0
0
0
1
0
0
1
Reserved
Reserved
Reserved
DIF2
DIF1
DIF0
0
0
0
0
0
0
MCLKDIV Reserved
0
0
DS479PP3
CS43L43
5.0 REGISTER DESCRIPTIONS
5.1 POWER AND MUTING CONTROL (ADDRESS 01H)
7
AMUTE
1
6
SZC1
1
5
SZC0
0
4
POR
1
3
RESERVED
0
2
RESERVED
0
1
PDN
1
0
CP_EN
0
5.1.1 AUTO-MUTE (AMUTE) BIT 7
Default = 1
0 - Disabled
1 - Enabled
Function:
The Digital-to-Analog converter output will mute following the reception of 8192 consecutive audio samples of static 0 or -1. A single sample of non-static data will release the mute. Detection and muting is
done independently for each channel. The quiescent voltage on the output will be retained. The muting
function is affected, similar to volume control changes, by the Soft and Zero Cross bits in the Power and
Muting Control register.
5.1.2 SOFT RAMP AND ZERO CROSS CONTROL (SZC) BIT 5-6
Default = 10
00 - Immediate Change
01 - Zero Cross Digital and Analog
10 - Ramped Digital and Analog
11 - Reserved
Function:
Immediate Change
When Immediate Change is selected all level changes will take effect immediately in one step.
Zero Cross Digital and Analog
Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will occur
on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a
timeout period of 512 sample periods (10.7 ms at 48 kHz sample rate) if the signal does not encounter a
zero crossing. The zero cross function is independently monitored and implemented for each channel.
Ramped Digital and Analog
Soft Ramp allows digital level changes, both muting and attenuation, to be implemented by incrementally
ramping, in 1/8 dB steps, from the current level to the new level at a rate of 1dB per 8 left/right clock periods. Analog level changes will occur in 1 dB steps on a signal zero crossing. The analog level change
will occur after a timeout period of 512 sample periods (10.7 ms at 48 kHz sample rate) if the signal does
not encounter a zero crossing. The zero cross function is independently monitored and implemented for
each channel.
NOTE: Ramped Digital and Analog is not available in Double-Speed mode.
DS479PP3
15
CS43L43
5.1.3 POPGUARD® TRANSIENT CONTROL (POR) BIT 4
Default - 1
0 - Disabled
1 - Enabled
Function:
The Popguard® Transient Control allows the quiescent voltage to slowly ramp to and from 0 volts to the
quiescent voltage during power-on or power-off when this feature is enabled. Please see section 3.6 for
implementation details.
5.1.4 POWER DOWN (PDN) BIT 1
Default = 1
0 - Disabled
1 - Enabled
Function:
The entire device will enter a low-power state whenever this function is enabled, but the contents of the
control registers will be retained in this mode. The power-down bit defaults to ‘enabled’ on power-up and
must be disabled before normal operation will begin.
5.1.5 CONTROL PORT ENABLE (CP_EN) BIT 0
Default = 0
0 - Disabled
1 - Enabled
Function:
The Control Port will become active and reset to the default settings when this function is enabled.
16
DS479PP3
CS43L43
5.2 CHANNEL A ANALOG ATTENUATION CONTROL (ADDRESS 02H) (VOLA)
5.3 CHANNEL B ANALOG ATTENUATION CONTROL (ADDRESS 03H) (VOLB)
7
VOLx7
0
6
VOLx6
0
5
VOLx5
0
4
VOLx4
0
3
VOLx3
0
2
VOLx2
0
1
VOLx1
0
0
VOLx0
0
Default = 0 dB (No attenuation)
Function:
The Analog Attenuation Control operates independently from the Digital Volume Control. The Analog Attenuation Control registers allow the user to attenuate the headphone output signal in 1 dB increments
from 0 to -25 dB, using the analog volume control. Attenuation settings are decoded as shown in Table 7,
using a 2’s complement code. The volume changes are implemented as dictated by the Soft and Zero
Cross bits in the Power and Muting Control register. All volume settings greater than zero are interpreted
as zero.
Binary Code
00000000
11110110
11110001
Decimal Value
0
-10
-15
Volume Setting
0 dB
-10 dB
-15 dB
Table 7. Example Analog Volume Settings
NOTE: When the Analog Headphone Attenuation Control registers are set for attenuation levels greater
than -10dB, the actual attenuation deviates from the register setting by more than 1dB.
DS479PP3
17
CS43L43
5.4 CHANNEL A DIGITAL VOLUME CONTROL (ADDRESS 04H) (DVOLA)
5.5 CHANNEL B DIGITAL VOLUME CONTROL (ADDRESS 05H) (DVOLB)
7
DVOLx7
0
6
DVOLx6
0
5
DVOLx5
0
4
DVOLx4
0
3
DVOLx3
0
2
DVOLx2
0
1
DVOLx1
0
0
DVOLx0
0
Default = 0 dB (No attenuation)
Function:
The Digital Volume Control allows the user to alter the signal level in 1 dB increments from +18 to -96 dB,
using the Digital Volume Control. Volume settings are decoded as shown in Table 8, using a 2’s complement code. The volume changes are implemented as dictated by the Soft and Zero Cross bits in the Power and Muting Control register. All volume settings less than - 96 dB are equivalent to muting the channel
via the ATAPI bits (See Section 5.10.4).
NOTE: Setting this register to values greater than +18 dB will cause distortion in the audio outputs.
Binary Code
00001010
00000111
00000000
11000100
10100110
Decimal Value
12
7
0
-60
-90
Volume Setting
+12 dB
+7 dB
0 dB
-60 dB
-90 dB
Table 8. Example Digital Volume Settings
5.6 TONE CONTROL (ADDRESS 06H)
7
BB3
0
6
BB2
0
5
BB1
0
4
BB0
0
3
TB3
0
2
TB2
0
1
TB1
0
0
TB0
0
5.6.1 BASS BOOST LEVEL (BB) BIT 4-7
Default = 0 dB (No Bass Boost)
Function:
The level of the shelving bass boost filter is set by Bass Boost Level. The level can be adjusted in 1 dB
increments from 0 to +12 dB of boost. Boost levels are decoded as shown in Table 9. Levels above
+12 dB are interpreted as +12 dB.
Binary Code
0000
0010
0110
1001
1100
Decimal Value
0
2
6
9
12
Boost Setting
0 dB
+2 dB
+6 dB
+9 dB
+12 dB
Table 9. Example Bass Boost Settings
18
DS479PP3
CS43L43
5.6.2 TREBLE BOOST LEVEL (TB) BIT 0-3
Default = 0 dB (No Treble Boost)
Function:
The level of the shelving treble boost filter is set by Treble Boost Level. The level can be adjusted in 1 dB
increments from 0 to +12 dB of boost. Boost levels are decoded as shown in Table 10. Levels above
+12 dB are interpreted as +12 dB.
NOTE: Treble Boost is not available in Double-Speed Mode.
Binary Code
0000
0010
1010
1001
1100
Decimal Value
0
2
6
9
12
Boost Setting
0 dB
+2 dB
+6 dB
+9 dB
+12 dB
Table 10. Example Treble Boost Settings
5.7 MODE CONTROL (ADDRESS 07H)
7
BBCF1
0
6
BBCF0
0
5
TBCF1
0
4
TBCF0
0
3
A=B
0
2
DEM1
0
1
DEM0
0
0
VCBYP
0
5.7.1 BASS BOOST CORNER FREQUENCY (BBCF) BIT 6-5
Default = 00
00 - 50 Hz
01 - 100 Hz
10 - 200 Hz
11 - Reserved
Function:
The bass boost corner frequency is user selectable as shown above.
5.7.2 TREBLE BOOST CORNER FREQUENCY (TBCF) BIT 4-5
Default = 00
00 - 2 kHz
01 - 4 kHz
10 - 7 kHz
11 - Reserved
Function:
The treble boost corner frequency is user selectable as shown above. NOTE: Treble Boost is not available in Double-Speed Mode.
DS479PP3
19
CS43L43
5.7.3 CHANNEL A VOLUME = CHANNEL B VOLUME (A=B) BIT 3
Default = 0
0 - Disabled
1 - Enabled
Function:
The HP_A and HP_B volume levels are independently controlled by the A and B Channel Volume Control
Bytes when this function is disabled. The volume on both HP_A and HP_B are determined by the A Channel Attenuation and Volume Control Bytes. The B Channel Bytes are ignored when this function is enabled.
5.7.4 DE-EMPHASIS CONTROL (DEM) BIT 1-2
Default = 00
00 - Disabled
01 - 44.1 kHz
10 - 48 kHz
11 - 32 kHz
Function:
Selects the appropriate digital filter to maintain the standard 15 µs/50 µs digital de-emphasis filter response at 32, 44.1 or 48 kHz sample rates. (See Figure 5) NOTE: De-emphasis is not available in Double-Speed Mode.
5.7.5 DIGITAL VOLUME CONTROL BYPASS (VCBYP) BIT 0
Default = 0
0 - Disabled
1 - Enabled
Function:
When this function is enabled the digital volume control section is bypassed. This disables the digital volume control, muting, bass boost, treble boost, limiting and ATAPI functions. The analog attenuation control will remain functional.
20
DS479PP3
CS43L43
5.8 LIMITER ATTACK RATE (ADDRESS 08H) (ARATE)
7
ARATE7
0
6
ARATE6
0
5
ARATE5
0
4
ARATE4
1
3
ARATE3
0
2
ARATE2
0
1
ARATE1
0
0
ARATE0
0
Default = 10h - 2 LRCK’s per 1/8 dB
Function:
The limiter attack rate is user selectable. The rate is a function of sampling frequency, Fs, and the value
in the Limiter Attack Rate register. Rates are calculated using the function RATE = 32/{value}. Where
{value} is the decimal value in the Limiter Attack Rate register and RATE is in LRCK’s per 1/8 dB of
change. NOTE: A value of zero in this register is not recommended, as it will induce erratic behavior of
the limiter. Use the LIM_EN bit to disable the limiter function (see Section 5.10.3).
Binary Code
00000001
00010100
00101000
00111100
01011010
Decimal Value
1
20
40
60
90
LRCK’s per 1/8 dB
32
1.6
0.8
0.53
0.356
Table 11. Example Limiter Attack Rate Settings
5.9 LIMITER RELEASE RATE (ADDRESS 09H) (RRATE)
7
RRATE7
0
6
RRATE6
0
5
RRATE5
1
4
RRATE4
0
3
RRATE3
0
2
RRATE2
0
1
RRATE1
0
0
RRATE0
0
Default = 20h - 16 LRCK’s per 1/8 dB
Function:
The limiter release rate is user-selectable. The rate is a function of sampling frequency, Fs, and the value
in Limiter Release Rate register. Rates are calculated using the function RATE = 512/{value}. Where {value} is the decimal value in the Limiter Release Rate register and RATE is in LRCK’s per 1/8 dB of change.
NOTE: A value of zero in this register is not recommended, as it will induce erratic behavior of the limiter.
Use the LIM_EN bit to disable the limiter function (see Section 5.10.3).
Binary Code
00000001
00010100
00101000
00111100
01011010
Decimal Value
1
20
40
60
90
LRCK’s per 1/8 dB
512
25
12
8
5
Table 12. Example Limiter Release Rate Settings
DS479PP3
21
CS43L43
5.10 VOLUME AND MIXING CONTROL (ADDRESS 0AH)
7
TC1
0
6
TC0
0
5
TC_EN
0
4
LIM_EN
0
3
ATAPI3
1
2
ATAPI2
0
1
ATAPI1
0
0
ATAPI0
1
5.10.1 TONE CONTROL MODE (TC) BIT 6-7
Default = 00
00 - All settings are taken from user registers
01 - 12 dB of Bass Boost at 100 Hz and 6 dB of Treble Boost at 7 kHz
10 - 8 dB of Bass Boost at 100 Hz and 4 dB of Treble Boost at 7 kHz
11 - 4 dB of Bass Boost at 100 Hz and 2 dB of Treble Boost at 7 kHz
Function:
The Tone Control Mode bits determine how the Bass Boost and Treble Boost features are configured.
The user-defined settings from the Bass and Treble Boost Level and Corner Frequency registers are used
when these bits are set to ‘00’. Alternatively, one of three pre-defined settings may be used.
5.10.2 TONE CONTROL ENABLE (TC_EN) BIT 5
Default = 0
0 - Disabled
1 - Enabled
Function:
The Bass Boost and Treble Boost features are active when this function is enabled.
5.10.3 PEAK SIGNAL LIMITER ENABLE (LIM_EN) BIT 4
Default = 0
0 - Disabled
1 - Enabled
Function:
The CS43L43 will limit the maximum signal amplitude to prevent clipping when this function is enabled.
Peak Signal Limiting is performed by first decreasing the Bass and Treble Boost Levels. If the signal is
still clipping, then the digital attenuation is increased. The attack rate is determined by the Limiter Attack
Rate register.
Once the signal has dropped below the clipping level, the attenuation is decreased back to the user selected level and then, the Bass Boost is increased back to the user selected level. The release rate is
determined by the Limiter Release Rate register.
NOTE: The A=B bit should be set to ‘1’ for optimal limiter performance.
22
DS479PP3
CS43L43
5.10.4 ATAPI CHANNEL MIXING AND MUTING (ATAPI) BIT 0-3
Default = 1001 - HP_A = L, HP_B = R (Stereo)
Function:
The CS43L43 implements the channel mixing functions of the ATAPI CD-ROM specification. Refer to Table 13 and Figure 9 for additional information.
NOTE: All mixing functions occur prior to the digital volume control.
ATAPI3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
ATAPI2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
ATAPI1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
ATAPI0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
HP_A
MUTE
MUTE
MUTE
MUTE
R
R
R
R
L
L
L
L
[(L+R)/2]
[(L+R)/2]
[(L+R)/2]
[(L+R)/2]
HP_B
MUTE
R
L
[(L+R)/2]
MUTE
R
L
[(L+R)/2]
MUTE
R
L
[(L+R)/2]
MUTE
R
L
[(L+R)/2]
Table 13. ATAPI Decode
Left Channel
Audio Data
Channel A
Digital
Volume
Control
EQ
Analog
Volume
Control
MUTE
HP_A
Channel B
Digital
Volume
Control
EQ
Analog
Volume
Control
MUTE
HP_B
Σ
Right Channel
Audio Data
Figure 9. ATAPI Block Diagram
DS479PP3
23
CS43L43
5.11 MODE CONTROL 2 (ADDRESS 0BH)
7
MCLKDIV
0
6
RESERVED
0
5
RESERVED
0
4
RESERVED
0
3
RESERVED
0
2
DIF2
0
1
DIF1
0
0
DIF0
0
5.11.1 MASTER CLOCK DIVIDE ENABLE (MCLKDIV) BIT 7
Default = 0
0 - Disabled
1 - Enabled
Function:
The MCLKDIV bit enables a circuit which divides the externally applied MCLK signal by 2 prior to all other
internal circuitry.
NOTE: Internal SCLK is not available when this function is enabled.
5.11.2 DIGITAL INTERFACE FORMAT (DIF) BIT 0-2
Default = 000 - Format 0 (I2S, up to 24-bit data, 64 x Fs Internal SLCK)
Function:
The required relationship between the Left/Right clock, serial clock and serial data is defined by the Digital
Interface Format and the options are detailed in Figures 2-4.
NOTE: Internal SCLK is not available when MCLKDIV is enabled.
DIF2
0
0
0
0
1
1
1
1
DIF1
0
0
1
1
0
0
1
1
DIF0
0
1
0
1
0
1
0
1
DESCRIPTION
I2S, up to 24-bit data, 64 x Fs Internal SLCK
I2S, up to 16-bit data, 32 x Fs Internal SLCK
Left Justified, up to 24-bit data,
Right Justified, 24-bit data
Right Justified, 20-bit data
Right Justified, 16-bit data
Right Justified, 18-bit data
Identical to Format 1
Format
0
1
2
3
4
5
6
1
FIGURE
2
2
3
4
4
4
4
2
Table 14. Digital Interface Format - Control Port Mode
24
DS479PP3
CS43L43
6.0 CHARACTERISTICS AND SPECIFICATIONS
ANALOG CHARACTERISTICS (CS43L43-KZ, KZZ) (Test conditions (unless otherwise
specified): Input test signal is a 997 Hz sine wave at 0 dBFS; measurement bandwidth is 10 Hz to 20 kHz; test load
RL = 16Ω, CL = 10 pF (see Figure 10). Typical performance characteristics are derived from measurements taken
at TA = 25°C, VL = VA_HP = VA = 3.0V and 1.8V. Min/Max performance characteristics are guaranteed over the
specified operating temperature and voltages.)
VA = 3.0V
Parameter
Single-Speed Mode
Dynamic Range
18 to 24-Bit
16-Bit
Total Harmonic Distortion + Noise
18 to 24-Bit
16-Bit
Double-Speed Mode
Dynamic Range
18 to 24-Bit
16-Bit
Total Harmonic Distortion + Noise
18 to 24-Bit
16-Bit
DS479PP3
VA = 1.8V
Min
Typ
Max
Min
Typ
Max
Unit
88
90
-
91
93
89
91
-
85
88
-
88
91
86
89
-
dB
dB
dB
dB
-
-76
-71
-31
-74
-69
-29
-71
-
-
-82
-68
-28
-80
-66
-26
-77
-
dB
dB
dB
dB
dB
dB
88
90
-
92
94
90
92
-
85
88
-
89
92
87
90
-
dB
dB
dB
dB
-
-73
-72
-32
-71
-70
-30
-68
-
-
-85
-69
-29
-83
-67
-27
-80
-
dB
dB
dB
dB
dB
dB
Fs = 48kHz
(Note 1)
unweighted
A-Weighted
unweighted
A-Weighted
(Note 1)
0 dB
-20 dB
-60 dB
0 dB
-20 dB
-60 dB
Fs = 96kHz
(Note 1)
unweighted
A-Weighted
unweighted
A-Weighted
(Note 1)
0 dB
-20 dB
-60 dB
0 dB
-20 dB
-60 dB
25
CS43L43
ANALOG CHARACTERISTICS (CS43L43-KZ, KZZ) (Continued)
Parameters
Min
Typ
Max
Units
-
66
-
dB
Interchannel Gain Mismatch
-
0.1
-
dB
Gain Drift
-
±100
-
ppm/°C
0.5•VA
0.55•VA
0.6•VA
Vpp
Dynamic Performance for All Speed Modes
Interchannel Isolation
(1 kHz)
DC Accuracy
Analog Output Characteristics
Full Scale Output Voltage
Notes: 1. One-half LSB of triangular PDF dither is added to data.
220 µF
HP_x
+
V
out
R
L
C
L
GND
Figure 10. Output Test Load
26
DS479PP3
CS43L43
COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE (The
filter characteristics and the X-axis of the response plots have been normalized to the sample rate (Fs) and can be
referenced to the desired sample rate by multiplying the given characteristic by Fs.)
Parameter
Min
Typ
Max
Unit
0
0
-
0.4535
0.4998
Fs
Fs
-0.02
-
+0.08
dB
0.5465
-
-
Fs
50
-
-
dB
Single-Speed Mode - (2kHz to 50kHz sample rates)
Passband
to -0.05 dB corner
to -3 dB corner
Frequency Response 10 Hz to 20 kHz
(Note 2)
StopBand
StopBand Attenuation
(Note 3)
Group Delay
Passband Group Delay Deviation
De-emphasis Error (Relative to 1 kHz)
(Note 4)
-
9/Fs
-
s
0 - 20 kHz
-
±0.36/Fs
-
s
Fs = 32 kHz
Fs = 44.1 kHz
Fs = 48 kHz
-
-
+0.2/-0.1
+0.05/-0.14
+0/-0.22
dB
0
0
-
0.4426
0.4984
Fs
Fs
0
-
+0.11
dB
0.577
-
-
Fs
55
-
-
dB
Double-Speed Mode - (50kHz to 100kHz sample rates)
Passband
to -0.1 dB corner
to -3 dB corner
Frequency Response 10 Hz to 20 kHz
StopBand
StopBand Attenuation
(Note 3)
Group Delay
Passband Group Delay Deviation
0 - 40 kHz
0 - 20 kHz
-
4/Fs
-
s
-
±1.39/Fs
±0.23/Fs
-
s
s
Notes: 2. Referenced to a 1 kHz, full-scale sine wave.
3. For Single-Speed Mode, the measurement bandwidth is 0.5465 Fs to 3 Fs.
For Double-Speed Mode, the measurement bandwidth is 0.577 Fs to 1.4 Fs.
4. De-emphasis is only available in Single-Speed Mode.
DS479PP3
27
Figure 11. Single-Speed Stopband Rejection
Figure 12. Single-Speed Transition Band
Figure 13. Single-Speed Transition Band (Detail)
Figure 14. Single-Speed Passband Ripple
0
0
-10
-10
-20
-20
-30
-30
-40
-40
Amplitude dB
Amplitude dB
CS43L43
-50
-60
-70
-60
-70
-80
-80
-90
-90
-100
-100
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
Frequency (normalized to Fs)
Figure 15. Double-Speed Stopband Rejection
28
-50
1.0
0.40
0.42
0.44
0.46
0.48
0.50
0.52
0.54
0.56
0.58
0.60
Frequency (normalized to Fs)
Figure 16. Double-Speed Transition Band
DS479PP3
CS43L43
0
0.30
-1
0.25
0.20
-2
0.15
0.10
-4
Amplitude dB
Amplitude dB
-3
-5
-6
-7
0.00
-0.05
-0.10
-0.15
-8
-0.20
-9
-0.25
-0.30
-10
0.45
0.05
0.46
0.47
0.48
0.49
0.50
0.51
0.52
0.53
0.54
Frequency (normalized to Fs)
Figure 17. Double-Speed Transition Band (Detail)
DS479PP3
0.55
0.00
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
Frequency (normalized to Fs)
Figure 18. Double-Speed Passband Ripple
29
CS43L43
SWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACE (Inputs: Logic “0” =
GND, Logic “1” = VL.)
Parameters
Symbol
Min
Max
Units
MCLK Frequency
1.024
51.2
MHz
MCLK Duty Cycle
45
55
%
2
50
50
100
kHz
kHz
40
60
%
External SCLK Mode
Input Sample Rate
Single-Speed Mode
Double-Speed Mode
Fs
Fs
LRCK Duty Cycle
SCLK Pulse Width Low
tsclkl
20
-
ns
SCLK Pulse Width High
tsclkh
20
-
ns
SCLK Period
tsclkw
-
s
-
MCLK
-----------------2
Hz
-
MCLK
-----------------4
Hz
SCLK Frequency
SCLK Frequency
(Note 10)
2
-----------------MCLK
SCLK rising to LRCK edge delay
tslrd
20
-
ns
SCLK rising to LRCK edge setup time
tslrs
20
-
ns
SDATA valid to SCLK rising setup time
tsdlrs
20
-
ns
SCLK rising to SDATA hold time
tsdh
20
-
ns
Notes: 5. This serial clock is required only in Control Port Mode when the MCLK Divide bit is enabled.
LR C K
t
t
slrd
t
slrs
t
sclkh
sclkl
S C LK
t
t
sdlrs
sd h
SDATA
Figure 19. External Se-
30
rial Mode Input Timing
DS479PP3
CS43L43
SWITCHING CHARACTERISTICS - INTERNAL SERIAL CLOCK (Inputs: Logic “0” =
GND, Logic “1” = VL.)
Parameters
Symbol
Min
Typ
Max
Units
-
50
-
%
-
-
s
tsclkw
-----------------2
-
s
Internal SCLK Mode
LRCK Duty Cycle
(Note 6)
SCLK Period
tsclkw
SCLK rising to LRCK edge
tsclkr
SDATA valid to SCLK rising setup time
tsdlrs
1
---------------------- + 10
( 512 )Fs
-
-
ns
Single-Speed Mode
tsdh
1
---------------------- + 15
( 512 )Fs
-
-
ns
Double-Speed Mode
tsdh
-
-
ns
SCLK rising to SDATA hold time
1
----------------SCLK
-
1
---------------------- + 15
( 384 )Fs
Notes: 6. In Internal SCLK Mode, the LRCK duty cycle must be 50% +/− 1/2 MCLK Period.
LRC K
t s c lk r
SDATA
t s c lk w
t s d lrs
t sdh
* IN T E R N A L
SCLK
Figure 20. Internal Serial
Mode Input Timing
*The SCLK pulses shown are internal to the CS43L43.
LR C K
M C LK
1
N
2
N
*IN TE R N A L S C LK
SD A TA
Figure 21. Internal Serial Clock Generation
* The SCLK pulses shown are internal to the CS43L43.
N equals MCLK divided by SCLK
DS479PP3
31
CS43L43
SWITCHING SPECIFICATIONS - CONTROL PORT INTERFACE
(Inputs: Logic “0” = GND, Logic “1” = VL.)
Parameter
Symbol
Min
Max
Unit
SCL Clock Frequency
fscl
-
100
kHz
RST Rising Edge to Start
tirs
1
--------------( 2 )Fs
-
s
Bus Free Time Between Transmissions
tbuf
4.7
-
µs
Start Condition Hold Time (prior to first clock pulse)
thdst
4.0
-
µs
Clock Low time
tlow
4.7
-
µs
Clock High Time
thigh
4.0
-
µs
Setup Time for Repeated Start Condition
tsust
4.7
-
µs
thdd
0
-
µs
tsud
250
-
ns
Rise Time of SCL
trc
-
25
ns
Fall Time of SCL
tfc
-
25
ns
Rise Time SDA
trd
-
1
µs
Fall Time of SDA
tfd
-
300
ns
tsusp
4.7
-
µs
2
I C Mode
SDA Hold Time from SCL Falling
(Note 7)
SDA Setup time to SCL Rising
Setup Time for Stop Condition
7. Data must be held for sufficient time to bridge the transition time, tfc, of SCL.
RST
t irs
Stop
R e p e a te d
S ta rt
S ta rt
Stop
SDA
t buf
t
t high
t hdst
tf
hdst
t susp
SCL
t
lo w
t
hdd
t sud
t sust
tr
Figure 22. Control Port Timing - I2C Mode
32
DS479PP3
CS43L43
DC ELECTRICAL CHARACTERISTICS (GND = 0V; all voltages with respect to GND.)
Parameters
Normal Operation (Note 8)
Power Supply Current
Power Supply Current
Total Power Dissipation
Power-down Mode (Note 9)
Power Supply Current
Power Supply Current
Total Power Dissipation
Symbol
Min
Typ
Max
Units
VA=1.8V
VA_HP=1.8V
VL=1.8V
VA=3.0V
VA_HP=3.0V
VL=3.0V
All Supplies=1.8V
All Supplies=3.0V
IA
IA_HP
ID_L
IA
IA_HP
ID_L
-
7.3
1.5
4
10.5
1.5
9.3
16
36
20
50
mA
mA
µA
mA
mA
µA
mW
mW
VA=1.8V
VA_HP=1.8V
VL=1.8V
VA=3.0V
VA_HP=3.0V
VL=3.0V
All Supplies=1.8V
All Supplies=3.0V
IA
IA_HP
ID_L
IA
IA_HP
ID_L
-
2.0
9.3
2.2
3.4
9.8
7.6
24.3
62.4
-
µA
µA
µA
µA
µA
µA
µW
µW
1 kHz
60 Hz
PSRR
-
60
40
0.5•VA
250
0.01
-
dB
dB
V
-
VA
250
0.01
-
All Modes of Operation
Power Supply Rejection Ratio (Note 10)
VQ Nominal Voltage
Output Impedance
Maximum allowable DC current source/sink
VQ_HP
Filt+ Nominal Voltage
Output Impedance
Maximum allowable DC current source/sink
kΩ
mA
V
kΩ
mA
DIGITAL INPUT CHARACTERISTICS AND SPECIFICATIONS (GND = 0V; all voltages
with respect to GND.)
Parameters
Input Leakage Current
Input Capacitance
High-Level Input Voltage
Low-Level Input Voltage
Symbol
Iin
VIH
VIL
Min
0.7 x VL
-
Typ
8
-
Max
±10
0.3 x VL
Units
µA
pF
V
V
THERMAL CHARACTERISTICS AND SPECIFICATIONS
Parameters
Symbol
Package Thermal Resistance
Ambient Operating Temperature
DS479PP3
(Power Applied)
Min
Typ
Max
Units
θJA
-
TA
-10
75
-
°C/Watt
-
+70
°C
33
CS43L43
RECOMMENDED OPERATING CHARACTERISTICS (GND = 0V; all voltages with respect
to GND.)
Parameters
Symbol
Min
Typ
Max
Units
VA
1.7
2.25
3.0
0.9
1.7
2.25
3.0
1.8
2.5
3.3
1.8
2.5
3.3
1.9
2.75
3.6
3.6
1.9
2.75
3.6
V
V
V
V
V
V
V
DC Power Supply
Analog
Headphone (Note 11)
Logic
VA_HP
VL
ABSOLUTE MAXIMUM RATINGS (GND = 0 V; all voltages with respect to AGND. Operation
beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these
extremes.)
Parameters
DC Power Supplies: Positive Analog
Headphone
Digital I/O
Input Current, Any Pin Except Supplies
Digital Input Voltage
Ambient Operating Temperature (power applied)
Storage Temperature
Symbol
VA
VA_HP
VL
Iin
VIND
TA
Tstg
Min
-0.3
-0.3
-0.3
-0.3
-55
-65
Max
4.0
4.0
4.0
±10
VL + 0.4
125
150
Units
V
V
V
mA
V
°C
°C
Notes: 8. Normal operation is defined as RST = HI with a 997 Hz, 0dBFS input sampled at Fs = 48kHz, and open
outputs, unless otherwise stated.
9. Power Down Mode is defined as RST = LO with all clocks and data lines held static.
10. Valid with the recommended capacitor values on FILT+ and VQ_HP as shown in Figure 1. Increasing
the capacitance will also increase the PSRR. NOTE: Care should be taken when selecting capacitor
type, as any leakage current in excess of 1.0 µA will cause degradation in analog performance.
11. To prevent clipping the outputs, VA_HPMIN is limited by the Full-Scale Output Voltage VFS_HP, where
VA_HP must be 200 mV greater than VFS_HP. However, if distortion is not a concern, VA_HP may be
as low as 0.9 V at any time.
34
DS479PP3
CS43L43
7.0 PARAMETER DEFINITIONS
Total Harmonic Distortion + Noise (THD+N)
The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified
bandwidth (typically 10Hz to 20kHz), including distortion components. Expressed in decibels.
Dynamic Range
The ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the
specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth made
with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement to full
scale. This technique ensures that the distortion components are below the noise level and do not affect the
measurement. This measurement technique has been accepted by the Audio Engineering Society,
AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307.
Interchannel Isolation
A measure of crosstalk between the left and right channels. Measured for each channel at the converter's
output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in decibels.
Interchannel Gain Mismatch
The gain difference between left and right channels. Units in decibels.
Gain Error
The deviation from the nominal full scale analog output for a full scale digital input.
Gain Drift
The change in gain value with temperature. Units in ppm/°C.
8.0 REFERENCES
1) CDB43L43 Evaluation Board Datasheet
2) “The I2C-Bus Specification: Version 2.1” Philips Semiconductors, January 2000.
http://www.semiconductors.philips.com
DS479PP3
35
CS43L43
9.0 PACKAGE DIMENSIONS
16L TSSOP PACKAGE DRAWING
N
D
E1
A2
E
A
∝
e
b
SIDE VIEW
A1
END VIEW
L
SEATING
PLANE
1 2 3
TOP VIEW
INCHES
DIM
A
A1
A2
b
D
E
E1
e
L
∝
MIN
-0.002
0.033
0.008
--0.169
-0.020
0°
NOM
--0.035
-0.197
0.252
0.173
0.026
0.024
--
MILLIMETERS
MAX
0.043
0.006
0.037
0.012
--0.177
-0.028
8°
MIN
-0.05
0.85
0.19
--4.30
-0.50
0°
NOM
--0.90
-5.00
6.40
4.40
0.65
0.60
--
NOTE
MAX
1.10
0.15
0.95
0.30
--4.50
-0.70
8°
2,3
1
1
JEDEC #: MO-150
Notes: 1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold
mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per
side.
2. Dimension “b” does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be
0.13 mm total in excess of “b” dimension at maximum material condition. Dambar intrusion shall not
reduce dimension “b” by more than 0.07 mm at least material condition.
3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.
36
DS479PP3