Cirrus CS4953-CQ Ntsc/pal digital video encoder Datasheet

CS4952/53
NTSC/PAL Digital Video Encoder
Features
Description
l Simultaneous composite and S-video output
l Supports RS170A and CCIR601 composite
output timing
l Multi-standard support for NTSC-M, PAL (B, D,
G, H, I, M, N, Combination N)
l Optional progressive scan @ MPEG2 field rates
l CCIR656 input mode supporting EAV/SAV
codes and CCIR601 Master/Slave input modes
l Stable color subcarrier for MPEG2 systems
l NTSC closed caption encoder with interrupt
l Supports Macrovision copy protection in
CS4953 version
l Host interface configurable for parallel or I2C
compatible operation
l General purpose input and output pins
l Individual DAC power-down capability
l On-chip voltage reference generator
l On-chip color bar generator
l +5 volt only, CMOS, low power modes, tri-state
DACs
The CS4952/3 provides full conversion from YCbCr or
YUV digital video formats into NTSC & PAL Composite
and Y/C (S-video) analog video. Input formats can be
27 MHz 8-bit YUV, 8-bit YCbCr, or CCIR656 with support for EAV/SAV codes. Output video can be formatted
to be compatible with NTSC-M, or PAL B,D,G,H,I,M,N,
and Combination N systems. Also supported is NTSC
line 21 and line 284 closed captioning encoding.
Four 9-bit DACs provide two channels for an S-Video output port and two composite video outputs. 2x oversampling
reduces the output filter requirements and guarantees
no DAC related modulation components within the specified bandwidth of any of the supported video standards.
Parallel or high speed I2C compatible control interfaces
are provided for flexibility in system design. The parallel
interface doubles as a general purpose I/O port when the
CS4952/3 is in I2C mode to help conserve valuable
board area.
ORDERING INFORMATION
CS4952/3-CL 44 pin PLCC
CS4952/3-CQ 44 pin TQFP
VAA
CLK
I 2C
Interface
SCL
SDA
PDAT[7:0]
RD*
WR*
Output
Interpolate
Control
Registers
8
Host
Parallel
Interface
Chroma Amplifier
Chroma Modulate
Color Sub-carrier
Synthesizer
ADDR
XTAL
LPF
8
U, V
Y
Video
Formatter
C
9-Bit
DAC
CVBS37
9-Bit
DAC
CVBS75
9-Bit
DAC
Y
Σ
Burst Insert
Chroma Interpolate
VD[7:0]
9-Bit
DAC
LPF
Luma Delay
Luma Amplifier
HSYNC*
VSYNC*
FIELD
INT
Sync Insert
Video Timing
Generator
Output
Interpolate
LPF
Voltage
Reference
VREFIN
VREFOUT
Current
Reference
ISET
RESET*
GND
Preliminary Product Information
Cirrus Logic, Inc.
Crystal Semiconductor Products Division
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.crystal.com
TEST
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Copyright  Cirrus Logic, Inc. 1997
(All Rights Reserved)
OCT ‘97
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1
CS4952/53
TABLE OF CONTENTS
AC & DC PARAMETRIC SPECIFICATIONS .....................................................................4
INTRODUCTION ...............................................................................................................11
FUNCTIONAL DESCRIPTION .........................................................................................11
Video Timing Generator .........................................................................................11
Video Input Formatter .............................................................................................11
Color Subcarrier Synthesizer ..................................................................................12
Chroma Path ..........................................................................................................12
Luma Path ..............................................................................................................12
Digital to Analog Converters ...................................................................................13
Voltage Reference ..................................................................................................13
Current Reference ..................................................................................................13
Host Interface .........................................................................................................13
Closed Caption Services ........................................................................................13
Control Registers ....................................................................................................13
OPERATIONAL DESCRIPTION .......................................................................................14
Reset Hierarchy ......................................................................................................14
Video Timing ...........................................................................................................14
Slave Mode Input Interface .............................................................................14
Master Mode Input Interface ...........................................................................14
Vertical Timing .................................................................................................15
Horizontal Timing ............................................................................................15
NTSC Interlaced ..............................................................................................17
PAL Interlaced .................................................................................................17
Progressive Scan ............................................................................................19
PAL Progressive Scan ....................................................................................19
NTSC Progressive Scan .................................................................................19
CCIR-656 ................................................................................................................19
Digital Video Input Modes .......................................................................................22
Multi-standard Output Format Modes .....................................................................22
Subcarrier Generation ............................................................................................22
Subcarrier Compensation .......................................................................................22
Closed Caption Insertion ........................................................................................23
Color Bar Generator ...............................................................................................23
Interrupts ................................................................................................................24
General Purpose I/O Port .......................................................................................24
ANALOG ...........................................................................................................................24
Analog Timing .........................................................................................................24
VREF ......................................................................................................................25
ISET ........................................................................................................................25
DACs ......................................................................................................................25
Luminance DAC ..............................................................................................25
Chrominance DAC ..........................................................................................25
CVBS75 DAC ..................................................................................................26
CVBS37 DAC ..................................................................................................26
PROGRAMMING ..............................................................................................................27
Host Control Interface .............................................................................................27
I2C Interface ....................................................................................................27
8-bit Parallel Interface .....................................................................................27
Register Description ...............................................................................................28
Control Register 0 ............................................................................................28
Control Register 1 ............................................................................................29
Control Register 2 ............................................................................................30
DAC Power Down Register ..............................................................................30
Status Register.................................................................................................31
Background Color Register ..............................................................................31
GPIO Control Register .....................................................................................31
GPIO Data Register .........................................................................................32
Chroma Filter Register .....................................................................................32
Luma Filter Register .........................................................................................32
I2C Address Register .......................................................................................32
Subcarrier Amplitude Register .........................................................................33
2
DS223PP2
CS4952/53
Subcarrier Synthesis Register ......................................................................... 33
Hue LSB Adjust Register ................................................................................. 33
Hue MSB Adjust Register ................................................................................ 33
Closed Caption Enable Register...................................................................... 34
Closed Caption Data Register ......................................................................... 34
Interrupt Enable Register ................................................................................. 34
Interrupt Clear Register.................................................................................... 35
Device ID Register ........................................................................................... 35
BOARD DESIGN & LAYOUT CONSIDERATIONS ......................................................... 36
Power and Ground Planes ..................................................................................... 36
Power Supply Decoupling ...................................................................................... 36
VREF Decoupling ................................................................................................... 36
Digital Interconnect ................................................................................................ 36
Analog Interconnect ............................................................................................... 37
Analog Output Protection ....................................................................................... 37
ESD Protection ....................................................................................................... 37
External DAC Output Filter ..................................................................................... 37
DEVICE PINOUT - 44 PLCC ............................................................................................ 38
PLCC Pin Description ............................................................................................ 39
DEVICE PINOUT - 44 TQFP ............................................................................................ 41
TQFP Pin Description ............................................................................................ 42
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3
CS4952/53
AC & DC PARAMETRIC SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS: (AGND, DGND = 0 V, all voltages with respect to 0 V.)
Parameter
Power Supply
Input Current Per Pin
Output Current Per Pin
Symbol
VAA
Except Supply Pins
Except Supply Pins
Analog Input Voltage
Digital Input Voltage
Ambient Temperature
Storage Temperature
Min
Max
Units
-0.3
-10
-50
6.0
10
+50
VAA+0.3
V
mA
mA
VAA+0.3
V
°C
°C
-0.3
-0.3
-55
-65
Power Applied
+125
+150
V
Warning: Operating beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS: (AGND, DGND = 0 V, all voltages with
respect to 0 V.)
Parameter
Power Supplies: Digital Analog
Symbol
VAA
Operating Ambient Temperature
TA
4
Min
Typ
Max
Units
4.75
5.0
5.25
V
0
+25
+70
°C
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CS4952/53
D.C. CHARACTERISTICS:
(TA=25 C; VAA = 5 V; GND = 0 V.)
Parameter
Symbol
Digital Inputs
High Level Input Voltage
V [7:0], PDAT [7:0],
VIH
HSYNC/VSYNC/FIELD/CLKIN
VIH
High Level Input Voltage
I2C
Min
Typ
Max
Units
2.0
0.7VAA
-
VAA+0.3
V
-
-
V
All Inputs
Digital Inputs
VIL
-
-0.3
-10
-
0.8
+10
V
µA
High Level Output Voltage
Io = -4mA
VOH
2.4
-
VAA
V
Low Level Output Voltage
Io = 4mA
VOL
-
-
0.4
V
Low Level Output Voltage
Output Leakage Current
Analog Outputs
Full Scale Output Current
Full Scale Output Current
LSB Current
LSB Current
DAC-to-DAC Matching
SDA pin only, Io = 6mA
High-Z Digital Outputs
VOL
-10
-
0.4
+10
V
µA
CVBS37/Y/C (Note 1)
CVBS75 (Note 1)
CVBS37/Y/C (Note 1)
CVBS75 (Note 1)
32.9
16.4
64.5
32.2
-
34.7
17.3
68
34
2
36.5
18.2
71.5
35.8
-
mA
mA
µA
µA
%
Output Compliance
IO37
IO75
IB37
IB35
MAT
VOC
0
-
+1.4
V
Output Impedance
ROUT
-
15
-
kΩ
Output Capacitance
COUT
-
-
30
pF
DAC Output Delay
ODEL
-
4
12
ns
DAC Rise/Fall Time
Voltage Reference
TRF
-
2.5
5
ns
Reference Voltage Output
VOV
1.198
1.232
1.272
V
Reference Input Current
Power Supply
IVC
-
-
10
µA
Supply Voltage
VAA
4.75
5
5.25
V
IAA1
IAA2
IAA3
-
180
110
75
200
-
mA
mA
mA
Low Level Input Voltage
Input Leakage Current
Digital Outputs
Supply Current
(Note 2)
All DACs on
CVBS75/CVGS37 only
CVBS75 only
-
Notes: 1. Output current levels with ISET = 10 kΩ, VREFIN = 1.232 V.
2. Times for black-to-white level and white-to-black level transitions.
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5
CS4952/53
D.C. CHARACTERISTICS (Continued)
Parameter
Static Performance
DAC Resolution
Differential Non-Linearity
Integral Non-Linearity
Dynamic Performance
Differential Gain
Differential Phase
Signal to Noise Ratio
Hue Accuracy
Saturation Accuracy
6
Symbol
Min
Typ
Max
Units
DNL
INL
-1
-1
±0.5
±0.35
9
+1
+1
Bits
LSB
LSB
DB
DP
SNR
HA
-70
2
±0.5
-
5
±2
-
%
°
dB
-
-
2
°
SA
-
-
2
%
DS223PP2
CS4952/53
A.C. CHARACTERISTICS:
Parameter
Pixel Input and Control Port
Symbol
Min
Typ
Max
Units
Clock Pulse High Time
Tch
14.82
18.52
22.58
ns
Clock Pulse Low Time
Tcl
14.82
18.52
22.58
ns
Clock to Data Set-up Time
Tisu
6
-
-
ns
Clock to Data Hold Time
Tih
0
-
-
ns
Clock to Data Output Delay
Toa
-
-
17
ns
Typ
Max
Units
1000
KHz
CLK
Tch
Tisu
Tcl
V[7:0]
Tih
HSYNC*/VSYNC*
(Inputs)
Toa
HSYNC*/VSYNC*/
CB/FIELD/INT
(Outputs)
Figure 1. Video Pixel Data and Control Port Timing
Parameter
Symbol
Min
SCL Frequency
Fclk
100
Clock Pulse High Time
Tsph
0.1
µs
Clock Pulse Low Time
Tspl
0.7
µs
Hold Time (Start Condition)
Tsh
100
ns
Setup Time (Start Condition)
Tssu
100
ns
Data Setup Time
Tsds
50
ns
Rise Time
Tsr
1
µs
Fall Time
Tsf
0.3
µs
Setup Time (Stop Condition)
Tss
100
ns
Bus Free Time
Tbuf
100
ns
Data Hold Time
Tdh
0
SCL Low to Data Out Valid
Tvdo
I2C
Host Port Timing
Tbuf
Tsh
ns
600
Tdh Tsds
Tsh
ns
Tss
SDA
Tsr
Tsph
Tvdo
SCL
Tspl
Tsf
Tssu
2
Figure 2. I C Host Port Timing
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7
CS4952/53
A.C. CHARACTERISTICS:
(Continued)
Parameter
8-bit Parallel Host Interface
Symbol
Min
Typ
Max
Units
Read Cycle Time
Trd
60
-
-
ns
Read Pulse Width
Trpw
30
-
-
ns
Address Setup Time
Tas
3
-
-
ns
Read Address Hold Time
Trah
10
-
-
ns
Read Data Access Time
Trda
-
-
40
ns
Read Data Hold Time
Trdh
10
-
50
ns
Write Recovery Time
Twr
60
-
-
ns
Write Pulse Width
Twpw
40
-
-
ns
Write Data Setup Time
Twds
8
-
-
ns
Write Data Hold Time
Twdh
3
-
-
ns
Write-Read/Read-Write Recovery Time
Trec
50
-
-
ns
Address from Write Hold Time
Twac
0
-
-
ns
Trd
RD*
Trpw
Trah
ADDR
PDAT[7:0]
Tas
Trda
Trdh
8-bit Parallel Host Port Timing: Read Cycle
Twpw
Twr
WR*
Twac
ADDR
PDAT[7:0]
Tas
Twds
Twdh
8-bit Parallel Host Port Timing: Address Write Cycle
WR*
Trec
Trec
RD*
8-bit Parallel Host Port Timing: Read-Write/Write-Read Cycle
Figure 3.
8
DS223PP2
CS4952/53
A.C. CHARACTERISTICS: (Continued)
Parameter
Symbol
Min
Tres
100
Typ
Max
Units
Reset Timing
Reset Pulse Width
ns
RESET*
Tres
Figure 4. Reset Timing
DS223PP2
9
CS4952/53
L1
Ferrite Bead
+5V
(Vcc)
4.7 µF
0.1 µF
1
18
NC
19
XTAL
ADDR
3 20 29
VAA
42
VREFOUT
41
VREFIN
8
GPIO Port
PDAT[7:0]
31
+5V (Vcc)
32
CVBS75
1.5kΩ
110Ω
I2 C
Controller
5
WR*
4
Composite Video
Connector
75Ω
35
36
SDA
CS4952
CS4953
Y
SCL
43
110Ω
75Ω
33
27 MHz Clock
To RF Modulator
75Ω
RD*
CVBS37
1.5kΩ
0.1 µF
8
Pixel Data
C
V[7:0]
44
7-14
15
16
17
6
S-Video
Connector
CLK
75Ω
FIELD
INT
HSYNC*/CB
VSYNC*
TEST
RESET*
GND
2 21 22 38
ISET
34
37
40
10 kΩ±1%
Figure 5. Typical Connection Diagram (I2C host interface)
10
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CS4952/53
INTRODUCTION
The CS4952/3 is a complete multi-standard digital
video encoder implemented in current 5-volt only
CMOS technology. CCIR601 or CCIR656 compliant digital video input can be converted into
NTSC-M, PAL B, PAL D, PAL G, PAL H, PAL I,
PAL M, PAL N, or PAL N Argentina-compatible
analog video. The CS4952/3 is designed to connect
to MPEG1 and MPEG2 digital video decompressors without glue logic.
Two 9-bit DAC outputs provide high quality
S-Video analog output while two other 9-bit DACs
simultaneously generate composite analog video.
The CS4952/3 will accept 8-bit YCbCr or 8-bit
YUV input data.
The CS4952/3 is completely configured and controlled via an 8-bit host interface port or an I2C
compatible serial interface. This host port provides
access and control of all CS4952/3 options and features like closed caption insertion, interrupts, etc.
In order to lower the end user set-top overall system costs, the CS4952/3 provides an internal voltage reference which eliminates the requirement for
an external discrete 3-pin voltage reference.
FUNCTIONAL DESCRIPTION
In the following subsections, the functions of the
CS4952/3 will be described. The descriptions refer
to the block diagram on the cover page.
Video Timing Generator
All timing generation is accomplished via a
27 MHz input applied to the CLK pin. The
CS4952/3 can also accept an optional color burst
crystal on the ADDR & XTAL pins. See section:
Color Subcarrier Synthesizer (page 12), for further
details.
The Video Timing Generator is responsible for orchestrating most all of the other modules in the device. It works in harmony with external sync input
timing or by providing external sync timing outDS223PP2
puts. It automatically disables color burst on appropriate scan lines and generates serration and
equalization pulses on appropriate scan lines.
The CS4952/3 is designed to function as a video
timing master or video timing slave. In both Master
and Slave Modes, all timing is sampled and asserted with the rising edge of the CLK pin.
In most cases the CS4952/3 will serve as the video
timing master. The master timing cannot be externally altered other than through the host interface
by changing the video display modes: PAL or
NTSC and Progressive Scan. HSYNC, VSYNC
and FIELD are configured as outputs for Master
Mode. HSYNC can also be defined as a composite
blanking output signal in Master Mode. Exact horizontal and vertical display timing is addressed in
section: Operational Description (page 14).
In Slave Mode HSYNC and VSYNC are configured as input pins and are used to initialize independent vertical and horizontal timing generators
upon their respective falling edges. FIELD remains
an output in Slave Mode.
The CS4952/3 also provides a CCIR-656 Slave
Mode where the video input stream contains EAV
and SAV codes. In this case, proper HSYNC
VSYNC timing is extracted automatically without
aid from any inputs other than the V [7:0].
CCIR-656 input data is sampled with the leading
edge of CLK. Slave Mode vertical and horizontal
timing derived via CCIR-656 or external hardware
must be equivalent to timing generated by the
CS4952/3 in Master Mode.
Video Input Formatter
The video input formatter translates YCbCr input
data into YUV information, if necessary, and splits
the luma and chroma information for filtering, scaling, and modulation.
11
CS4952/53
Color Subcarrier Synthesizer
The subcarrier synthesizer is a digital frequency
synthesizer that produces the correct subcarrier frequency for NTSC or PAL. The CS4952/3 generates
the color burst frequency based on the input CLK
(27 MHz). Color burst accuracy and stability are
limited by the accuracy of the 27 MHz input. If the
frequency varies then the color burst frequency will
also vary accordingly.
In order to handle situations in which the CLK varies unacceptably, a local crystal frequency reference may be used on the ADDR & XTAL device
pins. In this instance the input CLK is continuously
compared with the external crystal reference input
and the internal timing of the CS4952/3 is automatically adjusted so that the color burst frequency remains close to the requirements.
The output of the chroma low pass filter is connected to the chroma interpolation filter where upsampling from 4:2:2 to 4:4:4 is accomplished. The
chroma digital data is fed to a quadrature modulator
where they are combined with the output from the
subcarrier synthesizer to produce the proper modulated chrominance signal.
Following chroma modulation the chroma data
passes through a variable gain amplifier where the
chroma amplitude may be varied via the C_AMP
8-bit host addressable register. The chroma then is
interpolated by a factor of 2 in order to operate the
output DACs at 2 times the pixel rate. The interpolated filters help reduce the sinx/x roll-off for higher frequencies and reduce the complexity of the
external analog low pass filters.
Luma Path
Controls are provided for phase adjustment of the
burst to permit color adjustment and phase compensation. Chroma hue control is provided by the
CS4952/3 via a 10-bit Hue Control Register
(HUE_LSB and H_MSB). Burst amplitude control
is also made available to the host via the 8-bit burst
amplitude register (SC_AMP).
Along with the chroma output path, the CS4952/3
Video Input Formatter initiates a parallel luma data
path by directing the luma data to a digital delay
line. The delay line is built as a digital FIFO where
the depth of the FIFO replicates the clock period
delay associated with the more complex chroma
path.
Chroma Path
Following the luma delay, the data is passed
through a variable gain amplifier where the luma
DC values are modifiable via the Y_AMP register.
The Video Input Formatter at conclusion delivers
4:2:2 YUV outputs into separate chroma and luma
data paths. The chroma path will be discussed here.
The chroma output of the Video Input Formatter is
directed to a chroma low pass 19-tap FIR filter. The
filter bandwidth is selected or the filter may be bypassed via the CONTROL_1 register. The passband of the filter is either 650 KHz or 1.3 MHz and
the passband ripple is less than or equal to 0.05 dB.
The stopband for the 1.3 MHz selection begins at
3 MHz with an attenuation of greater that 35 dB.
The stopband for the 650 KHz selection begins
around 1.1 MHz with an attenuation of greater than
20 dB.
12
The output of the luma amplifier connects to the
sync insertion block. Sync insertion is accomplished by multiplexing into the luma data path the
different sync DC values at the appropriate times.
The digital sync generator takes horizontal sync
and vertical sync timing signals and generates the
appropriate composite sync timing (including vertical equalization and serration pulses), blanking
information, and burst flag. The sync edge rates
conform to RS-170A or CCIR specifications.
The luma only path is concluded via output interpolation by a factor of two in order to operate the output DACs at two times the pixel rate.
DS223PP2
CS4952/53
Digital to Analog Converters
Host Interface
The CS4952/3 provides four complete simultaneous 27 MHz DACs for analog video output: one
9-bit for S-video chrominance, one 9-bit for S-Video luminance, and two 9-bit composite outputs.
Both S-Video DACs are designed for 37.5 Ω overall loads. The two composite 9-bit DACs are not
identical. One DAC is designed to drive 37.5 Ω derived from a double terminated 75 Ω circuit. The
second 9-bit DAC is targeted for an on-board local
video connection where single point 75 Ω termination is sufficient i.e. Ch3/4 RF modulators, video
amps, muxes.
The CS4952/3 provides a parallel 8-bit data interface for overall configuration and control. The host
interface uses active low read and write strobes
along with an active low address enable signal to
provide microprocessor compatible read and write
cycles. Indirect host addressing to the CS4952/3 internal registers is accomplished via an internal address register which is uniquely accessible via bus
write cycles with the host address enable signal asserted.
The DACs can be put into tri-state mode via host
addressable control register bits. Each of the four
DACs has its own separate DAC enable associated
with it. In the disable mode, the 9-bit DACs source
or sink zero current.
For lower power standby scenarios the CS4952/3
also provides power shut-off control for the DACs.
Each DAC has a separate DAC shut-off associated
with it.
Voltage Reference
The CS4952/3 is equipped with an on-board
1.235 V voltage reference generator used by the
Video DACs. For most requirements, the voltage
reference output pin can be connected to the voltage reference input pin along with a decoupling capacitor. Otherwise the voltage reference input may
be connected to an external voltage reference.
Current Reference
The DAC output current per bit is derived in the
current reference block. The current step is specified by the size of resistor place between the ISET
current reference pin and electrical ground. This
has been optimized for 10kΩ (see “ISET” on
page 25 for more informmation on selecting the
proper ISET value).
DS223PP2
The CS4952/3 also provides an I2C compatible serial interface for device configuration and control.
This port can operate in standard or fast (400 KHz)
modes. When in I2C mode, the parallel data interface PDAT [7:0] pins may be used as a general purpose I/O port controlled by the I2C interface.
Closed Caption Services
The CS4952/3 supports the generation of NTSC
Closed Caption services. Line 21 and Line 284 captioning can be generated and enabled independently via a set of control registers. When enabled,
clock run-in, start bit, and data bytes are automatically inserted at the appropriate video lines. A convenient interrupt interface simplifies the software
interface between the host processor and the
CS4952/3.
Control Registers
The control and configuration of the CS4952/3 is
primarily accomplished through the control register block. All of the control registers are uniquely
addressable via the internal address register. The
control register bits are initialized during a chip reset.
See the detailed operation section of this data sheet
for all of the individual register bit allocations, bit
operational descriptions and initialization states.
13
CS4952/53
OPERATIONAL DESCRIPTION
Video Timing
Reset Hierarchy
Slave Mode Input Interface
The CS4952/3 is equipped with an active low asynchronous reset input pin RESET. RESET is used to
initialize the internal registers and the internal state
machines for subsequent default operation. See the
electrical and timing specification section of this
data sheet for specific CS4952/3 chip reset and
power-on signaling timing requirements and restrictions. All chip outputs are valid after a time period following RESET pin low.
In Slave Mode, the CS4952/3 takes VSYNC and
HSYNC as inputs. Slave Mode is the default following a reset and is changed to Master Mode via a
contol register bit (CONTROL_0 [4]). The
CS4952/3 is limited to CCIR601 horizontal and
vertical input timing. All clocking in the CS4952/3
is generated from the CLK pin. In Slave Mode the
Sync Generator uses externally provided horizontal
and vertical sync signals to synchronize the internal
timing of the CS4952/3.
When the RESET pin is held low, the host interface
in the CS4952/3 is disabled and will not respond to
host initiated bus cycles.
Video data that is sent to the CS4952/3 must be
synchronized to the horizontal and vertical sync
signals. Figure 6 illustrates horizontal timing for
CCIR601 input in Slave Mode. Note that the
CS4952/3 expects to receive the first active pixel
data on clock cycle 245 (NTSC) when bit
SYNC_DLY=0 in the CONTROL_2 Register
(Ox02). When SYNC_DLY=1, it expects the first
active pixel data on clock cycle 246 (NTSC).
A reset initializes the CS4952/3 internal registers to
their default values as described by Table 5. In the
default state, the CS4952/53 video DACs are disabled and the device is configured to internally provide blue field video data to the DACs (any input
data present on the V [7:0] pins is ignored). Otherwise the CS4952/53 registers are configured for
NTSC-M CCIR601 output operation. At a minimum, the DAC register (0x04) must be written (to
enable the DACs) and the IN_MODE bit of the
CONTROL_0 register (0x01) must be set (to enable CCIR601 data input on V [7:0]) for the
CS4952/53 to become operational after RESET.
NTSC 27MHz Clock Count
PAL 27MHz Clock Count
1682 1683 1684 1685 1686
1702 1703 1704 1705 1706
•••
•••
1716
1728
Master Mode Input Interface
The CS4952/3 defaults to Slave Mode following
RESET high but may be switched into Master
Mode via the MSTR bit in the CONTROL_0 Register (0x00). In Master Mode, the CS4952/3 uses
the VSYNC, HSYNC and FIELD device pins as
1
1
2
2
3
3
•••
•••
128
128
129
129
•••
•••
244
264
245
265
246
266
247
267
248
268
CLK
HSYNC* (input)
V[7:0]
(SYNC_DLY=0)
Y
•••
V[7:0]
(SYNC_DLY=1)
Cb
Cr
Y
Cb
horizontal blanking
active pixel
#720
Y
Cr
active pixel
#719
Y
active pixel
#720
Y
active pixel
#1
Cb
horizontal blanking
Cr
Y
active pixel
#2
Y
active pixel
#1
Cr
active pixel
#2
Figure 6. CCIR601 Input Slave Mode Horizontal Timing
14
DS223PP2
CS4952/53
outputs to schedule the proper external delivery of
digital video into the V [7:0] pins. Figure 7 illustrates horizontal timing for CCIR601 input in Master Mode. Note that the CS4952/3 expects to
receive the first active pixel data on clock cycle 245
(NTSC) when bit SYNC_DLY=0 in the
CONTROL_2
Register
(0x02).
When
SYNC_DLY=1, it expects the first active pixel data
on clock cycle 246 (NTSC).
specifies active line numbers for both NTSC and
PAL. Refer to Figure 8 for HSYNC, VSYNC and
FIELD signal timing.
MODE
NTSC
PAL
NTSC Progressive-Scan
PAL Progressive-Scan
Vertical Timing
The CS4952/3 can be selected through the
CONTROL_0 register (0x00) to operate in four
different timing modes: PAL which is 625 vertical
lines 25 frames per second interlaced, NTSC which
is 525 vertical lines 30 frames per second interlaced
and both PAL and NTSC again but in Progressive
Scan where the display is non-interlaced.
Table 1. Vertical Timing
Horizontal Timing
HSYNC is used to synchronize the horizontal input
to output timing in order to provide proper horizontal alignment. HSYNC defaults to an input pin following RESET but switches to output in Master
Mode (CONTROL_0 [4] = 1). Horizontal timing is
referenced to HSYNC transitioning low. For active
video lines, digital video input is to be applied to
the V [7:0] inputs 244 (NTSC) or 264 (PAL), CLK
periods following HSYNC going low to determine
the horizontal alignment of the active video.
The CS4952/3 conforms to standard digital decompression dimensions and does not process digital
input data for the active analog video half lines as
they are typically in the over/underscan region of
televisions. For NTSC, 240 active lines total per
field are processed and for PAL 288 active lines total per field. Frame vertical dimensions are 480
lines for NTSC and 576 lines for PAL. Table 1
NTSC 27MHz Clock Count
PAL 27MHz Clock Count
1682 1683 1684 1685 1686
1702 1703 1704 1705 1706
•••
•••
1716
1728
ACTIVE
LINES
22-261
285-524
23-310
336-623
22-261
23-310
FIELD
1, 3
2, 4
1, 3, 5, 7
2, 4, 6, 8
NA
NA
1
1
2
2
3
3
•••
•••
128
128
129
129
•••
•••
244
264
245
265
246
266
247
267
248
268
CLK
HSYNC* (output)
CB* (output)
V[7:0]
(SYNC_DLY=0)
Y
•••
V[7:0]
(SYNC_DLY=1)
Cb
Cr
Y
Cb
horizontal blanking
active pixel
#720
Y
active pixel
#719
Cr
Y
active pixel
#720
Y
active pixel
#1
Cb
horizontal blanking
Cr
Y
active pixel
#2
Y
active pixel
#1
Cr
active pixel
#2
Figure 7. CCIR601 Input Master Mode Horizontal Timing
DS223PP2
15
CS4952/53
NTSC Vertical Timing (odd field)
Line
3
4
5
6
7
8
9
10
267
268
269
270
271
3
4
5
6
7
314
315
316
317
318
HSYNC*
VSYNC*
FIELD
NTSC Vertical Timing (even field)
Line
264
265
266
HSYNC*
VSYNC*
FIELD
PAL Vertical Timing (odd field)
Line
265
1
2
HSYNC*
VSYNC*
FIELD
PAL Vertical Timing (even field)
Line
311
312
313
HSYNC*
VSYNC*
FIELD
Figure 8. Vertical Timing
16
DS223PP2
CS4952/53
NTSC Interlaced
The CS4952/3 supports NTSC-M and PAL-M
modes where there are 525 total lines per frame and
two fixed 262.5 line fields per frame and 30 total
frames occuring per second. Please reference Figure 9 for NTSC interlaced vertical timing. Each
field consists of 1 line for closed caption, 240 active lines of video plus 21.5 lines of blanking.
VSYNC field one transistions low at the beginning
of line 4 and will remain low for 3 lines or (858 x 3)
2574 pixel cycles. The CS4952/3 exclusively reserves line 21 of field one for closed caption insertion. Digital video input is expected to be delivered
to the CS4952/3 V [7:0] pins for 240 lines beginning on active video lines 22 and continuing
Analog
Field 1
523
524
525
1
through line 261. VSYNC field two transistions
low in the middle of line 266 and stays low for 3
lines times and transitions high in the middle of line
269. The CS4952/3 exclusively reserves line 284 of
field two for closed caption insertion. Video input
on the V [7:0] pins is expected between lines 285
through line 525.
PAL Interlaced
The CS4952/3 supports PAL modes B, D, G, H, I,
N, and Combination N where there are 625 total
lines per frame and two fixed 312.5 line fields per
frame and 25 total frames occuring per second.
Please reference Figure 10 for PAL interlaced vertical timing. Each field consists of 288 active lines
of video plus 24.5 lines of blanking.
VSYNC* Drops
2
3
4
5
6
7
8
9
10
22
Analog
Field 2
261
262
263
264
265
266
Analog
Field 3
523
524
525
1
267
268
269
270
271
272
284
285
VSYNC* Drops
2
3
4
5
6
7
8
9
10
22
Analog
Field 4
261
262
263
264
265
Burst begins with positive half-cycle
266
267
268
269
270
271
272
284
285
Burst begins with negative half-cycle
Figure 9. NTSC Video Interlaced Timming
DS223PP2
17
CS4952/53
VSYNC* Drops
Analog
Field 1
620
621
622
623
624
625
1
2
3
4
5
6
7
23
24
Analog
Field 2
308
309
310
311
312
313
314
315
316
317
318
319
320
336
337
Analog
Field 3
621
620
622
623
624
625
1
2
3
4
5
6
7
23
24
Analog
Field 4
308
309
310
311
312
313
314
315
316
317
318
319
320
336
337
Analog
Field 5
621
620
622
623
624
625
1
2
3
4
5
6
7
23
24
Analog
Field 6
308
309
310
311
312
313
314
315
316
317
318
319
320
336
337
Analog
Field 7
621
620
622
623
624
625
1
2
3
4
5
6
7
23
24
Analog
Field 8
308
309
310
311
312
313
314
Burst Phase = 135 degrees relative to U
315
316
317
318
319
320
336
337
Burst Phase = 225 degrees relative to U
Figure 10. PAL Video Interlaced Timing
18
DS223PP2
CS4952/53
VSYNC will transition low to begin field one and
will remain low for 2.5 lines or (864 x 2.5) 2160
pixel cycles. Digital video input is expected to be
delivered to the CS4952/3 V [7:0] pins for 287
lines beginning on active video line 24 and continuing through line 310.
Field two begins with VSYNC transitioning low
after 312.5 lines from the beginning of field one.
VSYNC stays low for 2.5 lines times and transitions high with the beginning of line 315. Video input on the V [7:0] pins is expected between line 336
through line 622.
Progressive Scan
The CS4952/3 supports a progessive scan mode
where the video output is non-interlaced. This is
accomplished by displaying only the first video
field for NTSC or PAL. To preserve exact MPEG-2
frame rates of 30 and 25 per second, the CS4952/3
displays the same first field repetitively but alternately varies the field times. Other digital video encoders commonly support progressive scan by
repetitively displaying a 262 line field (524/525
lines for NTSC). In the long run this method is
flawed in that over time, the output display rate will
overrun a system clock locked MPEG-2 decompressor and display a field twice every 8.75 seconds.
PAL Progressive Scan
VSYNC will transistion low to begin field one and
will remain low for for 2.5 lines or (864 x 2.5) 2160
pixel times. Please reference Figure 11 for PAL
non-interlaced timing. Digital video input is expected to be delivered to the CS4952/3 V [7:0] pins
for 288 lines beginning on active video line 23 and
continuing through line 309.
Field two begins with VSYNC transitioning low
after 312 lines from the beginning of field one.
DS223PP2
VSYNC stays low for 2.5 line times and transitions
high during the middle of line 315. Video input on
the V [7:0] pins is expected between line 335
through line 622. Field two is 313 lines long while
field one is 312.
NTSC Progressive Scan
VSYNC will transition low at line 4 to begin field
one and will remain low for 3 lines or (858 x 3)
2574 pixel times. Please reference Figure 12 for
NTSC interlaced timing. Digital video input is expected to be delivered to the CS4952/3 V [7:0] pins
for 240 lines beginning on active video line 22 and
continuing through line 261.
Field two begins with VSYNC transitioning low at
line 266. VSYNC stays low for 2.5 line times and
transitions high during the middle of line 268. Video input on the V [7:0] pins is expected between
line 284 through line 524. Field two is 263 lines
long while field one is 262.
CCIR-656
The CS4952/3 supports an additional Slave Mode
feature that is selectable through the CCIR601 bit
of the CONTROL_0 register. The CCIR-656 slave
feature is unique because the horizontal and vertical timing and digital video are combined into a
single 8-bit 27 MHz input. With CCIR-656 there
are no horizontal and vertical input or output
strobes, only 8-bit 27 MHz active CbYCrY data
with start and end of video codes being implemented with reserved 00 and FF code sequences within
the video feed. As with all modes, V [7:0] are sampled with the rising edge of CLK. The CS4952/3
expects the digital CCIR-656 stream to be error
free. The FIELD output toggles as with non
CCIR-656 input. CCIR-656 input timing is illustrated in Figure 13.
19
CS4952/53
VSYNC* Drops
Analog
Field 1
309
310
311
312
313
1
2
3
4
5
6
7
23
24
2
3
4
5
6
7
23
24
2
3
4
5
6
7
23
24
2
3
4
5
6
7
23
24
Analog
Field 2
308
309
310
311
312
1
Analog
Field 3
309
310
311
312
313
1
Analog
Field 4
308
309
310
311
312
1
Burst Phase = 135 degrees relative to U
Burst Phase = 225 degrees relative to U
Figure 11. PAL Video Non-Interlaced Progressive Scan Timing
20
DS223PP2
CS4952/53
Start of
VSYNC
262
263
1
2
3
4
Field 1
5
6
7
8
9
10
22
6
7
8
9
10
22
6
7
8
9
10
22
6
7
8
9
10
22
Field 2
261
262
1
2
3
4
5
Start of
VSYNC
262
263
1
2
3
4
Field 3
5
Field 4
261
262
1
2
3
4
5
Burst begins with positive half-cycle
Burst phase = reference phase =
180 0 relative
Burst begins with negative half-cycle
to B-Y
Burst phase = reference phase = 180 0 relative to B-Y
Figure 12. NTSC Video Non-Interlaced Progressive Scan Timing
Composite
Video
CCIR656 V[7:0]
DATA
Y Cr Y FF 00 00 XY 80 10 80 10
80 10 80 10 80 10
80 10 80 10 FF 00 00 XY Cb Y Cr Cb Y Cr
EAV Code
Ancilliary Data
SAV Code
4 Clocks
268 Clocks (NTSC)
280 Clocks (PAL)
4 Clocks
Active Video
1440 Clocks
Active Video
Horizontal Blanking
Figure 13. CCIR656 Input Mode Timing
DS223PP2
21
CS4952/53
Address
0x00
0x01
0x10
0x11
0x12
0x13
0x14
Register
CONTROL_0
CONTROL_1
SC_AMP
SC_SYNTH0
SC_SYNTH1
SC_SYNTH2
SC_SYNTH3
NTSC-MC
CIR601
01h
04h
1Ch
3Eh
F8h
E0h
43h
NTSC-MCCI
R60
NTSC-MR
(Japan)
S170A
01h
21h
00h
04h
1Ch
1Ch
3Eh
3Eh
F8h
F8h
E0h
E0h
43h
43h
PAL-B,D,
G,H,I
41h
04h
15h
96h
15h
13h
54h
PAL-M
61h
04h
15h
4Eh
4Ah
E1h
43h
PAL-N
A1h
04h
15h
96h
15h
13h
54h
PAL-NCom
(Argentina)
81h
04h
15h
8Ch
28h
EDh
43h
Table 2. Multi-standard Format Register Configurations
(Slave Mode, interlaced timing, non-656 data)
Digital Video Input Modes
The CS4952/3 provides 2 different digital video input modes that are selectable through the
IN_MODE bit of the CONTROL_0 register.
In mode 0 and upon RESET, the CS4952/3 defaults
to output a solid color (1 of a possible of 256 colors). The background color is selected by writing
the BKG_COLOR register (0x08). The colorspace
of the register is RGB 3:3:2 and is unaffected by
gamma correction. The default color following RESET is blue.
In mode 1 the CS4952/3 supports a single 8-bit
27 MHz CbYCrY source as input on the V [7:0]
pins. Input video timing can be CCIR601 master or
slave and progressive scan.
Multi-standard Output Format Modes
The CS4952/53 supports a wide range of output
formats compatible with worldwide broadcast standards. These formats include NTSC-M,
PAL-B/D/G/H/I, PAL-M, PAL-N and PAL Combination N (PAL-Nc) which is the broadcast standard
used in Argentina. After RESET, the CS4952/53 defaults to NTSC-M operation with CCIR601 analog
timing. NTSC-M can also be supported in the Japanese format by turning off the 7.5 IRE pedestal
through the PED bit in the CONTROL_1 register
(0x01).
22
Output formats are configured by writing control
registers as shown in Table 2.
Subcarrier Generation
The CS4952/3 automatically synthesizes NTSC
and PAL color subcarrier clocks using the CLK frequency
and
four
control
registers
(SC_SYNTH0/1/2/3). The NTSC subcarrier synthesizer is reset every four fields and every eight
fields for PAL.
The SC_SYNTH0/1/2/3 registers used together
provide a 32-bit value which defaults to NTSC values of 43E0F83Eh following reset.
Table 3 indicates the 32-bit value required for the
different broadcast formats.
Subcarrier Compensation
Since the subcarrier is synthesized from CLK the
subcarrier frequency error will track the clock frequency error. If the input clock has a tolerance of
200 ppm then the resulting subcarrier will also
have a tolerance of 200 ppm. Per the NTSC specification the final subcarrier tolerance is ±10 Hz
which is more like 3 ppm. Care must be taken in selecting a suitable clock source.
In MPEG-2 system environments the clock is actually recovered from the data stream. In these cases
the recovered clock can be 27 MHz ±50 ppm or
DS223PP2
CS4952/53
System
NTSC-M
PAL-B, D, G, H, I, N
PAL-N (Argentina)
PAL-M
Fsubcarrier
3.5795455 MHz
4.43361875 MHz
3.582056 MHz
3.579611 MHz
Value (dec)
1138817086
1410536854
1139615885
1138838095
Value (hex)
43E0F83E
54131596
43ED288D
43CDDFC7
Table 3. Multi-standard Format FSC Register Configurations
±1350 Hz. It varies per television but in many cases
given an MPEG-2 system clock of 27 MHz
±1350 Hz the resultant color subcarrier produced
will be outside of the televisions ability to compensate and the chrominance information will not be
displayed (black and white picture only).
The CS4952/3 is designed to provide automatic
compensation for an excessively inaccurate
MPEG-2 system clock. Sub-carrier compensation
is enabled through the XTAL bit of the
CONTROL_2 register. When enabled the
CS4952/3 will utilize a common quartz color burst
crystal (3.579545 MHz ±50 ppm for NTSC) attached to the ADDR and XTAL pins to automatically compare and compensate the color subcarrier
synthesis process. Use of the ADDR and XTAL
pins requires that the host interface is configured
for I2C operation.
Closed Caption Insertion
The CS4952/3 is capable of NTSC Closed Caption
insertion on lines 21 and 284 independently.
Closed captioning is enabled for either or both lines
21 & 284 via the CC_EN [1:0] register bits and data
to be inserted is also written into the four Closed
Caption Data registers. The CS4952/3 when enabled automatically generates the seven cycles of
clock run-in (32 x line rate), start bit insertion
(001)and finally insertion of the two data bytes per
line. Data low at the video outputs corresponds to 0
IRE and data high corresponds to 50 IRE.
& CC_284_2 for line 284). Interrupts are also provided to simplify the handshake between the driver
software and the chip. Typically the host would
write all 4 bytes to be inserted into the registers and
then enable closed caption insertion and interrupts.
As the closed caption interrupts occur the host software would respond by writing the next two bytes
to be inserted to the correct control registers and
then clear the interrupt and wait for the next field.
Color Bar Generator
The CS4952/3 is equipped with a color bar generator that is enabled through the CBAR bit of the
CONTROL_1 register. The color bar generator
works in Master or Slave Mode and has no effect
on the video input/output timing. If the CS4952/3 is
configured for Slave Mode color bars, proper video
timing must be present on the HSYNC and
VSYNC pins for the color bars to be displayed.
Given proper Slave Mode input timing or Master
Mode, the color bar generator will override the video input pixel data.
The output of the color bar generator is instantiated
after the chroma interpolation filter and before the
luma delay line. The generated color bar numbers
are for 100% amplitude, 100% saturation NTSC
EIA color bars or 100% amplitude, 100% saturation PAL EBU color bars. For PAL color bars, the
CS4952/3 generates NTSC color bar values, which
are very close to standard PAL values. The exact
luma and chroma values are listed in Table 4.
There are two independent 8-bit registers per line
(CC_21_1 & CC_21_2 for line 21 and CC_284_1
DS223PP2
23
CS4952/53
COLOR
White
Yellow
Cyan
Green
Magenta
Red
Blue
Black
Cb
0
-84
+28
-56
+56
-28
+84
0
Cr
0
+14
-84
-70
+70
+84
-14
0
Y
+180
+162
+131
+112
+84
+69
+35
+16
Table 4. Internal Color Bar Values
(8-bit values, Cb/Cr are in 2’s complement format)
Interrupts
In order to better support precise video mode
switches and to establish a software/hardware
handshake with the closed caption insertion block
the CS4952/3 is equipped with an interrupt pin
named INT. The INT pin is active high. There are
three interrupt sources: VSYNC, Line 21 and Line
284. Each interrupt can be individually disabled
with the INT_EN register. Each interrupt is also
cleared via writing a one to the corresponding
INT_CLR register bits. The three individual interrupts are ORed together to generate an interrupt
signal which is presented on the INT output pin. If
an interrupt has occurred, it cannot be eliminated
with a disable, it must be cleared.
General Purpose I/O Port
The CS4952/53 has a GPIO port and register which
is available when the device is configured for I2C
host interface operation. In I2C host interface
mode, the PDAT [7:0] pins are unused by the host
interface and they may operate independently as input or output pins for the GPIO_DATA_REG register (0x0A). The CS4952/53 also contains the
GPIO_CTRL_REG Register (0x09) which is used
to configure the GPIO pins for input or output operation.
GPIO_CTRL_REG [7:0] bits are cleared. In GPIO
input mode, the CS4952/53 will latch the data on
the PDAT [7:0] pins into the corresponding bit locations of GPIO_DATA_REG when it detects register address 0x0A through the I2C interface. A
detection of address 0x0A can happen in two ways.
The first and most common way this will happen is
when address 0x0A is written to the CS4952/53 via
its I2C interface. The second method for detecting
address 0x0A is implemented by accessing register
address 0x09 through I2C. In I2C host interface operation, the CS4952/53 register address pointer will
auto-increment to address 0x0A after an address
0x09 access.
The GPIO port PDAT [7:0] pins are configured for
output operation when the corresponding
GPIO_CTRL_REG [7:0] bits are set. In GPIO output mode, the CS4952/53 will output the data in
GPIO_DATA_REG [7:0] bit locations onto the
corresponding PDAT [7:0] pins when it detects a
register address 0x0A through the I2C interface.
ANALOG
Analog Timing
All CS4952/3 analog timing and sequencing is derived from the 27 MHz clock input. The analog outputs are controlled internally by the video timing
generator in conjunction with master and slave timing. The video output signals perform accordingly
for NTSC, PAL specifications and both modes again
but with progressive scan non-interlaced video output.
Being that the CS4952/3 is almost entirely a digital
circuit, great care has been taken to guarantee analog timing and slew rate performance as specified
in the NTSC and PAL analog specifications. Reference the Analog Parameters section of this data
sheet for exact performance parameters.
The GPIO port PDAT [7:0] pins are configured for
input operation when the corresponding
24
DS223PP2
CS4952/53
VREF
DACs
The CS4952/3 can operate with or without the aid
of an external voltage reference. The CS4952/3 is
designed with an internal voltage reference generator that provides a VREFOUT signal. The internal
voltage reference is utilized by electrically connecting the VREFOUT and VREFIN pins. VREFIN can also be connected to an external precision
1.235 volt reference. In either case, VREFIN is to
be decoupled to ground with a 0.1 µF capacitor.
Decoupling should be applied as close to the device
pin as possible.
The CS4952/3 is equipped with 4 independent video grade current output digital to analog converters.
They are 9-bit DACs operating at a 27 MHz two
times oversampling rate. All four DACs are disabled and put in a low power mode upon RESET.
All four DACs can be individually powered down
and disabled. The output current per bit of all four
DACs is determined by the size of resistor connected between the ISET pin and electrical ground.
ISET
All four of the CS4952/3 digital to analog converter
DACs are output current normalized with a common ISET device pin. The DAC output current per
bit is determined by the size of the resistor connected between ISET and electrical ground. Typically a
10 kΩ±1% metal film resistor should be used. The
ISET resistance can be changed by the user to accommodate varying video output attenuation via
post filters and also to suit individual preferred performance.
In conjunction with the ISET value, the user may
also independently vary the chroma, luma and colorburst amplitude levels via host addressable control register bits that are used to control internal
digital amplifiers. The DAC output levels are defined by the following operations:
VREFIN/RISET = IREF
1.235 V/10 kΩ = 123.5 µA
CVBS37/Y/C Outputs:
VOUT (max) = IREF × (8/15) × 511 × 37.5 Ω =
1.262 V
CVBS75 Output:
VOUT (max) = IREF × (4/15) × 511 × 75 Ω =
1.262 V
DS223PP2
Luminance DAC
The Y pin is driven from a 9-bit 27 MHz current
output DAC that internally receives the Y or luminance portion of the video signal (black and white
intensity and syncronization information only). Y
is designed to drive proper video levels into a
37.5 Ω load. Reference the detailed electrical section of this data sheet for the exact Y digital to analog AC and DC performance data. A Y_EN
enable control bit in the DAC register (0x08) is
provided to enable or disable the luminance DAC.
For a complete disable and lower power operation
the Luminance DAC can be totally shut down via
the Y_PD control bit in the DAC register (0x08). In
this mode turn-on through the control register will
not be instantaneous.
Chrominance DAC
The C pin is driven from a 9-bit 27 MHz current
output DAC that internally receives the C or
chrominance portion of the video signal (color
only). C is designed to drive proper video levels
into a 37.5 Ω load. Reference the detailed electrical
section of this data sheet for the exact C digital to
analog AC and DC performance data. A C_EN enable control register bit in the DAC register (0x08)
is provided to enable or disable the Chrominance
DAC. For a complete disable and lower power operation the Chrominance DAC can be totally shut
down via the C_PD control register bit in the DAC
25
CS4952/53
register (0x08). In this mode turn-on through the
control register will not be instantaneous.
CVBS75 DAC
The CVBS75 pin is driven from a 9-bit 27 MHz
current output DAC that internally receives a combined luma and chroma signal to provide composite video output. CVBS75 is designed to drive
proper composite video levels into a 75 Ω load.
Reference the detailed electrical section of this data
sheet for the exact CVBS75 digital to analog AC
and DC performance data. A C_75_EN enable control register bit in the DAC register (0x08) is provided to enable or disable the ouput pin. When
disabled, no current flows from the output. For a
complete disable and lower power operation the
CVBS75 DAC can be totally shut down via the
C_75_PD control register bit in the DAC register
(0x08). In this mode turn-on through the control
register will not be instantaneous.
26
CVBS37 DAC
The CVBS37 pin is driven from a 9-bit 27 MHz
current output DAC that internally receives a combined luma and chroma signal to provide composite video output. CVBS37 is designed to drive
proper composite video levels into a 37.5 Ω load.
Reference the detailed electrical section of this data
sheet for the exact CVBS37 digital to analog AC
and DC performance data. The C_37_EN DAC enable control register bit is in the DAC register
(0x08) provided to enable or disable the ouput pin.
When disabled, no current flow from the output.
For a complete disable and lower power operation
the CVBS37 DAC can be totally shut down via the
C_37_PD control register bit in the DAC register
(0x08). In this mode turn-on through the control
register will not be instantaneous.
DS223PP2
CS4952/53
The I2C bus address for the CS4952/3 is programmable via register I2C_ADR (0x0F).
PROGRAMMING
Host Control Interface
The CS4952/3 host control interface can be configured for I2C or 8-bit parallel operation. The
CS4952/3 will default to I2C operation when the
RD and WR pins are both tied low at power up. The
RD and WR pins are active for 8-bit parallel operation only.
I2C Interface
The CS4952/3 provides an I2C interface for accessing the internal control and status registers. External
pins are a bidirectional data pin (SDA) and a serial
input clock (SCL). The protocol follows the I2C
specifications. A complete data transfer is shown in
Figure 14. Note that this I2C interface will work in
Slave Mode only - it is not a bus master.
SDA and SCL are connected via an external
pull-up resistor to a positive supply voltage. When
the bus is free, both lines are high. The output stages of devices connected to the bus must have an
open-drain or open-collector in order to perform
the wired-AND function. Data on the I2C bus can
be transferred at a rate of up to 400 kbits/sec in fast
mode. The number of interfaces to the bus is solely
dependent on the limiting bus capacitance of
400 pF. When 8-bit parallel interface operation is
being used, SDA and SCL can be tied directly to
ground.
8-bit Parallel Interface
The CS4952/3 is equipped with a full 8-bit parallel
microprocessor write and read control port. Along
with the PDAT [7:0] pins the control port interface
is comprised of host read RD and host write WR
active low strobes and host address enable ADDR
which, when low, enables unique address register
accesses. The control port is used to access internal
registers which configure the CS4952/3 for various
modes of operation. The internal registers are
uniquely addressed via an address register. The address register is accessed during a host write cycle
with the WR and ADDR pins set low. Host write
cycles with ADDR set high will write the 8-bits on
the PDAT [7:0] pins into the register currently selected by the address register. Likewise read cycles
occur with RD set low and ADDR set high will return the register contents selected by the address
register. Reference the detailed electrical timing
parameter section of this data sheet for exact host
parallel interface timing characteristics and specifications. When I2C interface operation is being
used, RD and WR must be tied to ground.
PDAT [7:0] are available to be used for GPIO operation in I2C host interface mode.
I 2 C Protocol
SDA
SCL
A
Start
1-7
8
Address R/W
9
ACK
1-7
8
Data
9
ACK
1-7
8
Data
9
ACK
P
Stop
Note: I 2 C transfers data always with MSB first, LSB last
Figure 14. I2C Data Transfer
DS223PP2
27
CS4952/53
Register Description
A set of internal registers are available for controlling the operation of the CS4952/3. The registers
extend from internal address 0x00 through 0x3D.
Table 5 shows a complete list of these registers and
Address
0x00
0x01
0x02
0x03
0x04
0x05 - 0x06
0x07
0x08
0x09
0x0A
0x0B - 0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D - 0x3A
0x3B
0x3C
0x3D
Register Name
CONTROL_0
CONTROL_1
CONTROL_2
RESERVED
DAC
RESERVED
STATUS
BKG_COLOR
GPIO_CTRL_REG
GPIO_DATA_REG
RESERVED
C_AMP
Y_AMP
I2C_ADR
SC_AMP
SC_SYNTH0
SC_SYNTH1
SC_SYNTH2
SC_SYNTH3
HUE_LSB
HUE_MSB
RESERVED
CC_EN
CC_21_1
CC_21_2
CC_284_1
CC_284_2
RESERVED
INT_EN
INT_CLR
ID_REG
their internal addresses. Note that this table and the
subsequent register description section describe the
full register map for CS4952 only. A complete
CS4953 register set description is only available to
Macrovision ACP-PPV Licensed Buyers.
r/w
r/w
r/w
Type
Default Value
01h
04h
00h
r/w
F0h
read only
r/w
r/w
r/w
00h
03h
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
80h
80h
n/a
1Ch
3Eh
F8h
E0h
43h
00h
00h
r/w
r/w
r/w
r/w
r/w
00h
00h
00h
00h
00h
r/w
r/w
read only
00h
00h
n/a
00h
Table 5. Control Register Map
28
DS223PP2
CS4952/53
Control Register 0
Address
0x00
Bit Number
Bit Name
Default
7
0
Bit
7:5
Mnemonic
TV_FMT
4
3
2
1
0
MSTR
CCIR656
PROG
IN_MODE
CBCR_UV
CONTROL_0
6
TV_FMT
0
5
0
Read/Write
4
MSTR
0
3
CCIR656
0
Default Value = 01h
2
PROG
0
1
0
IN_MODE CBCR_UV
0
1
Function
selects the TV display format
000:
NTSC-M CCIR601 timing (default)
001:
NTSC-M RS170A timing
010:
PAL-B, D, G, H, I
011:
PAL-M
100:
PAL-N (Argentina)
101:
PAL-N (non Argentina)
110-111:
reserved
1: Master Mode, 0: Slave Mode
video input is in CCIR656 format (0: off, 1: on)
Progressive scanning enable (enable with 1)
Input select (0: solid background, 1: use V [7:0] data)
enable YCbCr to YUV conversion (1: enable, 0: disable)
Control Register 1
Address
0x01
Bit Number
Bit Name
Default
7
CBLANK
0
Bit
7
6
5
4
3
2
1
0
DS223PP2
Mnemonic
CBLANK
Y_DELAY
C_BW
C_LPF_EN
FLD
PED
CBAR
CBCRSEL
CONTROL_1
6
Y_DELAY
0
5
C_BW
0
Read/Write
4
C_LPF_EN
0
3
FLD
0
Default Value = 04h
2
PED
1
1
CBAR
0
0
CBCRSEL
0
Function
Composite Blank / HSYNC output select (1: CB, 0: HSYNC)
luma to chroma delay (0: no delay, 1: luma is delayed by one 13.5 MHz cycle)
chroma lpf bandwidth (0: 650 KHz, 1: 1.3 MHz)
chroma lpf on/off (0: off, 1: on)
Polarity of Field (0: odd field - 0, 1: odd field - 1)
Pedestal offset (0: 0 IRE, 1: 7.5 IRE)
internal color bar generator (0: off, 1: on)
CbCr select (0: chroma undelayed, 1: chroma delayed by one clock)
29
CS4952/53
Control Register 2
Address
0x02
CONTROL_2
Bit Number
Bit Name
Default
7
6
0
0
Bit
7:4
Mnemonic
-
3
Y_BW
2
1
0
SYNC_DLY
XTAL
SC_EN
5
RESERVED
0
Read/Write
4
3
0
0
Default Value = 00h
2
SYNC_DLY
0
1
XTAL
0
0
SC_EN
0
Function
reserved
Selects between 4.2 Mhz and 6 Mhz on-chip luminance low pass filters; default
value is zero which selects the 4.2 Mhz low pass filter option
Delays expected timing of first active pixel input data relative to falling edge of
HSYNC from 245 27 MHz clock cycles to 246 for NTSC and from 265 to 266 for
PAL. Default State is SYNC_DLY=0 for no delay
Crystal oscillator for subcarrier adjustment enable (1: enable)
Chroma burst disable (1: disable)
DAC Power Down Register
Address
0x04
Bit Number
Bit Name
Default
7
C_75_PD
1
Bit
7
6
5
4
3
2
1
0
Mnemonic
C_75_PD
C_37_PD
Y_PD
C_PD
C_75_EN
C_37_EN
Y_EN
C_EN
30
DAC
6
C_37_PD
1
Read/Write
5
Y_PD
1
4
C_PD
1
3
C_75_EN
0
Default Value = F0h
2
C_37_EN
0
1
Y_EN
0
0
C_EN
0
Function
power down composite DAC with 75 Ω load (0: power up, 1: power down)
power down composite DAC with 37.5 Ω load (0: power up, 1: power down)
power down luma s-video DAC (0: power up, 1: power down)
power down chroma s-video DAC (0: power up, 1: power down)
enable composite video DAC output for 75 Ω (0: tri-state, 1: enable)
enable composite video DAC output for 37.5 Ω (0: tri-state, 1: enable)
enable s-video DAC for luma output (0: tri-state, 1: enable)
enable s-video DAC for chroma output (0: tri-state, 1: enable)
DS223PP2
CS4952/53
Status Register
Address
Bit Number
Bit Name
Default
Bit
7:6
5
4
3
2:0
0x07
STATUS
7
6
RESERVED
0
0
Mnemonic
CC_INT_21
CC_INT_284
VS_INT
FIELD
5
CC_INT_21
0
Read Only
4
CC_INT_284
0
Default Value = 00h
3
VS_INT
0
2
0
1
FIELD
0
0
0
Function
reserved
Interrupt flag for line 21 (closed caption) complete
Interrupt flag for line 284 (closed caption) complete
Interrupt flag for video field change
Field Status bits
000: field 8
001: field 1
010: field 2
011: field 3
100: field 4
101: field 5
110: field 6
111: field 7
Background Color Register
Address
0x08
Bit Number
Bit Name
Default
7
0
Bit
7:0
Mnemonic
BG_COLR
BKG_COLOR
6
5
Read/Write
4
Default Value = 03h
3
2
1
0
0
0
1
1
BG_COLR
0
0
0
Function
Background color (7:5 = R, 4:2 = G, 1:0 = B)
GPIO Control Register
Address
0x09
Bit Number
Bit Name
Default
0
Bit
7:0
Mnemonic
GPIO_IO
DS223PP2
7
GPIO_CTRL_REG
6
5
Read/Write
4
Default Value = 00h
3
2
1
0
0
0
0
0
GPIO_IO
0
0
0
Function
input(0)/output(1) control of GPIO registers (bit X: PDAT(X) I/O configuration)
31
CS4952/53
GPIO Data Register
Address
0x0A
GPIO_DATA_REG
Bit Number
Bit Name
Default
7
6
5
0
0
0
Bit
Mnemonic
7:0
GPIO_DATA
Read/Write
4
3
GPIO_DATA
0
0
Default Value = 00h
2
1
0
0
0
0
Function
GPIO data register; data is output on PDAT [7:0] bus if appropriate bit in
GPIO_CTRL_REG (0x09) is set to “1”; data on PDAT [7:0] is latched into
GPIO_DATA_REG [7:0] when register address 0x0A is accessed via I2C.
This register is only accessible in I2C mode.
Chroma Filter Register
Address
0x0D
Bit Number
Bit Name
Default
7
Bit
7:0
Mnemonic
C_COEF
C_AMP
6
Read/Write
5
4
Default Value = 80h
3
2
1
0
0
0
0
0
C_COEF
1
0
0
0
Function
Chroma amplitude coefficient
Luma Filter Register
Address
0x0E
Y_AMP
Read/Write
Bit Number
Bit Name
Default
7
6
5
4
1
0
0
0
Bit
7:0
Mnemonic
Y_COEF
Default Value = 80h
3
2
1
0
0
0
0
0
Y_COEF
Function
Luma amplitude coefficient
I2C Address Register
Address
0x0F
Bit Number
Bit Name
Default
7
RESERVED
-
Bit
7
Mnemonic
-
6:0
ADDR
32
I2C_ADR
Read/Write
6
5
4
-
-
-
3
ADDR
-
Default Value = N/A
2
1
0
-
-
-
Function
reserved
I2C device address (programmable)
DS223PP2
CS4952/53
Subcarrier Amplitude Register
Address
0x10
SC_AMP
Read/Write
Bit Number
Bit Name
Default
7
6
5
4
0
0
0
1
Bit
7:0
Mnemonic
AMP
Default Value = 1Ch
3
2
1
0
1
1
0
0
AMP
Function
Color burst amplitude
Subcarrier Synthesis Register
Address
0x11
0x12
0x13
0x14
Register
SC_SYNTH0
SC_SYNTH1
SC_SYNTH2
SC_SYNTH3
SC_SYNTH0
SC_SYNTH1
SC_SYNTH2
SC_SYNTH3
Bits
7:0
7:0
7:0
7:0
Mnemonic
-
Read/Write
Default Value = 3Eh
F8h
E0h
43h
Function
Subcarrier synthesis bits 7:0
Subcarrier synthesis bits 15:8
Subcarrier synthesis bits 23:16
Subcarrier synthesis bits 31:24
Hue LSB Adjust Register
Address
0x15
Bit Number
Bit Name
Default
7
0
Bit
7:0
Mnemonic
LSB
HUE_LSB
6
5
Read/Write
4
Default Value = 00h
3
2
1
0
0
0
0
0
LSB
0
0
0
Function
8 LSBs for hue phase shift
Hue MSB Adjust Register
Address
0x16
HUE_MSB
Bit Number
Bit Name
Default
7
6
0
0
Bit
7:2
1:0
Mnemonic
MSB
DS223PP2
5
4
RESERVED
0
0
Read/Write
Default Value = 00h
3
2
1
0
0
0
0
MSB
0
Function
reserved
2 MSBs for hue phase shift
33
CS4952/53
Closed Caption Enable Register
Address
0x18
CC_EN
Bit Number
Bit Name
Default
7
6
0
0
Bit
7:2
1
0
Mnemonic
EN_284
EN_21
Read/Write
5
4
RESERVED
0
0
Default Value = 00h
3
2
0
0
1
EN_284
0
0
EN_21
0
Function
reserved
enable closed caption for line 284
enable closed caption for line 21
Closed Caption Data Register
Address
Register
CC_21_1
CC_21_2
CC_284_1
CC_284_2
0x19
0x1A
0x1B
0x1C
Bit
7:0
7:0
7:0
7:0
CC_21_1
CC_21_2
CC_284_1
CC_284_2
Mnemonic
-
Read/Write
Default Value = 00h
00h
00h
00h
Function
first closed caption databyte of line 21
second closed caption databyte of line 21
first closed caption databyte of line 284
second closed caption databyte of line 284
Interrupt Enable Register
Address
0x3B
INT_EN
Bit Number
Bit Name
Default
7
6
0
0
Bit
7:3
2
1
0
Mnemonic
EN_21
EN_284
VS_EN
34
5
RESERVED
0
Read/Write
4
3
0
0
Default Value = 00h
2
EN_21
0
1
EN_284
0
0
VS_EN
0
Function
reserved
interrupt enable for closed caption line 21
interrupt enable for closed caption line 284
interrupt enable for new field
DS223PP2
CS4952/53
Interrupt Clear Register
Address
0x3C
INT_CLR
Bit Number
Bit Name
Default
7
6
0
0
Bit
7:3
2
1
0
Mnemonic
CLR_21
CLR_284
VS_CLR
5
RESERVED
0
Read/Write
4
3
0
0
Default Value = 00h
2
CLR_21
0
1
CLR_284
0
0
VS_CLR
0
Function
reserved
clear interrupt for closed caption line 21 (INT_21)
clear interrupt for closed caption line 284 (INT_284)
clear interrupt for new video field (INT_V)
Device ID Register
Address
0x3D
ID_REG
Bit Number
Bit Name
Default
7
6
0
0
Bit
7:4
Mnemonic
DEV_ID
3:0
-
DS223PP2
Read Only
5
4
3
0
0
-
DEV_ID
Default Value = N/A
2
1
RESERVED
-
0
-
Function
0000 device ID for CS4952
0001 device ID for CS4953
These bits are reserved and the value they return on a read is not defined
35
CS4952/53
BOARD DESIGN & LAYOUT
CONSIDERATIONS
The printed circuit layout should be optimized for
lowest noise on the CS4952/3 power and ground
lines. Digital and analog sections should be physically separated and the CS4952/3 placed as close to
the output connectors as possible. All analog supply traces should be as short as possible to minimize inductive ringing.
A well designed power distribution network is essential in eliminating digital switching noise. The
ground planes must provide a low-impedance return path for the digital circuits. A PC board with a
minimum of four layers is recommended. The
ground layer should be used as a shield to isolate
noise from the analog traces. The top layer (1)
should be reserved for analog traces but digital
traces may share this layer if the digital signals
have low edge rates and switch little current or if
they are separated from the analog traces by a significant distance (dependent on their frequency
content and current). The second layer should then
be the ground plane followed by the analog power
plane on layer three and the digital signal layer on
layer four
same supply. If necessary, further isolate the digital
and analog power supplies by using ferrite beads on
each supply branch followed by a low ESR capacitor.
Place all decoupling caps as close as possible to the
device as possible. Surface mount capacitors generally have lower inductance than radial lead or axial lead components. Surface mount caps should be
placed on the component side of the PCB to minimize inductance caused by board vias. Any vias,
especially to ground, should be as large as practical
to reduce their inductive effects.
VREF Decoupling
The VREFOUT pin provides a 1.235 V reference
for the internal DACs. VREFOUT is only intended
to drive VREFIN. Do not connect to an external
load. A small bypass cap, however, may be placed
on VREFOUT to reduce noise. Usually a 0.1uF
MLC surface mount capacitor is sufficient.
Digital Interconnect
Power and Ground Planes
The digital inputs and outputs of the CS4952/3
should be isolated from the analog outputs as much
as possible. Use separate signal layers whenever
possible and do not route digital signals over the
analog power and ground planes.
The power and ground planes need isolation gaps
of at 0.05” to minimize digital switching noise effects on the analog signals and components. A split
analog/digital ground plane should be connected at
one point as close as possible to the CS4952/3. A
split analog/digital power plane should be connected at one point as close as possible to the power entry point and decoupled properly.
Noise from the digital section is directly related to
the digital edge rates used. Ringing, overshoot, undershoot, and ground bounce are all related to edge
rate. Use lower speed logic such as HCMOS for the
host port interface to reduce switching noise. For
the video input ports, higher speed logic is required, but use the slowest practical edge rate to reduce noise.
Power Supply Decoupling
To reduce digital noise, it is important to match the
source impedance, line impedance, and load impedance as much as possible. Generally, if the line
length is greater than one fourth the signal edge
rate, line termination is necessary. Ringing may
also be reduced by damping the line with a series
resistor (22 - 150 Ω). Under extreme cases, it may
Start by reducing power supply ripple and wiring
harness inductance by placing a large (33 - 100uF)
capacitor as close to the power entry point as possible. Use separate power planes or traces for the
digital and analog sections even if they use the
36
DS223PP2
CS4952/53
be advisable to use microstrip techniques to further
reduce radiated switching noise if very fast edge
rates (<2ns) are used. If microstrip techniques are
used, split the analog and digital ground planes and
use proper RF decoupling techniques.
Analog Interconnect
The CS4952/3 should be located as close as possible
to the output connectors to minimize noise pickup
and reflections due to impedance mismatch. All unused analog outputs should be placed in shutdown.
This reduces the total power that the CS4952/3 requires, and eliminates the impedance mismatch presented by an unused connector. The analog outputs
should not overlay the analog power plane to maximize high frequency power supply rejection.
Analog Output Protection
To minimize the possibility of damage to the analog out put sections, make sure that all video connectors are well grounded. The connector ground
should have a good DC ground path to the analog
and digital power supply grounds. If no DC (and
low frequency) path is present, improperly grounded equipment may impose damaging reverse currents on the video out lines. Therefore, it is also a
good idea to use output filters that are AC coupled
to avoid any problems.
ESD Protection
External DAC Output Filter
If an output filter is required for the composite
and/or S-video outputs of the CS4952/53, the following low pass filter in Figure 15 can be used.
2.2µH
OUT
IN
C1
330pF
C2
220pF
C CABLE
C 2 should be chosen so that C 1 = C 2 + C CABLE
Figure 15. Low Pass Filter
DS223PP2
37
CS4952/53
DEVICE PINOUT - 44 PLCC
VAA
GND
C
VAA
Y
CVBS37
VREFOUT
CVBS75
VREFIN
TEST
ISET
V0
VAA
V1
6
4
2
1 44
42
GND
40
7
39
8
38
V3
9
37
V4
10
V2
V5
V6
V7
FIELD
HSYNC/CB
36
CS4952/3-CL
44-pin
PLCC
Top View
11
12
13
35
34
33
14
32
15
31
16
30
17
29
18
20
22
24
26
28
RESET
SCL
SDA
INT
CLKIN
WR
RD
PDAT0
VSYNC
PDAT1
XTAL
PDAT2
ADDR
PDAT3
VAA
PDAT4
GND
PDAT5
GND
PDAT6
PDAT7
38
DS223PP2
CS4952/53
PLCC Pin Description
Pin Name
V [7:0]
CLK
ADDR
XTAL
HSYNC/CB
VSYNC
FIELD
RD
WR
PDAT [7:0]
SDA
SCL
CVBS75
CVBS37
Y
C
VREFOUT
VREFIN
ISET
INT
RESET
TEST
VAA
GND
DS223PP2
Pin Number
14, 13, 12, 11, 10, 9, 8, 7
33
19
18
16
17
15
31
32
23,24,25,26,27,28,29,30
Type
IN
IN
IN
OUT
I/O
I/O
OUT
IN
IN
I/O
35
I/O
36
5
4
43
44
42
41
40
34
37
6
1, 3, 20, 39
2, 22, 21, 38
IN
CURRENT
CURRENT
CURRENT
CURRENT
OUT
IN
OUT
OUT
IN
IN
PS
PS
Description
Digital video data inputs
27 MHz input clock
Address enable line / subcarrier crystal input
subcarrier crystal output
Active low horizontal sync, or composite blank signal
Active low vertical sync.
Video field ID. Selectable polarity
Host parallel port read strobe, active low
Host parallel port write strobe, active low
Host parallel port/ general purpose I/O
I2C data
I2C clock input
Composite video output for driving 75 Ω loads
Composite video output for driving 37.5 Ω loads
Luminance analog output for driving 37.5 Ω loads
Chrominance analog output for driving 37.5 Ω loads
Internal voltage reference output
External voltage reference input
DAC current set
Interrupt output, active high
Active low master reset
TEST pin. Ground for normal operation
+5 V supply
Ground
39
CS4952/53
44L PLCC PACKAGE DRAWING
e
D2/E2
E1 E
B
D1
A1
D
A
INCHES
DIM
A
A1
B
D
D1
D2
E
E1
E2
e
MIN
0.165
0.090
0.013
0.685
0.650
0.590
0.685
0.650
0.590
0.040
MAX
0.180
0.120
0.021
0.695
0.656
0.630
0.695
0.656
0.630
0.060
MILLIMETERS
MIN
MAX
4.043
4.572
2.205
3.048
0.319
0.533
16.783
17.653
15.925
16.662
14.455
16.002
16.783
17.653
15.925
16.662
14.455
16.002
0.980
1.524
JEDEC # : MS-018
40
DS223PP2
CS4952/53
DEVICE PINOUT - 44 TQFP
VAA
GND
C
VAA
Y
CVBS37
VREFOUT
CVBS75
VREFIN
TEST
ISET
V0
VAA
V1
V2
V3
V4
V5
V6
V7
FIELD
HSYNC/CB
44
42
40
38
36
GND
34
1
33
2
32
3
31
4
30
CS4952/3-CL
44-pin
TQFP
Top View
5
6
7
8
29
28
9
10
11
12
14
16
18
20
22
RESET
SCL
SDA
INT
27
26
CLKIN
25
24
WR
23
RD
PDAT0
VSYNC
PDAT1
XTAL
PDAT2
ADDR
PDAT3
VAA
PDAT4
GND
PDAT5
GND
PDAT6
PDAT7
DS223PP2
41
CS4952/53
TQFP Pin Description
Pin Name
V [7:0]
CLKIN
ADDR
XTAL
HSYNC/CB
VSYNC
FIELD
RD
WR
PDAT [7:0]
SDA
SCL
CVBS75
CVBS37
Y
C
VREFOUT
VREFIN
ISET
INT
RESET
TEST
VAA
GND
42
Pin Number
8, 7, 6, 5, 4, 3, 2, 1
27
13
12
10
11
9
25
26
17,18,19,20,21,22,23,24
Type
IN
IN
IN
OUT
I/O
I/O
OUT
IN
IN
I/O
29
I/O
30
43
42
37
38
36
35
34
28
31
44
14, 33, 39, 41
15, 16, 32, 40
IN
CURRENT
CURRENT
CURRENT
CURRENT
OUT
IN
OUT
OUT
IN
IN
PS
PS
Description
Digital video data inputs
27 MHz input clock
Address enable line / subcarrier crystal input
subcarrier crystal output
Active low horizontal sync, or composite blank signal
Active low vertical sync.
Video field ID. Selectable polarity
Host parallel port read strobe, active low
Host parallel port write strobe, active low
Host parallel port/ general purpose I/O
I2C data
I2C clock input
Composite video output for driving 75 Ω loads
Composite video output for driving 37.5 Ω loads
Luminance analog output for driving 37.5 Ω loads
Chrominance analog output for driving 37.5 Ω loads
Internal voltage reference output
External voltage reference input
DAC current set
Interrupt output, active high
Active low master reset
TEST pin. Ground for normal operation
+5 V supply
Ground
DS223PP2
CS4952/53
44L TQFP PACKAGE DRAWING
∝
L
1
e
E1
E
B
A1
D1
A
D
INCHES
DIM
A
A1
B
D
D1
E
E1
e
L
∝
MIN
0.000
0.002
0.012
0.478
0.404
0.478
0.404
0.029
0.018
0.000
MAX
0.065
0.006
0.018
0.502
0.412
0.502
0.412
0.037
0.030
7.000
MILLIMETERS
MIN
MAX
0.000
1.600
0.050
0.150
0.300
0.450
11.700
12.300
9.900
10.100
11.700
12.300
9.900
10.100
0.700
0.900
0.450
0.750
0.000
7.000
JEDEC # : MS-026
DS223PP2
43
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