CS5484 Four Channel Energy Measurement IC Features & Description Description • The CS5484 is a high-accuracy, four-channel, energy measurement analog front end. • • • • • • • • • • • • • • • • • Superior Analog Performance with Ultra-low Noise Level and High SNR Energy Measurement Accuracy of 0.1% over 4000:1 Dynamic Range Current RMS Measurement Accuracy of 0.1% over 1000:1 Dynamic Range 4 Independent 24-bit, 4th-order, Delta-Sigma Modulators for Voltage and Current Measurements 4 Configurable Digital Outputs for Energy Pulses, Zero-crossing, or Energy Direction Supports Shunt Resistor, CT, and Rogowski Coil Current Sensors On-chip Measurements/Calculations: - Active, Reactive, and Apparent Power - RMS Voltage and Current - Power Factor and Line Frequency - Instantaneous Voltage, Current, and Power Overcurrent, Voltage Sag, and Voltage Swell Detection Ultra-fast On-chip Digital Calibration Internal Register Protection via Checksum and Write Protection UART/SPI™ Serial Interface On-chip Temperature Sensor On-chip Voltage Reference (25ppm/°C Typ.) Single 3.3V Power Supply Ultra-fine Phase Compensation Low Power Consumption: <13mW Power Supply Configurations - GNDA = GNDD = 0V, VDDA = +3.3V 5mmx5mm 28-pin QFN Package ORDERING INFORMATION See Page 67. VDDA IIN1+ IIN1- The CS5484 incorporates independent 4th order Delta-Sigma analog-to-digital converters for every channel, reference circuitry, and the proven EXL signal processing core to provide active, reactive, and apparent energy measurement. In addition, RMS and power factor calculations are available. Calculations are output through a configurable energy pulse, or direct UART/SPI™ serial access to on-chip registers. Instantaneous current, voltage, and power measurements are also available over the serial port. Multiple serial options are offered to allow customer flexibility. The SPI provides higher speed, and the 2-wire UART minimizes the cost of isolation where required. Four configurable digital outputs provide energy pulses, zero-crossing, energy direction, and interrupt functions. Interrupts can be generated for a variety of conditions including voltage sag or swell, overcurrent, and more. On-chip register integrity is assured via checksum and write protection. The CS5484 is designed to interface to a variety of voltage and current sensors including shunt resistors, current transformers, and Rogowski coils. On-chip functionality makes digital calibration simple and ultra-fast, minimizing the time required at the end of the customer production line. Performance across temperature is ensured with an on-chip voltage reference with low drift. A single 3.3V power supply is required, and power consumption is low at <13mW. To minimize space requirements, the CS5484 is offered in a low-cost, 5mm x5mm 28-pin QFN package. RESET VDDD PGA 4 th Order Modulator Digital Filter HPF Option PGA 4 th Order Modulator Digital Filter HPF Option 4 th Order Modulator Digital Filter HPF Option 4 th Order Modulator Digital Filter HPF Option CS5484 SSEL IIN2+ IIN2- VIN1+ VIN1- 10x UART/SPI Serial Interface CS RX / SDI TX / SDO SCLK Calculation DO1 VIN2+ VIN2- 10x M U X Configurable Digital Outputs DO2 DO3 DO4 Temperature Sensor System Clock Clock Generator MODE GNDA Cirrus Logic, Inc. http://www.cirrus.com XIN XOUT CPUCLK Copyright Cirrus Logic, Inc. 2012 (All Rights Reserved) Voltage Reference VREF+ VREF- GNDD JUN’12 DS981F2 CS5484 TABLE OF CONTENTS 1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 2. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 2.1 Analog Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 2.1.1 Voltage Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 2.1.2 Current Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 2.1.3 Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 2.1.4 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 2.2 Digital Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 2.2.1 Reset Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 2.2.2 CPU Clock Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 2.2.3 Digital Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 2.2.4 UART/SPI™ Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 2.2.5 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 2.2.6 UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 2.2.7 MODE Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 3. Characteristics and Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 4. Signal Flow Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.1 Analog-to-Digital Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.2 Decimation Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.3 IIR Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.4 Phase Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.5 DC Offset and Gain Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.6 High-pass and Phase Matching Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.7 Digital Integrators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.8 Low-rate Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.8.1 Fixed Number of Samples Averaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.8.2 Line-cycle Synchronized Averaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 4.8.3 RMS Current and Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.8.4 Active Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 4.8.5 Reactive Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.8.6 Apparent Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.8.7 Peak Voltage and Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.8.8 Power Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 4.9 Average Active Power Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 4.10 Average Reactive Power Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.1 Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.2 Power Saving Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.3 Zero-crossing Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.4 Line Frequency Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.5 Energy Pulse Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.5.1 Pulse Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.5.2 Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.6 Voltage Sag, Voltage Swell, and Overcurrent Detection . . . . . . . . . . . . . . . . . . . . .24 2 DS981F2 CS5484 5.7 Phase Sequence Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.8 Temperature Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.9 Anti-creep . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.10 Register Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.10.1 Write Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.10.2 Register Checksum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6. Host Commands and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.1 Host Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.1.1 Memory Access Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.1.1.1 Page Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.1.1.2 Register Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.1.1.3 Register Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.1.2 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.1.3 Checksum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.1.4 Serial Time Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.2 Hardware Registers Summary (Page 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.3 Software Registers Summary (Page 16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.4 Software Registers Summary (Page 17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.5 Software Registers Summary (Page 18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.6 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7. System Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 7.1 Calibration in General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 7.1.1 Offset Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 7.1.1.1 DC Offset Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 7.1.1.2 AC Offset Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 7.1.2 Gain Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 7.1.3 Calibration Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 7.2 Phase Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 7.3 Temperature Sensor Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 7.3.1 Temperature Offset and Gain Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 8. Basic Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 9. Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 10. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 11. Environmental, Manufacturing, and Handling Information . . . . . . . . . . . . . . . . . . . . . 67 12. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 DS981F2 3 CS5484 LIST OF FIGURES Figure 1. Oscillator Connections................................................................................................... 7 Figure 2. Multi-device UART Connections.................................................................................... 8 Figure 3. UART Serial Frame Format ........................................................................................... 8 Figure 4. Active Energy Load Performance.................................................................................. 9 Figure 5. Reactive Energy Load Performance............................................................................ 10 Figure 6. IRMS Load Performance ............................................................................................. 10 Figure 7. SPI Data and Clock Timing ......................................................................................... 15 Figure 8. Multi-Device UART Timing .......................................................................................... 15 Figure 9. Signal Flow for V1, I1, P1, and Q1 Measurements ..................................................... 17 Figure 10. Signal Flow for V2, I2, P2, and Q2 Measurements ................................................... 17 Figure 11. Low-rate Calculations ................................................................................................ 18 Figure 12. Power-on Reset Timing ............................................................................................. 21 Figure 13. Zero-crossing Level and Zero-crossing Output on DOx ............................................ 22 Figure 14. Energy Pulse Generation and Digital Output Control ................................................ 23 Figure 15. Sag, Swell, and Overcurrent Detect .......................................................................... 24 Figure 16. Phase Sequence A, B, C for Rising Edge Transition ................................................ 25 Figure 17. Phase Sequence C, B, A for Rising Edge Transition ................................................ 26 Figure 18. Byte Sequence for Page Select................................................................................. 27 Figure 19. Byte Sequence for Register Read ............................................................................ 27 Figure 20. Byte Sequence for Register Write ............................................................................. 27 Figure 21. Byte Sequence for Instructions.................................................................................. 27 Figure 22. Byte Sequence for Checksum ................................................................................... 28 Figure 23. Calibration Data Flow ................................................................................................ 62 Figure 24. T Register vs. Force Temp ........................................................................................ 64 Figure 25. Typical Connection (Single-phase, 3-wire, 12S Electricity Meter) ............................. 65 LIST OF TABLES Table 1. POR Thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 2. Command Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 3. Instruction Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4 DS981F2 CS5484 1. OVERVIEW The CS5484 is a CMOS power measurement integrated circuit using four analog-to-digital converters to measure two line voltages and two currents. Optionally, voltage2 channel can be used for temperature measurement. It calculates active, reactive, and apparent power as well as RMS voltage and current and peak voltage and current. It handles other system-related functions, such as energy pulse generation, voltage sag and swell, overcurrent and zero-crossing detection, and line frequency measurement. The CS5484 is optimized to interface to current transformers, shunt resistors, or Rogowski coils for current measurement and to resistive dividers or voltage transformers for voltage measurement. Two full-scale ranges are provided on the current inputs to accommodate different types of current sensors. The CS5484’s four differential inputs have a common-mode input range from analog ground (GNDA) to the positive analog supply (VDDA). An on-chip voltage reference (typically 2.4 volts) is generated and provided at analog output, VREF±. Four digital outputs (DO1, DO2, DO3, and DO4) provide a variety of output signals, and depending on the mode selected, provide energy pulses, zero-crossings, or other choices. The CS5484 includes a UART/SPI™ serial host interface to an external microcontroller. The serial select (SSEL) pin is used to configure the serial port to be a SPI or UART. SPI signals include serial data input (SDI), serial data output (SDO), and serial clock (SCLK). UART signals include serial data input (RX) and serial data output (TX). A chip select (CS) signal allows multiple CS5484s to share the same serial interface with the microcontroller. DS981F2 5 CS5484 XOUT VDDD GNDD CPUCLK MODE SSEL CS 2. PIN DESCRIPTIONS 28 27 26 25 24 23 22 XIN 1 21 SCLK RESET 2 20 RX/SDI IIN1- 3 19 TX/SDO IIN1+ 4 18 DO4 17 DO3 16 DO2 15 DO1 8 9 10 11 12 13 14 GNDA VDDA 7 VREF+ VIN1+ Top-Down View 28-pin QFN Package VREF- 6 IIN2+ VIN2+ IIN2- 5 VIN1- VIN2- Thermal Pad Do Not Connect Digital Pins and Serial Data I/O Digital Outputs Reset Serial Data I/O 15,16, 17,18 2 19,20 DO1, DO2, DO3, DO4 — Configurable digital outputs for energy pulses, interrupt, energy direction, and zero-crossings. RESET — An active-low Schmitt-trigger input used to reset the chip. TX/SDO, RX/SDI — UART/SPI serial data output/input. Serial Clock Input 21 SCLK — Serial clock for the SPI. Chip Select 22 CS — Chip select for the UART/SPI. Serial Mode Select 23 SSEL — Selects the type of serial interface, UART or SPI™. Logic level one - UART selected. Logic level zero - SPI selected. Operating Mode Select 24 MODE — Connect to VDDA for proper operation. Analog Inputs/Outputs Voltage Inputs 7,8,6,5 Current Inputs 4,3,10,9 Voltage Reference Input VIN1+, VIN1-, VIN2+, VIN2- — Differential analog inputs for the voltage channels. IIN1+, IIN1-, IIN2+, IIN2- — Differential analog inputs for the current channels. 12,11 VREF+, VREF- — The internal voltage reference. A 0.1µF bypass capacitor is required between these two pins. Internal Digital Supply 27 VDDD — Decoupling pin for the internal 1.8V digital supply. A 0.1µF bypass capacitor is required between this pin and GNDD. Digital Ground 26 GNDD — Digital ground. Positive Analog Supply 14 VDDA — The positive 3.3V analog supply. Analog Ground 13 GNDA — Analog ground. Power Supply Connections Clock Generator Crystal In Crystal Out CPU Clock Output Thermal Pad 6 1,28 25 - XIN, XOUT — Connect to an external quartz crystal. Alternatively, an external clock can be supplied to the XIN pin to provide the system clock for the device. CPUCLK — Output of on-chip oscillator which can drive one standard CMOS load. No Electrical Connection. DS981F2 CS5484 2.1 Analog Pins The CS5484 has two differential inputs (VIN1VIN2) for voltage input and two differential inputsIIN1 IIN2) for current1 and current2 inputs. The CS5484 also has two voltage reference pins (VREF) between which a bypass capacitor should be placed. XIN XOUT 2.1.1 Voltage Inputs The output of the line voltage resistive divider or transformer is connected to the VIN1 or VIN2 input pins of the CS5484. The voltage channel is equipped with a 10x, fixed-gain amplifier. The full-scale signal level that can be applied to the voltage channel is ±250mV. If the input signal is a sine wave, the maximum RMS voltage is 250mVp/ 2 176.78mVRMS, which is approximately 70.7% of maximum peak voltage. 2.1.2 Current Inputs The output of the current-sensing shunt resistor, transformer, or Rogowski coil is connected to the IIN1 or IIN2 input pins of the CS5484. To accommodate different current-sensing elements, the current channel incorporates a programmable gain amplifier (PGA) with two selectable input gains, as described in the Config0 register description (see section 6.6.1 Configuration 0 (Config0) – Page 0, Address 0 on page 35.) There is a 10x gain setting and a 50x gain setting. The full-scale signal level for current channels is ±50mV and ±250mV for 50x and 10x gain settings, respectively. If the input signal is a sine wave, the maximum RMS voltage is 35.35mVRMS or 176.78mVRMS, which is approximately 70.7% of maximum peak voltage. 2.1.3 Voltage Reference The CS5484 generates a stable voltage reference of 2.4V between the VREF pins. The reference system also requires a filter capacitor of at least 0.1µF between the VREF pins. The reference system is capable of providing a reference for the CS5484 but has limited ability to drive external circuitry. It is strongly recommended that nothing other than the required filter capacitor be connected to the VREF pins. 2.1.4 Crystal Oscillator An external, 4.096MHz quartz crystal can be connected to the XIN and XOUT pins, as shown in Figure 1. To reduce system cost, each pin is supplied with an on-chip load capacitor. DS981F2 C1 = 22pF C2 = 22pF Figure 1. Oscillator Connections Alternatively, an external connected to the XIN pin. clock source can be 2.2 Digital Pins 2.2.1 Reset Input The active-low RESET pin, when asserted for longer than 120µs, will halt all CS5484 operations and reset internal hardware registers and states. When de-asserted, an initialization sequence begins, setting default register values. To prevent erroneous noise-induced resets to the CS5484, an external pull-up resistor and a decoupling capacitor are necessary on the RESET pin. 2.2.2 CPU Clock Output A logic-level clock output (CPUCLK) is provided at the crystal frequency to drive another CS5484 IC or external microcontroller. Writing ‘1’ to bit CPUCLK_ON of the Config0 register enables the CPU clock output. After the CPU clock output is enabled, it can be disabled only by a power-on reset (POR) or by writing ‘0’ to the CPUCLK_ON bit. A hardware reset through pin/RESET or a software reset instruction through the serial interface will not disable the CPU clock output. Two phase choices are available on the CPUCLK pin through bit iCPUCLK of the Config0 register. Different from the CPUCLK_ON bit, the iCPUCLK bit can be cleared by a POR, a hardware reset, a software reset instruction, or a register write. 2.2.3 Digital Outputs The CS5484 provides four configurable digital outputs (DO1-DO4). They can be configured to output energy pulses, interrupt, zero-crossings, or energy directions. Refer to section 6.6.2 Configuration 1 (Config1) – Page 0, Address 1 on page 36 for more details. 7 CS5484 2.2.4 UART/SPI™ Serial Interface The CS5484 provides five pins—SSEL, RX/SDI, TX/SDO, CS, and SCLK—for communication between a host microcontroller and the CS5484. requires a separate CS signal for enabling communication to that slave. The multi-device UART mode connections are shown in Figure 2. SLAVE 0 SSEL is an input that, when low, indicates to the CS5484 to use the SPI port as the serial interface to communicate with the host microcontroller. The SSEL pin has an internal weak pull-up. When the SSEL pin is left unconnected or pulled high externally, the UART port is used as the serial interface. UART MASTER CS0 TX RX CS1 CS RX TX CSN SLAVE 1 CS RX TX 2.2.5 SPI The CS5484 provides a Serial Peripheral Interface (SPI) that operates as a slave device in 4-wire mode and supports multiple slaves on the SPI bus. The 4-wire SPI includes CS, SCLK, SDI, and SDO signals. SLAVE N CS RX TX CS is the chip select input for the CS5484 SPI port. A high logic level de-asserts it, tri-stating the SDO pin and clearing the SPI interface. A low logic level enables the SPI port. Although the CS pin may be tied low for systems that do not require multiple SDO drivers, using the CS signal is strongly recommended to achieve more reliable SPI communications. The multi-device UART mode timing diagram provides the timing requirements for the CS control (see Figure 8. Multi-Device UART Timing on Page 15). SCLK is the serial clock input for the CS5484 SPI port. Serial data changes as a result of the falling edge of SCLK and is valid at the rising edge. The SCLK pin is a Schmitt-trigger input. The CS5484 UART operates in 8-bit mode, which transmits a total of 10 bits per byte. Data is transmitted and received LSB first, with one start bit, eight data bits, and one stop bit. Figure 2. Multi-device UART Connections SDI is the serial data input to the CS5484. SDO is the serial data output from the CS5484. The CS5484 SPI transmits and receives data MSB first. Refer to Switching Characteristics on page 14 and Figure 7 on page 15 for more detailed information about SPI timing. 2.2.6 UART The CS5484 device contains an asynchronous, full-duplex UART. The UART may be used in either standard 2-wire communication mode (RX/TX) for connecting a single device or 3-wire communication mode (RX/TX/ CS) for connecting multiple devices. When connecting a single CS5484 device, CS should be held low to enable the UART. Multiple CS5484 devices can communicate to the same master UART in the 3-wire mode by pulling a slave CS pin low during data transmissions. Common RX and TX signals are provided to all the slave devices, and each slave device 8 IDLE START 0 1 2 3 4 5 6 7 STOP IDLE DATA Figure 3. UART Serial Frame Format The baud rate is defined in the SerialCtrl register. After chip reset, the default baud rate is 600, if MCLK is 4.096MHz. The baud rate is based on the contents of bits BR[15:0] in the SerialCtrl register and is calculated as follows: BR[15:0] = Baud Rate x (524288/MCLK) or Baud Rate = BR[15:0] / (524288/MCLK) The maximum baud rate is 512K if MCLK is 4.096MHz. 2.2.7 MODE Pin The MODE pin must be tied to VDDA for normal operation. The MODE pin is used primarily for factory test procedures. DS981F2 CS5484 3. CHARACTERISTICS AND SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS Parameter Positive Analog Power Supply Specified Temperature Range Symbol VDDA TA Min 3.0 -40 Typ 3.3 - Max 3.6 +85 Unit V °C POWER MEASUREMENT CHARACTERISTICS Parameter Active Energy (Note 1 and 2) Reactive Energy (Note 1 and 2) Apparent Power (Note 1 and 3) Current RMS (Note 1, 3, and 4) Symbol Min Typ Max Unit All Gain Ranges Current Channel Input Signal Dynamic Range 4000:1 PAvg - ±0.1 - % All Gain Ranges Current Channel Input Signal Dynamic Range 4000:1 QAvg - ±0.1 - % All Gain Ranges Current Channel Input Signal Dynamic Range 1000:1 S - ±0.1 - % All Gain Ranges Current Channel Input Signal Dynamic Range 1000:1 IRMS - ±0.1 - % Voltage Channel Input Signal Dynamic Range 20:1 VRMS - ±0.1 - % PF - ±0.1 - % Voltage RMS (Note 1 and 3) Power Factor (Note 1 and 3) Notes: 1. 2. 3. 4. All Gain Ranges Current Channel Input Signal Dynamic Range 1000:1 Specifications guaranteed by design and characterization. Active energy is tested with power factor (PF) = 1.0. Reactive energy is tested with Sin() = 1.0. Energy error measured at system level using a single energy pulse. Where: 1) One energy pulse = 0.5Wh or 0.5Varh; 2) VDDA = +3.3V, TA = 25°C, MCLK = 4.096MHz; 3) System is calibrated. Calculated using register values; N ≥ 4000. IRMS error calculated using register values. 1) VDDA = +3.3V; TA = 25°C; MCLK = 4.096MHz; 2) AC offset calibration applied. TYPICAL LOAD PERFORMANCE • • • Energy error measured at system level using single energy pulse; where one energy pulse = 0.5Wh or 0.5Varh IRMS error calculated using register values VDDA = +3.3V; TA = 25°C; MCLK = 4.096MHz 1 Percent Error (%) 0.5 0 Lagging PF = 0.5 Leading PF = 0.5 PF = 1 -0.5 -1 0 500 1000 1500 2000 2500 3000 3500 4000 4500 Current Dynamic Range (x : 1) Figure 4. Active Energy Load Performance DS981F2 9 CS5484 1 Percent Error (%) 0.5 0 Lagging sin(੮) = 0.5 Leading sin(੮) = 0.5 sin(੮) = 1 -0.5 -1 0 500 1000 1500 2000 2500 3000 3500 4000 4500 Current Dynamic Range (x : 1) Figure 5. Reactive Energy Load Performance 1 Percent Error (%) 0.5 0 IRMS Error IRMS Error -0.5 -1 0 500 1000 1500 Current Dynamic range (x : 1) Figure 6. IRMS Load Performance 10 DS981F2 CS5484 ANALOG CHARACTERISTICS • • • • Min / Max characteristics and specifications are guaranteed over all Recommended Operating Conditions. Typical characteristics and specifications are measured at nominal supply voltages and TA = 25°C. VDDA = +3.3V ±10%; GNDA = GNDD = 0V. All voltages with respect to 0V. MCLK = 4.096MHz. Parameter Symbol Min Typ Max Unit Analog Inputs (Current Channels) Common Mode Rejection (DC, 50, 60Hz) CMRR Common Mode+Signal Differential Full-scale Input Range 80 - - dB -0.25 - VDDA V [(IIN+) – (IIN-)] (Gain = 10) (Gain = 50) IIN - 250 50 - mVP mVP Total Harmonic Distortion (Gain = 50) THD 90 100 - dB SNR - 80 80 - dB dB Signal-to-Noise Ratio (SNR) (Gain = 10) (Gain = 50) Crosstalk from Voltage Inputs at Full Scale (50, 60Hz) - -115 - dB Crosstalk from Current Input at Full Scale (50, 60Hz) - -115 - dB Input Capacitance IC - 27 - pF Effective Input Impedance EII 30 - - k Offset Drift (Without the High-pass Filter) OD - 4.0 - µV/°C Noise (Referred to Input) (Gain = 10) (Gain = 50) NI - 15 3.5 - µVRMS µVRMS Power Supply Rejection Ratio (60Hz) (Gain = 10) (Gain = 50) PSRR 60 68 65 75 - dB dB (DC, 50, 60Hz) CMRR 80 - - dB -0.25 - VDDA V VIN - 250 - mVP Total Harmonic Distortion THD 80 88 - dB Signal-to-Noise Ratio (SNR) SNR - 73 - dB (Note 7) Analog Inputs (Voltage Channels) Common Mode Rejection Common Mode+Signal Differential Full-scale Input Range Crosstalk from Current Inputs at Full Scale [(VIN+) – (VIN-)] - -115 - dB Input Capacitance IC - 2.0 - pF Effective Input Impedance EII 2 - - M Noise (Referred to Input) NV - 40 - µVRMS Offset Drift (Without the High-pass Filter) OD - 16.0 - µV/°C PSRR 60 65 - dB T - ±5 - °C Power Supply Rejection Ratio (Note 7) (50, 60Hz) (60Hz) (Gain = 10) Temperature Temperature Accuracy DS981F2 (Note 6) 11 CS5484 Parameter Symbol Min Typ Max Unit PSCA - 3.9 - mA PC - 12.9 4.5 - mW mW Power Supplies Power Supply Currents (Active State) IA+ (VDDA = +3.3V) Power Consumption (Note 5) Notes: Active State (VDDA = +3.3V) Stand-by State 5. 6. 7. All outputs unloaded. All inputs CMOS level. Temperature accuracy measured after calibration is performed. Measurement method for PSRR: VDDA = +3.3V, a 150mV (zero-to-peak) (60Hz) sine wave is imposed onto the +3.3V DC supply voltage at the VDDA pin. The “+” and “-” input pins of both input channels are shorted to GNDA. The CS5484 is then commanded to continuous conversion acquisition mode, and digital output data is collected for the channel under test. The (zero-to-peak) value of the digital sinusoidal output signal is determined, and this value is converted into the (zero-to-peak) value of the sinusoidal voltage (measured in mV) that would need to be applied at the channel’s inputs in order to cause the same digital sinusoidal output. This voltage is then defined as Veq PSRR is (in dB): 150 PSRR = 20 log ----------V eq VOLTAGE REFERENCE Parameter Reference Symbol Min Typ Max Unit VREF +2.3 +2.4 +2.5 V (Note 9) TCVREF - 25 - ppm/°C (Note 10) VR - 30 - mV (Note 8) Output Voltage Temperature Coefficient Load Regulation Notes: 8. 9. It is strongly recommended that no connection other than the required filter capacitor be made to VREF±. The voltage at VREF± is measured across the temperature range. From these measurements the following formula is used to calculate the VREF temperature coefficient: VREF MAX – VREFMIN 1 TC VREF = ------------------------------------------------------------ ---------------------------------------------- 1.0 10 6 T A MAX – TA MIN VREF AVG 10. 12 Specified at maximum recommended output of 1µA sourcing. VREF is a sensitive signal; the output of the VREF circuit has a high output impedance so that the 0.1µF reference capacitor provides attenuation even to low-frequency noise, such as 50Hz noise on the VREF output. Therefore VREF intended for the CS5484 only and should not be connected to any external circuitry. The output impedance is sufficiently high that standard digital multi-meters can significantly load this voltage. The accuracy of the metrology IC cannot be guaranteed when a multimeter or any component other than the 0.1µF capacitor is attached to VREF. If it is desired to measure VREF for any reason other than a very course indicator of VREF functionality, Cirrus recommends a very high input impedance multimeter such as the Keithley Model 2000 Digital Multimeter be used. Cirrus cannot guarantee the accuracy of the metrology with this meter connected to VREF. DS981F2 CS5484 DIGITAL CHARACTERISTICS • • • • Min / Max characteristics and specifications are guaranteed over all Recommended Operating Conditions. Typical characteristics and specifications are measured at nominal supply voltages and TA = 25°C. VDDA = +3.3V ±10%; GNDA = GNDD = 0V. All voltages with respect to 0V. MCLK = 4.096MHz. Parameter Master Clock Characteristics XIN Clock Frequency Filter Characteristics Phase Compensation Range Input Sampling Rate Digital Filter Output Word Rate High-pass Filter Corner Frequency Input/Output Characteristics High-level Input Voltage (All Pins) Internal Gate Oscillator Symbol Min Typ Max Unit MCLK 2.5 4.096 5 MHz -10.79 - MCLK/8 MCLK/1024 2.0 +10.79 - ° Hz Hz Hz VIH 0.6(VDDA) - - V VIL - - 0.6 V ±1 0.5 0.5 ±10 V V V V µA (60Hz, OWR = 4000Hz) (Both channels) OWR -3dB Low-level Input Voltage (All Pins) Input Leakage Current Iin VDDA-0.3 VDDA-0.3 - 3-state Leakage Current IOZ - - ±10 µA Digital Output Pin Capacitance Cout - 5 - pF High-level Output Voltage (Note 12) Low-level Output Voltage (Note 12) Notes: 11. 12. DS981F2 DO1-DO4, Iout = +10mA All Other Outputs, Iout = +5mA VOH DO1-DO4, Iout = -12mA All Other Outputs, Iout = -5mA VOL All measurements performed under static conditions. XOUT pin used for crystal only. Typical drive current<1mA. 13 CS5484 SWITCHING CHARACTERISTICS • • • • Min / Max characteristics and specifications are guaranteed over all Recommended Operating Conditions. Typical characteristics and specifications are measured at nominal supply voltages and TA = 25°C. VDDA = +3.3V ±10%; GNDA = GNDD = 0V. All voltages with respect to 0V. Logic Levels: Logic 0 = 0V, Logic 1 = VDDA. Parameter Symbol Min Typ Max Unit DO1-DO4 Any Digital Output Except DO1-DO4 trise - 50 1.0 - µs ns DO1-DO4 Any Digital Output Except DO1-DO4 tfall - 50 1.0 - µs ns XTAL = 4.096 MHz (Note 14) tost - 60 - ms SCLK - - 2 MHz t1 t2 200 200 - - ns ns CS Enable to SCLK Falling t3 50 - - ns Data Set-up Time prior to SCLK Rising t4 50 - - ns Data Hold Time After SCLK Rising t5 100 - - ns SCLK Rising Prior to CS Disable t6 1 - - µs SCLK Falling to New Data Bit t7 - - 150 ns CS Rising to SDO Hi-Z t8 - - 250 ns CS Enable to RX START bit t9 5 - - ns STOP bit to CS Disable t10 1 - - µs CS Disable to TX IDLE Hold Time t11 - - 250 ns Rise Times (Note 13) Fall Times (Note 13) Start-up Oscillator Start-up Time SPI Timing Serial Clock Frequency Serial Clock (Note 15) Pulse Width High Pulse Width Low UART Timing Notes: 14 13. 14. 15. Specified using 10% and 90% points on waveform of interest. Output loaded with 50pF. Oscillator start-up time varies with crystal parameters. This specification does not apply when using an external clock source. The maximum SCLK is 2MHz during a byte transaction. The minimum 1µs idle time is required on the SCLK between two consecutive bytes. DS981F2 CS5484 CS t6 t1 t3 SCLK t2 t7 SDO MSB t4 SDI t8 MSB-1 LSB INTERMEDIATE BITS t5 MSB MSB-1 INTERMEDIATE BITS LSB Figure 7. SPI Data and Clock Timing CS t10 t9 TX RX START IDLE START LSB DATA MSB STOP IDLE LSB DATA MSB OPTIONAL OVERLAP INSTRUCTION * t11 IDLE STOP STOP * Reading registers during the optional overlap instruction requires the start to occur during the last byte transmitted by the part Figure 8. Multi-Device UART Timing DS981F2 15 CS5484 ABSOLUTE MAXIMUM RATINGS Parameter DC Power Supplies Input Current (Note 16) (Notes 17 and 18) Input Current for Power Supplies Symbol Min Typ Max Unit VDDA -0.3 - +4.0 V IIN - - ±10 mA - - - ±50 - Output Current (Note 19) IOUT - - 100 mA Power Dissipation (Note 20) PD - - 500 mW Input Voltage (Note 21) VIN - 0.3 - (VDDA) + 0.3 V 2 Layer Board 4 Layer Board JA - 53 43 - °C/W °C/W Ambient Operating Temperature TA - 40 - 85 °C Storage Temperature Tstg - 65 - 150 °C Junction-to-Ambient Thermal Impedance Notes: 16. 17. 18. 19. 20. 21. VDDA and GNDA must satisfy [(VDDA) – (GNDA)] + 4.0V. Applies to all pins, including continuous overvoltage conditions at the analog input pins. Transient current of up to 100mA will not cause SCR latch-up. Applies to all pins, except VREF±. Total power dissipation, including all input currents and output currents. Applies to all pins. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. 16 DS981F2 PMF 4th Order ∆Σ Modulator x10 DELAY CTRL SINC3 IIR X + X + V1DCOFF PC ... CPCC1[1:0] ... FPCC1[8:0] ... V1GAIN SYSGAIN Config 2 I1 DCOFF IIN1± 4th Order ∆Σ Modulator PGA V1 HPF DELAY CTRL SINC3 IIR X + ... V1FLT[1:0] I1FLT[1:0] Phase Shift X Epsilon X ... X Q1 2 X I1 GAIN P1 + HPF X INT MUX VIN1± MUX CS5484 PMF I1 Registers Figure 9. Signal Flow for V1, I1, P1, and Q1 Measurements 4. SIGNAL FLOW DESCRIPTION The signal flow consists of two current channels and two voltage channels. The current and voltage channels have differential input pins. 4.1 Analog-to-Digital Converters All four input channels use fourth-order delta-sigma modulators to convert the analog inputs to single-bit digital data streams. The converters sample at a rate of MCLK/8. This high sampling provides a wide dynamic range and simplifies anti-alias filter design. 4.2 Decimation Filters The single-bit modulator output data is widened to 24 bits and down sampled to MCLK/1024 with low-pass decimation filters. These decimation filters are 4th Order ∆Σ Modulator x10 ... CPCC2[1:0] SINC3 X IIR + PGA 4th Order ∆Σ Modulator 4.4 Phase Compensation Phase compensation changes the phase of voltage relative to current by adding a delay in the decimation filters. The amount of phase shift is set by the PC register bits CPCCx[1:0] and FPCCx[8:0] for current channels. Bits CPCCx[1:0] set the delay for the voltage channels. X V2 HPF + ... FPCC2[8:0] ... V2GAIN SYSGAIN Config 2 I2 DCOFF IIN2± The IIR filters are used to compensate for the amplitude roll-off of the decimation filters. The droop-correction filter flattens the magnitude response of the channel out to the Nyquist frequency, thus allowing for accurate measurements of up to 2 kHz (MCLK = 4.096 MHz). By default, the IIR filters are enabled. The IIR filters can be bypassed by setting the IIR_OFF bit in the Config2 register. PMF DELAY CTRL V2DCOFF PC 4.3 IIR Filters DELAY CTRL SINC3 X IIR + ... V2FLT[1:0] I2FLT[1:0] Phase Shift X Epsilon X ... X Q2 2 X I2 GAIN P2 + X HPF INT PMF MUX VIN2± third-order Sinc filters. The filter outputs pass through an IIR "anti-sinc" filter. MUX The signal flow for voltage measurement, current measurement, and the other calculations is shown in Figures 9, 10, and 11. I2 Registers Figure 10. Signal Flow for V2, I2, P2, and Q2 Measurements DS981F2 17 CS5484 Fine phase compensation control bits, FPCCx[8:0], provide up to 1/OWR delay in the current channel. Coarse phase compensation control bits, CPCCx[1:0], provide an additional 1/OWR delay in the current channels or up to 2/OWR delay in the voltage channel. Negative delay in the voltage channel can be implemented by setting longer delay in the current channel than the voltage channel. For a OWR of 4000Hz, the delay range is ±500µs, a phase shift of ±8.99° at 50Hz and ±10.79° at 60 Hz. The step size is 0.008789° at 50 Hz and 0.010547° at 60Hz. 4.5 DC Offset and Gain Correction The system and CS5484 inherently have component tolerances, gain, and offset errors, which can be removed using the gain and offset registers. Each measurement channel has its own set of gain and offset registers. For every instantaneous voltage and current sample, the offset and gain values are used to correct DC offset and gain errors in the channel (see section 7. System Calibration on page 62 for more details). 4.6 High-pass and Phase Matching Filters Optional high-pass filters (HPF in Figures 9 and 10) remove any DC component from the selected signal paths. Each power calculation contains a current and voltage channel. If an HPF is enabled in only one channel, a phase-matching filter (PMF) should be applied to the other channel to match the phase response of the HPF. For AC power measurement, high-pass filters should be enabled on the voltage and current channels. For information about how to enable and disable the HPF or PMF on each channel, refer to section 6.6.3 Configuration 2 (Config2) – Page 16, Address 0 on page 38. N V1(V2) ÷N 4.7 Digital Integrators Optional digital integrators (INT in Figures 9 and 10) are implemented on both current channels (I1, I2) to compensate for the 90º phase shift and 20dB/decade gain generated by the Rogowski coil current sensor. When a Rogowski coil is used as the current sensor, the integrator (INT) should be enabled on that current channel. For information about how to enable and disable the INT on each current channel, refer to section 6.6.3 Configuration 2 (Config2) – Page 16, Address 0 on page 38. 4.8 Low-rate Calculations All the RMS and power results come from low-rate calculations by averaging the output word rate (OWR) instantaneous values over N samples, where N is the value stored in the SampleCount register. The low-rate interval or averaging period is N divided by OWR (4000Hz if MCLK = 4.096MHz). The CS5484 provides two averaging modes for low-rate calculations: Fixed Number of Samples Averaging mode and Line-cycle Synchronized Averaging mode. By default, the CS5484 averages with the Fixed Number of Samples Averaging mode. By setting the AVG_MODE bit in the Config2 register, the CS5484 will use the Line-cycle Synchronized Averaging mode. 4.8.1 Fixed Number of Samples Averaging N is the preset value in the SampleCount register and should not be set less than 100. By default, the SampleCount is 4000. With MCLK = 4.096MHz, the averaging period is fixed at N/4000 = 1 second, regardless of the line frequency. V1RMS (V2RMS) Config 2 ... APCM ... I1 ACOFF (I2ACOFF ) ÷N + - I1RMS (I2RMS) MUX N I1 (I2) Q1 OFF (Q2OFF ) N Q1 (Q2) ÷N + + Q1AVG (Q2AVG) X P1OFF (P2OFF ) N P1 (P2) S1 (S2) ÷N + + Inverse P1AVG (P2AVG) X Registers + + X PF1 (PF2) Figure 11. Low-rate Calculations 18 DS981F2 CS5484 4.8.2 Line-cycle Synchronized Averaging 4.8.5 Reactive Power When operating in Line-cycle Synchronized Averaging mode, and when line frequency measurement is enabled (see section 5.4 Line Frequency Measurement on page 22), the CS5484 uses the voltage (V) channel zero crossings and measured line frequency to automatically adjust N such that the averaging period will be equal to the number of half line-cycles in the CycleCount register. For example, if the line frequency is 51Hz, and the CycleCount register is set to 100, N will be 4000 (100/2)/51 = 3921 during continuous conversion. N is self-adjusted according to the line frequency, therefore the averaging period is always close to the whole number of half line-cycles, and the low-rate calculation results will minimize ripple and maximize resolution, especially when the line frequency varies. Before starting a low-rate conversion in the Line-cycle Synchronized Averaging mode, the SampleCount register should not be changed from its default value of 4000, and bit AFC of the Config2 register must be set. During continuous conversion, the host processor should not change the SampleCount register. Instantaneous reactive power (Q1, Q2) are sample rate results obtained by multiplying instantaneous current (I1, I2) by instantaneous quadrature voltage (V1Q, V2Q), which are created by phase shifting instantaneous voltage (V1, V2) 90 degrees using first-order integrators (see Figures 9 and 10). The gain of these integrators is inversely related to line frequency, so their gain is corrected by the Epsilon register, which is based on line frequency. Reactive power (Q1AVG, Q2AVG) is generated by integrating the instantaneous quadrature power over N samples. 4.8.3 RMS Current and Voltage The root mean square (RMS in Figure 11) calculations are performed on N instantaneous current and voltage samples using Equation 1: N–1 RMS = I2 n n=0 -------------------N V2 n By default, the CS5484 calculates the apparent power (S1, S2) as the product of RMS voltage and current, as shown in Equation 2: S = V RMS I RMS [Eq: 1] n=0 ---------------------N 4.8.4 Active Power The instantaneous voltage and current samples are multiplied to obtain the instantaneous power (P1, P2) (see Figures 9 and 10). The product is then averaged over N samples to compute active power (P1AVG, P2AVG). The CS5484 also provides an alternate apparent power calculation method. The alternate apparent power method uses real power (P1AVG, P2AVG) and reactive power (Q1AVG, Q2AVG) to calculate apparent power. See Equation 3: S = Q AVG 2 + P AVG 2 [Eq: 3] 4.8.7 Peak Voltage and Current Peak current (I1PEAK, I2PEAK) and peak voltage (V1PEAK, V2PEAK) are calculated over N samples and recorded in the corresponding channel peak register documented in the register map. This peak value is updated every N samples. 4.8.8 Power Factor Power factor (PF1, PF2) is active power divided by apparent power. The sign of the power factor is determined by the active power. See Equation 4: P ACTIVE PF = ---------------------S DS981F2 [Eq: 2] The APCM bit in the Config2 register controls which method is used for apparent power calculation. N–1 V RMS = 4.8.6 Apparent Power [Eq: 4] 19 CS5484 4.9 Average Active Power Offset 4.10 Average Reactive Power Offset The average active power offset registers, P1OFF (P2OFF), can be used to offset erroneous power sources resident in the system not originating from the power line. Residual power offsets are usually caused by crosstalk into current channels from voltage channels, or from ripple on the meter’s or chip’s power supply, or from inductance from a nearby transformer. The average reactive power offset registers, Q1OFF (Q2OFF), can be used to offset erroneous power sources resident in the system not originating from the power line. Residual reactive power offsets are usually caused by crosstalk into current channels from voltage channels, or from ripple on the meter’s or chip’s power supply, or from inductance from a nearby transformer. These offsets can be either positive or negative, indicating crosstalk coupling either in phase or out of phase with the applied voltage input. The power offset registers can compensate for either condition. These offsets can be either positive or negative, depending on the phase angle between the crosstalk coupling and the applied voltage. The reactive power offset registers can compensate for either condition. To use this feature, measure the average reactive power at no load. Take the measured result from the Q1AVG (Q2AVG) register, invert (negate) the value and write it to the associated reactive power offset register, Q1OFF (Q2OFF). To use this feature, measure the average power at no load. Take the measured result (from the P1AVG (P2AVG) register), invert (negate) the value, and write it to the associated average active power offset register, P1OFF (P2OFF). 20 DS981F2 CS5484 5. FUNCTIONAL DESCRIPTION 5.1 Power-on Reset Table 1. POR Thresholds The CS5484 has an internal power supply supervisor circuit that monitors the VDDA and VDDD power supplies and provides the master reset to the chip. If any of these voltages are in the reset range, the master reset is triggered. The CS5484 has dedicated power-on reset (POR) circuits for the analog supply and digital supply. During power-up, both supplies have to be above the rising threshold for the master reset to be de-asserted. Each POR is divided into two blocks: rough and fine. Rough POR triggers the fine POR. Rough POR depends only on the supply voltage. The trip point for the fine POR is dependent on bandgap voltage for precise control. The POR circuit also acts as a brownout detect. The fine POR detects supply drops and asserts the master reset. The rough and fine PORs have hysteresis in their rise and fall thresholds, which prevents the reset signal from chattering. Figure 12 shows the POR outputs for each of the power supplies. The POR_Fine_VDDA and POR_Fine_VDDD signals are AND-ed to form the actual power-on reset signal to the digital circuity. The digital circuitry, in turn, holds the master reset signal for 130ms and then de-asserts the master reset. VDDA V th5 V th2 Vth1 V th6 POR_Rough_VDDA POR_Fine_VDDA Vth4 VDDD Vth7 Vth8 Vth3 POR_Rough_VDDD Typical POR Threshold VDDA VDDD Rising Falling Rough Vth1 = 2.34V Vth6 = 2.06V Fine Vth2 = 2.77V Vth5 = 2.59V Rough Vth3 = 1.20V Vth8 = 1.06V Fine Vth4 = 1.51V Vth7 = 1.42V 5.2 Power Saving Modes Power Saving modes for the CS5484 are accessed through the Host Commands (see section 6.1 Host Commands on page 27). • Standby: Powers down all the ADCs, rough buffer, and the temperature sensor. Standby mode disables the system time calculations. Use the wake-up command to come out of standby mode. • Wake-up: Clears the ADC power-down bits and starts the system time calculations. After any of these commands are completed, the DRDY bit is set in the Status0 register. 5.3 Zero-crossing Detection Zero-crossing detection logic is implemented in the CS5484. One current and one voltage channel can be selected for zero-crossing detection. The IZX_CH and VZX_CH control bits in the Config0 register are used to select the zero-crossing channel. A low-pass filter can be enabled by setting the ZX_LPF bit in register Config2. The low-pass filter has a cut-off frequency of 80Hz. It is used to eliminate any harmonics and help the zero-crossing detection on the 50Hz or 60Hz fundamental component. The zero-crossing level registers are used to set the minimum threshold over which the channel peak must exceed in order for the zero-crossing detection logic to function. There are two separate zero-crossing level registers: VZXLEVEL is the threshold for the voltage channels, and IZXLEVEL is the threshold for the current channels. POR_Fine_VDDD POR_Fine_VDDA POR_Fine_VDDD Master Reset 130ms Figure 12. Power-on Reset Timing DS981F2 21 CS5484 V(t), I(t) If |VPEAK| > VZXLEVEL, then voltage zero-crossing detection is enabled. If |IPEAK| > IZXLEVEL, then current zero-crossing detection is enabled. If |VPEAK| VZXLEVEL, then voltage zero-crossing detection is disabled. If |IPEAK| IZXLEVEL, then current zero-crossing detection is disabled. VZXLEVEL IZXLEVEL t DOx Zero-crossing output on DOx pin Pulse width = 250μs t Figure 13. Zero-crossing Level and Zero-crossing Output on DOx 5.4 Line Frequency Measurement If the Automatic Frequency Calculation (AFC) bit in the Config2 register is set, the line frequency measurement on the voltage channel will be enabled. The line frequency measurement is based on a number of voltage channel zero crossings. This number is 100 by default and configurable through the ZXNUM register (see section 6.6.76 on page 61). The Epsilon register will be updated automatically with the line frequency information. The Frequency Update (FUP) bit in the Status0 interrupt status register is set when the frequency calculation is completed. When the line frequency is 50Hz and the ZXNUM register is 100, the Epsilon register is updated every one second with a resolution of less than 0.1%. A larger zero-crossing number in the ZXNUM register will increase line frequency measurement resolution and the period. Note that the CS5484 line frequency measurement function does not support the line frequency out of the range of 40Hz to 75Hz. 22 The Epsilon register is also used to set the gain of the 90° phase shift filter used in the quadrature power calculation. The value in the Epsilon register is the ratio of the line frequency to the output word rate (OWR). For 50Hz line frequency and 4000Hz OWR, Epsilon is 50/4000 (0.0125) (the default). For 60Hz line frequency, it is 60/4000 (0.015). 5.5 Energy Pulse Generation The CS5484 provides four independent energy pulse generation blocks (EPG1, EPG2, EPG3, and EPG4) in order to simultaneously output active, reactive, and apparent energy pulses on any of the four digital output pins (DO1, DO2, DO3, and DO4). The energy pulse frequency is proportional to the magnitude of the power. The energy pulse output is commonly used as the test output of a power meter. The host microcontroller can also use the energy pulses to easily accumulate the energy. Refer to Figure 14. DS981F2 CS5484 EPGx_ON (Config1) MCLK 0001 0001 P SUM 0010 Q SUM 0101 S1 AVG 0110 S2 AVG 0111 S SUM 1000 PULSE RATE P1 Sign 0100 P2 Sign 0101 P SUM Sign 0110 Q1 Sign 0111 Q2 Sign 1000 QSUM Sign 1001 RESERVED 1010 V1/V2 Crossing 1011 I1/I2 Crossing 1100 RESERVED 1101 Hi-Z Interrupt (PulseCtrl) EPGxIN[3:0] 4 (PulseWidth) FREQ_RNG[3:0] 4 (PulseWidth) PW[7:0] 8 1110 DO2_OD (Config1) DO2 Digital Output Mux (DO4) 0100 0011 Digital Output Mux (DO3) Q2AVG DO1 0010 Digital Output Mux (DO2) 0011 DO1_OD (Config1) Digital Output Mux (DO1) Q1AVG Energy Pulse Generation (EPG4) P2 AVG Energy Pulse Generation (EPG3) 0000 Energy Pulse Generation (EPG2) 0000 Energy Pulse Generation (EPG1) P1 AVG DO3_OD (Config1) DO3 DO4_OD (Config1) DO4 1111 DOxMODE[3:0] 4 (Config1) Figure 14. Energy Pulse Generation and Digital Output Control 4. Write ‘1’ to bit EPGx_ON of register Config1 (page 0, After reset, all four energy pulse generation blocks are address 1) to enable the desired energy pulse disabled (DOxMODE[3:0] = Hi-Z). To output a desired generation blocks. energy pulse to a DOx pin, it is necessary to follow the steps below: 5. Wait at least 0.1 seconds. 1. Write to register PulseWidth (page 0, address 8) to 6. Write bits DOxMODE[3:0] of register Config1 to select the energy pulse width and pulse frequency select DOx to output pulses from the appropriate range. energy pulse generation block. 2. Write to register PulseRate (page 18, address 28) to 7. Send DSP instruction (0xD5) to begin continuous select the energy pulse rate. conversion. 3. Write to register PulseCtrl (page 0, address 9) to select the input to each energy pulse generation block. DS981F2 23 CS5484 5.5.1 Pulse Rate Before configuring the PulseRate register, the full-scale pulse rate needs to be calculated and the frequency range needs to be specified through FREQ_RNG[3:0] bits in the PulseWidth register. Refer to section 6.6.6 Pulse Output Width (PulseWidth) – Page 0, Address 8 on page 41. The FREQ_RNG[3:0] bits should be set to b[0110]. For example, if a meter has the meter constant of 1000imp/kWh, a maximum voltage (UMAX) of 240 V, and a maximum current (IMAX) of 100A, the maximum pulse rate is: [1000x(240x100/1000)]/3600 = 6.6667Hz. Assume the meter is calibrated with UMAX and IMAX, and the Scale register contains the default value of 0.6. After gain calibration, the power register value will be 0.36, which represents 240x100 = 24kW or 6.6667Hz pulse output rate. The full-scale pulse rate is: Fout = 6.6667/0.36 = 18.5185Hz. The CS5484 pulse generation block behaves as follows: • The pulse rate generated by full-scale (1.0decimal) power register is: FOUT = (PulseRatex2000)/2FREQ_RNG • The PulseRate register value is: PulseRate = (FOUT x2FREQ_RNG)/2000 5.6 Voltage Sag, Voltage Swell, and Overcurrent Detection Voltage sag detection is used to determine when the voltage falls below a predetermined level for a specified interval of time (duration). Voltage swell and overcurrent detection determine when the voltage or current rises above a predetermined level for the duration. The duration is set by the value in the V1SagDUR (V2SagDUR), V1SwellDUR (V2SwellDUR), and I1OverDUR (I2OverDUR) registers. Setting any of these to zero (default) disables the detect feature for the given channel. The value is in output word rate (OWR) samples. The predetermined level is set by the values in the V1SagLEVEL (V2SagLEVEL), V1SwellDUR (V2SwellDUR), and I1OverLEVEL (I2OverLEVEL) registers. For each enabled input channel, the measured value is rectified and compared to the associated level register. Over the duration window, the number of samples above and below the level are counted. If the number of samples below the level exceeds the number of samples above, a Status0 register bit V1SAG (V2SAG) is set, indicating a sag condition. If the number of samples above the level exceeds the number of samples below, a Status0 register bit V1SWELL (V2SWELL) or I1OVER (I2OVER) is set, indicating a swell or overcurrent condition (see Figure 15). = (18.5186x64)/2000 = 0.5925952 = 0x4BDA29 5.5.2 Pulse Width The PulseWidth register defines the Active-low time of each energy pulse: Active-low = 250µs+(PulseWidth/64000). By default, the PulseWidth register value is 1, and the Active-low time of each energy pulse is 265.6µs. Note that the pulse width should never exceed the pulse period. L e ve l D u ra tio n Figure 15. Sag, Swell, and Overcurrent Detect 24 DS981F2 CS5484 5.7 Phase Sequence Detection Polyphase meters using multiple CS5484 devices may be configured to sense the succession of voltage zero-crossings and determine which phase order is in service. The phase sequence detection within CS5484 involves counting the number of OWR samples from a starting point to the next voltage zero-crossing rising edge or falling for each phase. By comparing the count for each phase, the phase sequence can be easily determined: the smallest count is first, and the largest count is last. The phase sequence detection and control (PSDC) register provides the count control, zero-crossing direction and count results. Writing '0' to bit DONE and '10110' to bits CODE[4:0] of the PSDC register followed by a falling edge on the RX pin will initiate the phase sequence detection circuit. The RX pin must be held low for a minimum of 500ns. When the device is in UART mode, it is recommended that a 0xFF command be written to all parts to start the phase sequence detection. This command is ignored by the UART interface and a checksum is not needed. Multiple CS5484 devices in a polyphase meter must receive the register writing and the RX falling edge at the same time so that all CS5484 devices start to count simultaneously. Bit DIR of the PSDC register specifies the direction of the next zero-crossing at which the count stops. If bit DIR is '0', the count stops at the next negative-to-positive zero crossing. If bit DIR is '1', the count stops at the next positive-to-negative zero-crossing. When the count stops, the DONE bit will be set by the CS5484, and then the count result of each phase may be read from bits PSCNT[6:0] of the PSDC register. Write 0x16 to PSDC Register Start on the Falling Edge on the RX Pin 2 If the PSCNT[6:0] bits are equal to 0x00, 0x7F or greater than 0x64 (for 50Hz) or 0x50 (for 60Hz), then a measurement error has occurred, and the measurement results should be disregarded. This could happen when the voltage input signal amplitude is lower than the amplitude specified in the VZXLEVEL register. To determine the phase order, the PSCNT[6:0] bit count from each CS5484 is sorted in ascending order. Figure 16 and Figure 17 illustrate how phase sequence detection is performed. Phase sequences A, B, and C for the default rising edge transition are illustrated in Figure 16. The PSCNT[6:0] bits from the CS5484 on phase A will have the lowest count, followed by the PSCNT[6:0] bits from the CS5484 on phase B with the middle count, and the PSCNT[6:0] bits from the CS5484 on phase C with the highest count. Phase sequences C, B, and A for rising edge transition are illustrated in Figure 17. The PSCNT[6:0] bits from the CS5484 on phase C will have the lowest count, followed by the PSCNT[6:0] bits from the CS5484 on phase B with the middle count, and the PSCNT[6:0] bits from the CS5484 on phase A with the highest count. 5.8 Temperature Measurement The CS5484 has an internal temperature sensor, which is designed to measure temperature and optionally compensate for temperature drift of the voltage reference. Temperature measurements are stored in the Temperature register (T), which, by default, is configured to a range of ±128 degrees on the Celsius (°C) scale. The application program can change both the scale and range of temperature by changing the Temperature Gain (TGAIN) and Temperature Offset (TOFF) registers. Phase A Channel Stop Phase A Count 0 -2 A Phase B Channel 2 Stop Phase B Count 0 -2 C B Phase C Channel Stop 2 Phase C Count 0 -2 Figure 16. Phase Sequence A, B, C for Rising Edge Transition DS981F2 25 CS5484 Write 0x16 to PSDC Register Start on the Falling Edge on the RX Pin Phase A Channel Stop 2 Phase A Count 0 -2 C Phase B Channel Stop 2 Phase B Count 0 -2 A B Phase C Channel Stop 2 Phase C Count 0 -2 Figure 17. Phase Sequence C, B, A for Rising Edge Transition The temperature sensor and V2 input share the same delta-sigma modulator on the second voltage channel. By default, the temperature measurement is disabled, and the delta-sigma modulator is used for V2 measurement. To enable temperature measurement, set Config0 register bit 23, bit 22, and bit 13. The Temperature register (T) updates every 2240 output word rate (OWR) samples. The Status0 register bit TUP indicates when T is updated. The temperature measurement and the second voltage channel, V2, share the same delta-sigma modulator, so the V2 measurement will be using the V1 delta-sigma modulator output when temperature measurement is enabled. 5.9 Anti-creep The anti-creep (no-load threshold) is used to determine if a no-load condition is detected. The |PSum| and |QSum| are compared to the value in the No-Load Threshold register (LoadMIN). If both |PSUM| and |QSUM| are less than this threshold, then PSUM and QSUM are forced to zero. If SSUM is less than the value in LoadMIN register, then SSUM is forced to zero. 5.10 Register Protection To prevent the critical configuration and calibration registers from unintended changes, the CS5484 provides two enhanced register protection mechanisms: write protection and automatic checksum calculation. 5.10.1 Write Protection Setting the DSP_LCK[4:0] bits in the RegLock register to 0x16 enables the CS5484 DSP lockable registers to be write-protected from the calculation engine. Setting 26 the DSP_LCK[4:0] bits write-protection mode. to 0x09 disables the Setting the HOST_LCK[4:0] bits in the RegLock register to 0x16 enables the CS5484 HOST lockable registers to be write-protected from the serial interface. Setting the HOST_LCK[4:0] bits to 0x09 disables the write-protection mode. For registers that are DSP lockable, HOST lockable, or both, refer to sections 6.2 Hardware Registers Summary (Page 0) on page 29, 6.3 Software Registers Summary (Page 16) on page 31, and 6.4 Software Registers Summary (Page 17) on page 33. 5.10.2 Register Checksum All the configuration and calibration registers are protected by checksum, if enabled. Refer to 6.2 Hardware Registers Summary (Page 0) on page 29, 6.3 Software Registers Summary (Page 16) on page 31, and 6.4 Software Registers Summary (Page 17) on page 33. The checksum for all registers marked with an asterisk symbol (*) is calculated once every low-rate cycle. The checksum result is stored in the RegChk register. After the CS5484 has been fully configured and loaded with the calibrations, the host microcontroller should keep a copy of the checksum (RegChk_Copy) in its memory. In normal operation, the host microcontroller can read the RegChk register and compare it with the saved copy of the RegChk register. If the two values mismatch, a reload of configurations and calibrations into the CS5484 is necessary. The automatic checksum computation can be disabled by setting the REG_CSUM_OFF bit in the Config2 register. DS981F2 CS5484 6. HOST COMMANDS AND REGISTERS 6.1.1.2 Register Read 6.1 Host Commands A register read is designated by setting the two MSBs of the command to binary ‘00’. The lower 6 bits of the register read command are the lower 6 bits of the 12-bit register address. After the register read command has been received, the CS5484 will send 3 bytes of register data onto the SDO/TX pin. The first byte sent to the CS5484 SDI/RX pin contains the host command. Four types of host commands are required to read and write registers and instruct the calculation engine. The two most significant bits (MSBs) of the host command defines the function to be performed. The following table depicts the types of commands. Table 2. Command Format Function Binary Value Note Register Read 0 0 A5 A4 A3 A2 A1 A0 Register Write 0 1 A5 A4 A3 A2 A1 A0 Page Select 1 0 P5 P4 P3 P2 P1 P0 P[5:0] specifies the page. Instruction 1 1 C5 C4 C3 C2 C1 C0 C[5:0] specifies the instruction. A[5:0] specifies the register address. 6.1.1 Memory Access Commands The CS5484 memory has 12-bit addresses and is organized as P5 P4 P3 P2 P1 P0 A5 A4 A3 A2 A1 A0 in 64 pages of 64 addresses each. The higher 6 bits specify the page number. The lower 6 bits specify the address within the selected page. 6.1.1.1 Page Select A page select command is designated by setting the two MSBs of the command to binary ‘10’. The page select command provides the CS5484 with the page number of the register to access. Register read and write commands access 1 of 64 registers within a specified page. Subsequent register reads and writes can be performed once the page has been selected. SDI/RX Page Select Cmd. Figure 18. Byte Sequence for Page Select DS981F2 SDI/RX Read Cmd. SDO/TX DATA DATA DATA Figure 19. Byte Sequence for Register Read 6.1.1.3 Register Write A register write command is designated by setting the two MSBs of the command to binary ‘01’. The lower 6 bits of the register write command are the lower 6 bits of the 12-bit register address. A register write command must be followed by 3 bytes of data. SDI/RX Write Cmd. DATA DATA DATA Figure 20. Byte Sequence for Register Write 6.1.2 Instructions An instruction command is designated by setting the two MSBs of the command to binary '11'. An Instruction command will interrupt any process currently running and initiate a new process in the CS5484. SDI/RX Instruction Figure 21. Byte Sequence for Instructions These new processes include calibration, power control, and soft reset. The following table depicts the types of instructions. These new processes include calibration, power control, and soft reset. The following table depicts the types of instructions. Note that when the CS5484 is in continuous conversion mode, an unexpected or invalid instruction command could cause the device to stop continuous conversion and enter an unexpected operation mode. The host processor should keep monitoring the CS5484 operation status and react accordingly. 27 CS5484 Table 3. Instruction Format Function Controls Binary Value 0 C4 C3 C2 C1 C0 0 00001 - Software Reset 0 00010 - Standby 0 00011 - Wakeup 0 10100 - Single Conv. 0 10101 - Continuous Conv. 0 11000 - Halt Conv. 1 C4 C3 C2 C1 C0 1 00 1 10 1 11 Calibrations C2C1C0 C2C1C0 C2C1C0 DC Offset AC Offset* Gain Note C[5] specifies the instruction type: 0 = Controls 1 = Calibrations For calibrations, C[4:3] specifies the type of calibration. *AC Offset calibration valid only for current channel 1 C4 C3 C2 C1 C0 The checksum is calculated by subtracting each transmit byte from 0xFF. Any overflow is truncated and the result wraps. The CS5484 executes the command only if the checksum transmitted by the host matches the checksum calculated locally. Otherwise, it sets a status bit (RX_CSUM_ERR in the Status0 register), ignores the command, and clears the serial interface in preparation for the next transmission. SDI/RX Page Select Cmd. Checksum Page Select SDI/RX Instruction Checksum Instruction SDI/RX Read Cmd. CHECKSUM SDO/TX 1 C4C3 1 C4C3 1 C4C3 1 C4C3 1 C4C3 001 010 011 100 110 I1 V1 I2 V2 All Four For calibrations, C[2:0] specifies the channel(s). DATA DATA DATA CHECKSUM Read Command SDI/RX Write Cmd. DATA DATA DATA CHECKSUM Write Command Figure 22. Byte Sequence for Checksum 6.1.3 Checksum 6.1.4 Serial Time Out To improve the communication reliability on the serial interface, the CS5484 provides a checksum mechanism on transmitted and received signals. Checksum is disabled by default but can be enabled by setting the appropriate bit in the SerialCtrl register. When enabled, both host and CS5484 are expected to send one additional checksum byte after the normal command byte and applicable 3-byte register data has been transmitted. In case a transaction from the host is not completed (for example, a data byte is missing in a register write), a time out circuit will reset the interface after 128ms. This will require that each byte be sent from the host within 128ms of the previous byte. 28 DS981F2 CS5484 6.2 Hardware Registers Summary (Page 0) Address2 0* 1* 2 3* 4 5* 6 7* 8* 9* 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34* 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 DS981F2 RA[5:0] 00 0000 00 0001 00 0010 00 0011 00 0100 00 0101 00 0110 00 0111 00 1000 00 1001 00 1010 00 1011 00 1100 00 1101 00 1110 00 1111 01 0000 01 0001 01 0010 01 0011 01 0100 01 0101 01 0110 01 0111 01 1000 01 1001 01 1010 01 1011 01 1100 01 1101 01 1110 01 1111 10 0000 10 0001 10 0010 10 0011 10 0100 10 0101 10 0110 10 0111 10 1000 10 1001 10 1010 10 1011 10 1100 10 1101 10 1110 10 1111 11 0000 11 0001 11 0010 11 0011 11 0100 Name Config0 Config1 Reserved Mask PC SerialCtrl PulseWidth PulseCtrl Status0 Status1 Status2 RegLock V1PEAK I1PEAK V2PEAK I2PEAK PSDC - Description1 Configuration 0 Configuration 1 DSP3 Y Y Interrupt Mask Reserved Phase Compensation Control Reserved UART Control Energy Pulse Width Energy Pulse Control Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Interrupt Status Chip Status 1 Chip Status 2 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Register Lock Control Reserved V1 Peak Voltage I1 Peak Current V2 Peak Voltage I2 Peak Current Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Phase Sequence Detection & Control Reserved Reserved Reserved Reserved Y HOST 3 Y Y Y Y Y Y Y Y Y Y Y N N N N N N N N N N N N Y Y Y Y N Y Default 0x 40 0000 0x 00 EEEE 0x 00 0000 0x 00 0000 0x 02 004D 0x 00 0001 0x 00 0000 0x 80 0000 0x 80 1800 0x 00 0000 0x 00 0000 0x 00 0000 0x 00 0000 0x 00 0000 0x 00 0000 0x 00 0000 29 CS5484 53 54 55 56 57 58 59 60 61 62 63 Notes: 30 11 0101 11 0110 11 0111 11 1000 11 1001 11 1010 11 1011 11 1100 11 1101 11 1110 11 1111 ZXNUM - Reserved Reserved Num. Zero Crosses used for Line Freq. Y Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Y 0x00 0064 - (1) Warning: Do not write to unpublished or reserved register locations. (2) * Registers with checksum protection. (3) Registers that can be set to write protect from DSP and/or HOST. DS981F2 CS5484 6.3 Software Registers Summary (Page 16) Address2 0* 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32* 33* 34* 35* 36* 37* 38* 39* 40* 41* 42* 43* 44* 45* 46 47 48 49 50* 51* 52 DS981F2 RA[5:0] 00 0000 00 0001 00 0010 00 0011 00 0100 00 0101 00 0110 00 0111 00 1000 00 1001 00 1010 00 1011 00 1100 00 1101 00 1110 00 1111 01 0000 01 0001 01 0010 01 0011 01 0100 01 0101 01 0110 01 0111 01 1000 01 1001 01 1010 01 1011 01 1100 01 1101 01 1110 01 1111 10 0000 10 0001 10 0010 10 0011 10 0100 10 0101 10 0110 10 0111 10 1000 10 1001 10 1010 10 1011 10 1100 10 1101 10 1110 10 1111 11 0000 11 0001 11 0010 11 0011 11 0100 Name Config2 RegChk I1 V1 P1 P1AVG I1RMS V1RMS I2 V2 P2 P2AVG I2RMS V2RMS Q1AVG Q1 Q2AVG Q2 S1 PF1 S2 PF2 T PSUM SSUM QSUM I1DCOFF I1GAIN V1DCOFF V1GAIN P1OFF I1ACOFF Q1OFF I2DCOFF I2GAIN V2DCOFF V2GAIN P2OFF I2ACOFF Q2OFF Epsilon SampleCount - Description1 Configuration 2 Register Checksum I1 Instantaneous Current V1 Instantaneous Voltage Instantaneous Power 1 Active Power 1 I1 RMS Current V1 RMS Voltage I2 Instantaneous Current V2 Instantaneous Voltage Instantaneous Power 2 Active Power 2 I2 RMS Current V2 RMS Voltage Reactive Power 1 Instantaneous Reactive Power 1 Reactive Power 2 Instantaneous Reactive Power 2 Reserved Reserved Apparent Power 1 Power Factor 1 Reserved Reserved Apparent Power 2 Power Factor 2 Reserved Temperature Reserved Total Active Power Total Apparent Power Total Reactive Power I1 DC Offset I1 Gain V1 DC Offset V1 Gain Average Active Power 1 Offset I1 AC Offset Average Reactive Power 1 Offset I2 DC Offset I2 Gain V2 DC Offset V2 Gain Average Active Power 2 Offset I2 AC Offset Average Reactive Power 2 Offset Reserved Reserved Reserved Ratio of Line to Sample Frequency Reserved Sample Count Reserved DSP3 Y N N N N N N N N N N N N N N N N N HOST 3 Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y N N Y Y N N Y Y N Y N N N Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y N Y N Y Default 0x 06 0200 0x 00 0000 0x 00 0000 0x 00 0000 0x 00 0000 0x 00 0000 0x 00 0000 0x 00 0000 0x 00 0000 0x 00 0000 0x 00 0000 0x 00 0000 0x 00 0000 0x 00 0000 0x 00 0000 0x 00 0000 0x 00 0000 0x 00 0000 0x 00 0000 0x 00 0000 0x 00 0000 0x 00 0000 0x 00 0000 0x 00 0000 0x 00 0000 0x 00 0000 0x 00 0000 0x 40 0000 0x 00 0000 0x 40 0000 0x 00 0000 0x 00 0000 0x 00 0000 0x 00 0000 0x 40 0000 0x 00 0000 0x 40 0000 0x 00 0000 0x 00 0000 0x 00 0000 0x 01 999A 0x 00 0FA0 31 CS5484 53 54* 55* 56* 57 58* 59* 60* 61 62 63 Notes: 32 11 0101 11 0110 11 0111 11 1000 11 1001 11 1010 11 1011 11 1100 11 1101 11 1110 11 1111 TGAIN TOFF TSETTLE LoadMIN SYSGAIN Time - Reserved Temperature Gain Temperature Offset Reserved Filter Settling Time to Conv. Startup No-Load Threshold Reserved System Gain System Time (in samples) Reserved Reserved Y Y Y Y Y Y Y Y N N Y Y 0x 06 B716 0x D5 3998 0x 00 001E 0x 00 0000 0x 50 0000 0x 00 0000 - (1) Warning: Do not write to unpublished or reserved register locations. (2) * Registers with checksum protection. (3) Registers that can be set to write protect from DSP and/or HOST. DS981F2 CS5484 6.4 Software Registers Summary (Page 17) Address2 0* 1* 2 3 4* 5* 6 7 8* 9* 10 11 12* 13* 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Notes: DS981F2 RA[5:0] 00 0000 00 0001 00 0010 00 0011 00 0100 00 0101 00 0110 00 0111 00 1000 00 1001 00 1010 00 1011 00 1100 00 1101 00 1110 00 1111 01 0000 01 0001 01 0010 01 0011 01 0100 01 0101 01 0110 01 0111 01 1000 01 1001 01 1010 01 1011 01 1100 01 1101 01 1110 01 1111 Name V1SagDUR V1SagLevel I1OverDUR I1OverLEVEL V2SagDUR V2SagLevel I2OverDUR I2OverLEVEL - Description1 V1 Sag Duration V1 Sag Level Reserved Reserved I1 Overcurrent Duration I1 Overcurrent Level Reserved Reserved V2 Sag Duration V2 Sag Level Reserved Reserved I2 Overcurrent Duration I2 Overcurrent Level Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved DSP3 Y Y Y Y Y Y Y Y HOST 3 Default Y 0x 00 0000 Y 0x 00 0000 Y 0x 00 0000 Y 0x 7F FFFF Y 0x 00 0000 Y 0x 00 0000 Y 0x 00 0000 Y 0x 7F FFFF - (1) Warning: Do not write to unpublished or reserved register locations. (2) * Registers with checksum protection. (3) Registers that can be set to write protect from DSP and/or HOST. 33 CS5484 6.5 Software Registers Summary (Page 18) Address2 24* 25 26 27 28* 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43* 44 45 46* 47* 48 49 50* 51* 52 53 54 55 56 57 58* 59 60 61 62* 63* Notes: 34 RA[5:0] 01 1000 01 1001 01 1010 01 1011 01 1100 01 1101 01 1110 01 1111 10 0000 10 0001 10 0010 10 0011 10 0100 10 0101 10 0110 10 0111 10 1000 10 1001 10 1010 10 1011 10 1100 10 1101 10 1110 10 1111 11 0000 11 0001 11 0010 11 0011 11 0100 11 0101 11 0110 11 0111 11 1000 11 1001 11 1010 11 1011 11 1100 11 1101 11 1110 11 1111 Name IZX LEVEL PulseRate INTGAIN V1SwellDUR V1SwellLEVEL V2SwellDUR V2SwellLEVEL VZX LEVEL CycleCount Scale Description1 Zero-Cross Threshold for I-Channel Reserved Reserved Reserved Energy Pulse Rate Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Rogowski Coil Integrator Gain Reserved Reserved V1 Swell Duration V1 Swell Level Reserved Reserved V2 Swell Duration V2 Swell Level Reserved Reserved Reserved Reserved Reserved Reserved Zero-Cross Threshold for V-Channel Reserved Reserved Reserved Line Cycle Count I-Channel Gain Calibration Scale Value DSP3 Y Y Y Y Y Y Y Y N Y HOST 3 Default Y 0x 10 0000 Y 0x 80 0000 Y 0x14 3958 Y 0x 00 0000 Y 0x 7F FFFF Y 0x 00 0000 Y 0x 7F FFFF Y 0x 10 0000 Y 0x 00 0064 Y 0x 4C CCCC (1) Warning: Do not write to unpublished or reserved register locations. (2) * Registers with checksum protection. (3) Registers that can be set to write protect from DSP and/or HOST. DS981F2 CS5484 6.6 Register Descriptions 1. 2. 3. 4. “Default” = bit states after power-on or reset DO NOT write a “1” to any unpublished register bit or to a bit published as “0”. DO NOT write a “0” to any bit published as “1”. DO NOT write to any unpublished register address. 6.6.1 Configuration 0 (Config0) – Page 0, Address 0 23 TSEL 22 1 21 iCPUCLK 20 CPUCLK_ON 19 - 18 - 17 - 16 - 15 - 14 V2CAP[1] 13 V2CAP[0] 12 0 11 0 10 - 9 - 8 INT_POL 7 I2PGA[1] 6 I2PGA[0] 5 I1PGA[1] 4 I1PGA[0] 3 - 2 NO_OSC 1 IZX_CH 0 VZX_CH Default = 0x40 0000 TSEL Selects between Voltage Channel2 and Temperature. 0 = Selects Voltage Channel 2 (Default) 1 = Selects Temperature Sensor [22] Reserved. iCPUCLK CPU clock inversion control. 0 = CPU clock is same as MCLK (Default) 1 = Invert CPU clock to pin (CPU clock is inversion of MCLK) CUCLK_ON Enable CPUCLK to pad. 0 = Disable CPUCLK to pin (Default) 1 = Enable CPUCLK to pin [19:15] Reserved. V2CAP[1:0] Select the internal sampling capacitor size for V2 channel. Must be set to 00 for voltage measurement. 00 = V2 used for voltage measurement (Default) 01 = V2 used for temperature measurement 10 = Reserved 11 = Reserved [12:9] Reserved. INT_POL Interrupt Polarity. 0 = Active low (Default) 1 = Active high I2PGA[1:0] Select PGA gain for I2 channel. 00 = 10x gain (Default) 10 = 50x gain I1PGA[1:0] Select PGA gain for I1 channel. 00 = 10x gain (Default) 10 = 50x gain [3] Reserved. DS981F2 35 CS5484 NO_OSC Disable crystal oscillator (making XIN a logic-level input). 0 = Crystal oscillator enabled (Default) 1 = Crystal oscillator disabled IZX_CH Select current channel for zero-cross detect. 0 = Selects current channel 1 for zero-cross detect (Default) 1 = Selects current channel 2 for zero-cross detect VZX_CH Selects voltage channel for zero-cross detect. 0 = Selects voltage channel 1 for zero-cross detect (Default) 1 = Selects voltage channel 2 for zero-cross detect 6.6.2 Configuration 1 (Config1) – Page 0, Address 1 23 EPG4_ON 22 EPG3_ON 21 EPG2_ON 20 EPG1_ON 19 DO4_OD 18 DO3_OD 17 DO2_OD 16 DO1_OD 15 14 13 12 11 10 9 8 DO4MODE[3] DO4MODE[2] DO4MODE[1] DO4MODE[0] DO3MODE[3] DO3MODE[2] DO3MODE[1] DO3MODE[0] 7 6 5 4 3 2 1 0 DO2MODE[3] DO2MODE[2] DO2MODE[1] DO2MODE[0] DO1MODE[3] DO1MODE[2] DO1MODE[1] DO1MODE[0] Default = 0x00 EEEE 36 EPG4_ON Enable EPG4 block. 0 = Disable energy pulse generation block 4 (Default) 1 = Enable energy pulse generation 4 EPG3_ON Enable EPG3 block. 0 = Disable energy pulse generation block 3 (Default) 1 = Enable energy pulse generation block 3 EPG2_ON Enable EPG2 block. 0 = Disable energy pulse generation block 2 (Default) 1 = Enable energy pulse generation block 2 EPG1_ON Enable EPG1 block. 0 = Disable energy pulse generation block 1 (Default) 1 = Enable energy pulse generation block 1 DO4_OD Allow the DO4 pin to be an open-drain output. 0 = Normal output (Default) 1 = Open-drain output DO3_OD Allow the DO3 pin to be an open-drain output. 0 = Normal output (Default) 1 = Open-drain output DO2_OD Allow the DO2 pin to be an open-drain output. 0 = Normal output (Default) 1 = Open-drain output DO1_OD Allow the DO1 pin to be an open-drain output. 0 = Normal output (Default) 1 = Open-drain output DS981F2 CS5484 DO4MODE[3:0] Output control for DO4 pin. 0000 = Energy pulse generation block 1 (EPG1) output 0001 = Energy pulse generation block 2 (EPG2) output 0010 = Energy pulse generation block 3 (EPG3) output 0011 = Energy pulse generation block 4 (EPG4) output 0100 = P1 sign 0101 = P2 sign 0110 = PSUM sign 0111 = Q1 sign 1000 = Q2 sign 1001 = QSUM sign 1010 = Reserved 1011 = V1/V2 zero-crossing 1100 = I1/I2 zero-crossing 1101 = Reserved 1110 = Hi-Z, pin not driven (Default) 1111 = Interrupt DO3MODE[3:0] Output control for DO3 pin. 0000 = Energy pulse generation block 1 (EPG1) output 0001 = Energy pulse generation block 2 (EPG2) output 0010 = Energy pulse generation block 3 (EPG3) output 0011 = Energy pulse generation block 4 (EPG4) output 0100 = P1 sign 0101 = P2 sign 0110 = PSUM sign 0111 = Q1 sign 1000 = Q2 sign 1001 = QSUM sign 1010 = Reserved 1011 = V1/V2 zero-crossing 1100 = I1/I2 zero-crossing 1101 = Reserved 1110 = Hi-Z, pin not driven (Default) 1111 = Interrupt DO2MODE[3:0] Output control for DO2 pin. 0000 = Energy pulse generation block 1 (EPG1) output 0001 = Energy pulse generation block 2 (EPG2) output 0010 = Energy pulse generation block 3 (EPG3) output 0011 = Energy pulse generation block 4 (EPG4) output 0100 = P1 sign 0101 = P2 sign 0110 = PSUM sign 0111 = Q1 sign 1000 = Q2 sign 1001 = QSUM sign 1010 = Reserved 1011 = V1/V2 zero-crossing 1100 = I1/I2 zero-crossing 1101 = Reserved 1110 = Hi-Z, pin not driven (Default) 1111 = Interrupt DS981F2 37 CS5484 DO1MODE[3:0] Output control for DO1 pin. 0000 = Energy pulse generation block 1 (EPG1) output 0001 = Energy pulse generation block 2 (EPG2) output 0010 = Energy pulse generation block 3 (EPG3) output 0011 = Energy pulse generation block 4 (EPG4) output 0100 = P1 sign 0101 = P2 sign 0110 = PSUM sign 0111 = Q1 sign 1000 = Q2 sign 1001 = QSUM sign 1010 = Reserved 1011 = V1/V2 zero-crossing 1100 = I1/I2 zero-crossing 1101 = Reserved 1110 = Hi-Z, pin not driven (Default) 1111 = Interrupt 6.6.3 Configuration 2 (Config2) – Page 16, Address 0 23 - 22 POS 21 - 20 - 19 - 18 1 17 1 16 - 15 - 14 APCM 13 - 12 ZX_LPF 11 AVG_MODE 10 REG_CSUM_OFF 9 AFC 8 I2FLT[1] 7 I2FLT[0] 6 V2FLT[1] 5 V2FLT[0] 4 I1FLT[1] 3 I1FLT[0] 2 V1FLT[1] 1 V1FLT[0] 0 IIR_OFF Default = 0x06 0200 38 [23] Reserved. POS Positive energy only. Suppress negative values in P1AVG and P2AVG. If a negative value is calculated, a zero result will be stored. 0 = Positive and negative energy (Default) 1 = Positive energy only [21:15] Reserved. APCM Selects the apparent power calculation method. 0 = VxRMS IxRMS (Default) 1 = SQRT(PxAVG2 + QxAVG2) [13] Reserved. ZX_LPF Enable LPF in zero-cross detect. 0 = LPF disabled (Default) 1 = LPF enabled AVG_MODE Select averaging mode for low-rate calculations. 0 = Use SampleCount (Default) 1 = Use CycleCount REG_CSUM_OFF Disable checksum on critical registers. 0 = Enable checksum on critical registers (Default) 1 = Disable checksum on critical registers DS981F2 CS5484 AFC Enables automatic line frequency measurement which sets Epsilon every time a new line frequency measurement completes. Epsilon is used to control the gain of 90 degree phase shift integrator used in quadrature power calculations. 0 = Disable automatic line frequency measurement 1 = Enable automatic line frequency measurement (Default) I2FLT[1:0] Filter enable for current channel 2. 00 = No filter (Default) 01 = High-pass filter (HPF) on current channel 2 10 = Phase-matching filter (PMF) on current channel 2 11 = Rogowski coil integrator on current channel 2 V2FLT[1:0] Filter enable for voltage channel 2/temperature. 00 = No filter (Default) 01 = High-pass filter (HPF) on voltage channel 2 10 = Phase-matching filter (PMF) on voltage channel 2 11 = Reserved I1FLT[1:0] Filter enable for current channel 1. 00 = No filter (Default) 01 = High-pass filter (HPF) on current channel 1 10 = Phase-matching filter (PMF) on current channel 1 11 = Rogowski coil integrator on current channel 1 V1FLT[1:0] Filter enable for voltage channel 1. 00 = No filter (Default) 01 = High-pass filter (HPF) on voltage channel 1 10 = Phase-matching filter (PMF) on voltage channel 1 11 = Reserved IIR_OFF Bypass IIR filter. 0 = Do not bypass IIR filter (Default) 1 = Bypass IIR filter DS981F2 39 CS5484 6.6.4 Phase Compensation (PC) – Page 0, Address 5 23 CPCC2[1] 22 CPCC2[0] 21 CPCC1[1] 20 CPCC1[0] 19 - 18 - 17 FPCC2[8] 16 FPCC2[7] 15 FPCC2[6] 14 FPCC2[5] 13 FPCC2[4] 12 FPCC2[3] 11 FPCC2[2] 10 FPCC2[1] 9 FPCC2[0] 8 FPCC1[8] 7 6 5 4 3 2 1 0 FPCC1[7] FPCC1[6] FPCC1[5] FPCC1[4] FPCC1[3] FPCC1[2] FPCC1[1] FPCC1[0] Default = 0x00 0000 CPCC2[1:0] Coarse phase compensation control for I2 and V2. 00 = No extra delay 01 = 1 OWR delay in current channel 2 10 = 1 OWR delay in voltage channel 2 11 = 2 OWR delay in voltage channel 2 CPCC1[1:0] Coarse phase compensation control for I1 and V1. 00 = No extra delay 01 = 1 OWR delay in current channel 1 10 = 1 OWR delay in voltage channel 1 11 = 2 OWR delay in voltage channel 1 [19:18] Reserved. FPCC2[8:0] Fine phase compensation control for I2 and V2. Sets a delay in current, relative to voltage. Resolution: 0.008789° at 50Hz and 0.010547° at 60Hz (OWR = 4000) FPCC1[8:0] Fine phase compensation control for I1 and V1. Sets a delay in current, relative to voltage. Resolution: 0.008789° at 50Hz and 0.010547° at 60Hz (OWR = 4000) 6.6.5 UART Control (SerialCtrl) – Page 0, Address 7 23 - 22 - 21 - 20 - 19 - 18 17 RX_PU_OFF RX_CSUM_OFF 16 - 15 BR[15] 14 BR[14] 13 BR[13] 12 BR[12] 11 BR[11] 10 BR[10] 9 BR[9] 8 BR[8] 7 BR[7] 6 BR[6] 5 BR[5] 4 BR[4] 3 BR[3] 2 BR[2] 1 BR[1] 0 BR[0] Default = 0x02 004D 40 [23:19] Reserved. RX_PU_OFF Disable the pull-up resistor on the RX input pin. 0 = Pull-up resistor enabled (Default) 1 = Pull-up resistor disabled RX_CSUM_OFF Disable the checksum on serial port data. 0 = Enable checksum 1 = Disable checksum (Default) [16] Reserved. BR[15:0] Baud rate (serial bit rate). BR[15:0] = Baud Rate x (524,288/MCLK) DS981F2 CS5484 6.6.6 Pulse Output Width (PulseWidth) – Page 0, Address 8 23 - 22 - 21 - 20 - 19 18 17 16 FREQ_RNG[3] FREQ_RNG[2] FREQ_RNG[1] FREQ_RNG[0] 15 PW[15] 14 PW[14] 13 PW[13] 12 PW[12] 11 PW[11] 10 PW[10] 9 PW[9] 8 PW[8] 7 6 5 4 3 2 1 0 PW[7] PW[6] PW[5] PW[4] PW[3] PW[2] PW[1] PW[0] Default = 0x00 0001 (265.6µs at OWR = 4kHz) PulseWidth sets the energy pulse frequency range and the duration of energy pulses. The actual pulse duration is 250µs plus the contents of PulseWidth divided by 64,000. PulseWidth is an integer in the range of 1 to 65,535. [23:20] Reserved. FREQ_RNG[3:0] Energy pulse (PulseRate) frequency range for 0.1% resolution. 0000 = Freq. range: 2kHz–0.238Hz (Default) 0001 = Freq. range: 1kHz–0.1192Hz 0010 = Freq. range: 500 Hz–0.0596Hz 0011 = Freq. range: 250Hz–0.0298Hz 0100 = Freq. range: 125 Hz–0.0149Hz 0101 = Freq. range: 62.5 Hz–0.00745Hz 0110 = Freq. range: 31.25Hz–0.003725Hz 0111 = Freq. range: 15.625Hz–0.0018626Hz 1000 = Freq. range: 7.8125Hz–0.000931323Hz 1001 = Freq. range: 3.90625Hz–0.000465661Hz 1010 = Reserved ... 1111 = Reserved PW[15:0] Energy Pulse Width. 6.6.7 Pulse Output Rate (PulseRate) – Page 18, Address 28 MSB -(20) LSB 2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23 Default= 0x80 0000 PulseRate sets the full-scale frequency for the energy pulse outputs. For a 4 kHz OWR rate, the maximum pulse rate is 2kHz. This is a two's complement value in the range of -1value1, with the binary point to the left of the MSB. Refer to section 5.5 Energy Pulse Generation on page 22 for more information. DS981F2 41 CS5484 6.6.8 Pulse Output Control (PulseCtrl) – Page 0, Address 9 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 EPG4IN[3] 14 EPG4IN[2] 13 EPG4IN[1] 12 EPG4IN[0] 11 EPG3IN[3] 10 EPG3IN[2] 9 EPG3IN[1] 8 EPG3IN[0] 7 6 5 4 3 2 1 0 EPG2IN[3] EPG2IN[2] EPG2IN[1] EPG2IN[0] EPG1IN[3] EPG1IN[2] EPG1IN[1] EPG1IN[0] Default = 0x00 0000 This register controls the input to the energy pulse generation block (EPGx). [23:16] Reserved. EPGxIN[3:0] Selects the input to the energy pulse generation block (EPGx). 0000 = P1AVG (Default) 0001 = P2AVG 0010 = PSUM 0011 = Q1AVG 0100 = Q2AVG 0101 = QSUM 0110 = S1 0111 = S2 1000 = SSUM 1001 = Unused ... 1111 = Unused 6.6.9 Register Lock Control (RegLock) – Page 0, Address 34 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 DSP_LCK[4] 11 DSP_LCK[3] 10 DSP_LCK[2] 9 DSP_LCK[1] 8 DSP_LCK[0] 7 6 5 4 3 2 1 0 - - - HOST_LCK[4] HOST_LCK[3] HOST_LCK[2] HOST_LCK[1] HOST_LCK[0] Default = 0x00 0000 42 [23:13] Reserved. DSP_LCK[4:0] DSP_LCK[4:0] = 0x16 sets the DSP lockable registers to be write protected from the CS5484 internal calculation engine. Writing 0x09 unlocks the registers. [7:5] Reserved. HOST_LCK[4:0] HOST_LCK[4:0] = 0x16 sets all the registers except RegLock, Status0, Status1, and Status2 to be write protected from the serial interface. Writing 0x09 unlocks the registers. DS981F2 CS5484 6.6.10 Phase Sequence Detection and Control (PSDC) – Page 0, Address 48 23 DONE 22 PSCNT[6] 21 PSCNT[5] 20 PSCNT[4] 19 PSCNT[3] 18 PSCNT[2] 17 PSCNT[1] 16 PSCNT[0] 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 DIR 4 CODE[4] 3 CODE[3] 2 CODE[2] 1 CODE[1] 0 CODE[0] Default = 0x00 0000 DONE Indicates valid count values reside in PSCNT[6:0]. 0 = Invalid values in PSCNT[6:0]. (Default) 1 = Valid values in PSCNT[6:0]. PSCNT[6:0] Registers the number of OWR samples from the start time to the time when the next zero crossing is detected. [15:6] Reserved. DIR Set the zero-crossing edge direction which will stop PSCNT count. 0 = Stop count at negative to positive zero-crossing - Rising Edge. (Default) 1 = Stop count at positive to negative zero-crossing - Falling Edge. CODE[4:0] Write 10110 to this location to enable the phase sequence detection. 6.6.11 Checksum of Critical Registers (RegChk) – Page 16, Address 1 MSB 223 LSB 222 221 220 219 218 217 216 ..... 26 25 24 23 22 21 20 Default = 0x00 0000 This register contains the checksum of critical registers. DS981F2 43 CS5484 6.6.12 Interrupt Status (Status0) – Page 0, Address 23 23 DRDY 22 CRDY 21 WOF 20 - 19 - 18 MIPS 17 V2SWELL 16 V1SWELL 15 P2OR 14 P1OR 13 I2OR 12 I1OR 11 V2OR 10 V1OR 9 I2OC 8 I1OC 7 V2SAG 6 V1SAG 5 TUP 4 FUP 3 IC 2 RX_CSUM_ERR 1 - 0 RX_TO Default = 0x80 0000 The Status0 register indicates a variety of conditions within the chip. Writing a one to a Status0 register bit will clear that bit. Writing a zero to any bit has no effect. DRDY Data Ready. During conversion, this bit indicates that low-rate results have been updated. It indicates completion of other host instruction and the reset sequence. CRDY Conversion Ready. Indicates that sample rate (output word rate) results have been updated. WOF Watchdog timer overflow. [20:19] Reserved. MIPS MIPS overflow. Sets when the calculation engine has not completed processing a sample before the next one arrives. V2SWELL(V1SWELL) Voltage channel 2 (voltage channel 1) swell event detected. 44 P2OR (P1OR) Power out of range. Sets when the measured power would cause the P2 (P1) register to overflow. I2OR (I1OR) Current out of range. Set when the measured current would cause the I2 (I1) register to overflow. V2OR (V1OR) Voltage out of range. Set when the measured voltage would cause the V2 (V1) register to overflow. I2OC (I1OC) I2 (I1) overcurrent. V2SAG (V1SAG) Voltage channel 2 (voltage channel 1) sag event detected. TUP Temperature updated. Indicates when the Temperature register (T) has been updated. FUP Frequency updated. Indicates the Epsilon register has been updated. IC Invalid command has been received. RX_CSUM_ERR Received data checksum error. Sets to one automatically if checksum error is detected on serial port received data. [1] Reserved. RX_TO SDI/RX time out. Sets to one automatically when SDI/RX time out occurs. DS981F2 CS5484 6.6.13 Interrupt Mask (Mask) – Page 0, Address 3 23 DRDY 22 CRDY 21 WOF 20 - 19 - 18 MIPS 17 V2SWELL 16 V1SWELL 15 P2OR 14 P1OR 13 I2OR 12 I1OR 11 V2OR 10 V1OR 9 I2OC 8 I1OC 7 V2SAG 6 V1SAG 5 TUP 4 FUP 3 IC 2 RX_CSUM_ERR 1 - 0 RX_TO Default = 0x00 0000 The Mask register is used to control the activation of the INT pin. Writing a '1' to a Mask register bit will allow the corresponding Status0 register bit to activate the INT pin when set. [23:0] Enable/disable (mask) interrupts. 0 = Interrupt disabled (Default) 1 = Interrupt enabled 6.6.14 Chip Status 1 (Status1) – Page 0, Address 24 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 LCOM[7] 14 LCOM[6] 13 LCOM[5] 12 LCOM[4] 11 LCOM[3] 10 LCOM[2] 9 LCOM[1] 8 LCOM[0] 7 - 6 - 5 - 4 - 3 V2OD 2 V1OD 1 I2OD 0 I1OD Default = 0x80 1800 This register indicates a variety of conditions within the chip. [23:16] Reserved. LCOM[7:0] Indicates the value of the last serial command executed. V2OD (V1OD) Modulator oscillation has been detected in the voltage2 (voltage1) ADC. I2OD (I1OD) Modulator oscillation has been detected in the current2 (current1) ADC. DS981F2 45 CS5484 6.6.15 Chip Status 2 (Status2) – Page 0, Address 25 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 QSUM_SIGN 4 Q2_SIGN 3 Q1_SIGN 2 PSUM_SIGN 1 P2_SIGN 0 P1_SIGN Default = 0x00 0000 This register indicates a variety of conditions within the chip. 46 [23:6] Reserved. QSUM_SIGN Indicates the sign of the value contained in QSUM. 0 = positive value 1 = negative value Q2_SIGN Indicates the sign of the value contained in Q2AVG. 0 = positive value 1 = negative value Q1_SIGN Indicates the sign of the value contained in Q1AVG. 0 = positive value 1 = negative value PSUM_SIGN Indicates the sign of the value contained in PSUM. 0 = positive value 1 = negative value P2_SIGN Indicates the sign of the value contained in P2AVG. 0 = positive value 1 = negative value P1_SIGN Indicates the sign of the value contained in P1AVG. 0 = positive value 1 = negative value DS981F2 CS5484 6.6.16 Line to Sample Frequency Ratio (Epsilon) – Page 16, Address 49 MSB -(20) LSB 2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23 Default = 0x01 999A (0.0125 or 50Hz/4.0kHz) Epsilon is the ratio of the input line frequency to the OWR. It can either be written by the application program or calculated automatically from the line frequency (from the voltage channel 1 input) using the AFC bit in the Config2 register. It is a two's complement value in the range of -1.0 value 1.0, with the binary point to the right of the MSB. Negative values are not used. 6.6.17 No-Load Threshold (LoadMIN ) – Page 16, Address 58 MSB -(20) LSB 2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23 Default = 0x00 0000 LoadMIN is used to set the no-load threshold for the anti-creep function. When the magnitudes of PSUM and QSUM are less than LoadMIN, PSUM and QSUM are forced to zero. When the magnitude of SSUM is less than LoadMIN, SSUM is forced to zero. LoadMIN is a two’s complement value in the range of -1.0 value 1.0, with the binary point to the right of the MSB. Negative values are not used. 6.6.18 Sample Count (SampleCount) – Page 16, Address 51 MSB 0 LSB 222 221 220 219 218 217 216 ..... 26 25 24 23 22 21 20 Default = 0x00 0FA0 (4000) Determines the number of OWR samples to use in calculating low-rate results. SampleCount (N) is an integer in the range of 100 to 8,388,607. Values less than 100 should not be used. 6.6.19 Cycle Count (CycleCount) – Page 18, Address 62 MSB 0 LSB 222 221 220 219 218 217 216 ..... 26 25 24 23 22 21 20 Default = 0x00 0064 (100) Determines the number of half-line cycles to use in calculating low-rate results when the CS5484 is in Line-cycle Synchronized Averaging mode. CycleCount is an integer in the range of 1 to 8,388,607. Zero should not be used. DS981F2 47 CS5484 6.6.20 Filter Settling Time for Conversion Startup (TSETTLE) – Page 16, Address 57 MSB 223 LSB 222 221 220 219 218 217 216 ..... 26 25 24 23 22 21 20 Default = 0x00 001E (30) Sets the number of OWR samples that will be used to allow filters to settle at the beginning of Conversion and Calibration commands. This is an integer in the range of 0 to 16,777,215 samples. 6.6.21 System Gain (SysGAIN ) – Page 16, Address 60 MSB -(21) LSB 20 2-1 2-2 2-3 2-4 2-5 2-6 ..... 2-16 2-17 2-18 2-19 2-20 2-21 2-22 Default = 0x50 0000 (1.25) System Gain (SysGAIN) is applied to all channels. By default, SysGAIN = 1.25 but can be finely adjusted to compensate for voltage reference error. It is a two's complement value in the range of -2.0 value 2.0, with the binary point to the right of the second MSB. Values should be kept within 5% of 1.25. 6.6.22 Rogowski Coil Integrator Gain (IntGAIN ) – Page 18, Address 43 MSB -(20) LSB 2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23 Default = 0x14 3958 Gain for the Rogowski coil integrator. This must be programmed accordingly for 50Hz and 60Hz (0.158 for 50Hz, 0.1875 for 60Hz). This is a two's complement value in the range of -1.0 value 1.0, with the binary point to the right of the MSB. Negative values are not used. 6.6.23 System Time (Time) – Page 16, Address 61 MSB 223 LSB 222 221 220 219 218 217 216 ..... 26 25 24 23 22 21 20 Default = 0x00 0000 System Time (Time) is measured in OWR samples. This is an unsigned integer in the range of 0 to 16,777,215 samples. At OWR = 4.0kHz, OWR will overflow every 1 hour, 9 minutes, 54 seconds. Time can be used by the application to manage real-time events. 48 DS981F2 CS5484 6.6.24 Voltage 1 Sag Duration (V1SagDUR ) – Page 17, Address 0 MSB 0 LSB 222 221 220 219 218 217 216 ..... 26 25 24 23 22 21 20 Default = 0x00 0000 Voltage sag duration, V1SagDUR, determines the count of OWR samples utilized to determine a sag event. These are integers in the range of 0 to 8,388,607 samples. A value of zero disables the feature. 6.6.25 Voltage 1 Sag Level (V1SagLEVEL ) – Page 17, Address 1 MSB -(20) LSB 2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23 Default = 0x00 0000 Voltage sag level, V1SagLEVEL, establishes an input level below which a sag event is triggered. This is a two's complement value in the range of -1.0 value 1.0, with the binary point to the right of the MSB. Negative values are not used. 6.6.26 Current 1 Overcurrent Duration (I1OverDUR ) – Page 17, Address 4 MSB 0 LSB 222 221 220 219 218 217 216 ..... 26 25 24 23 22 21 20 Default = 0x00 0000 Overcurrent duration, I1OverDUR, determines the count of OWR samples utilized to determine an overcurrent event. These are integers in the range of 0 to 8,388,607 samples. A value of zero disables the feature. 6.6.27 Current 1 Overcurrent Level (I1OverLEVEL ) – Page 17, Address 5 MSB -(20) LSB 2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23 Default = 0x7F FFFF Overcurrent level, I1OverLEVEL, establishes an input level above which an overcurrent event is triggered. This is a two's complement value in the range of -1.0 value 1.0, with the binary point to the right of the MSB. Negative values are not used. DS981F2 49 CS5484 6.6.28 Voltage 2 Sag Duration (V2SagDUR ) – Page 17, Address 8 MSB 0 LSB 222 221 220 219 218 217 216 ..... 26 25 24 23 22 21 20 Default = 0x00 0000 Voltage sag duration, V2SagDUR, determines the count of OWR samples utilized to determine a sag event. These are integers in the range of 0 to 8,388,607 samples. A value of zero disables the feature. 6.6.29 Voltage 2 Sag Level (V2SagLEVEL ) – Page 17, Address 9 MSB -(20) LSB 2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23 Default = 0x00 0000 Voltage sag level, V2SagLEVEL, establishes an input level below which a sag event is triggered. This is a two's complement value in the range of -1.0 value 1.0, with the binary point to the right of the MSB. Negative values are not used. 6.6.30 Current 2 Overcurrent Duration (I2OverDUR ) – Page 17, Address 12 MSB 0 LSB 222 221 220 219 218 217 216 ..... 26 25 24 23 22 21 20 Default = 0 x00 0000 Overcurrent duration, I2OverDUR, determines the count of OWR samples utilized to determine an overcurrent event. These are integers in the range of 0 to 8,388,607 samples. A value of zero disables the feature. 6.6.31 Current 2 Overcurrent Level (I2OverLEVEL ) – Page 17, Address 13 MSB -(20) LSB 2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23 Default = 0x7F FFFF Overcurrent level, I2OverLEVEL, establishes an input level above which an overcurrent event is triggered. This is a two's complement value in the range of -1.0value1.0, with the binary point to the right of the MSB. Negative values are not used. 50 DS981F2 CS5484 6.6.32 Voltage 1 Swell Duration (V1SwellDUR ) – Page 18, Address 46 MSB 0 LSB 222 221 220 219 218 217 216 ..... 26 25 24 23 22 21 20 Default = 0x00 0000 Voltage swell duration, V1SwellDUR, determines the count of OWR samples utilized to determine a swell event. These are integers in the range of 0 to 8,388,607 samples. A value of zero disables the feature. 6.6.33 Voltage 1 Swell Level (V1SwellLEVEL ) – Page 18, Address 47 MSB -(20) LSB 2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23 Default = 0x7F FFFF Voltage swell level, V1SwellLEVEL, establishes an input level above which a swell event is triggered. This is a two's complement value in the range of -1.0value1.0, with the binary point to the right of the MSB. Negative values are not used. 6.6.34 Voltage 2 Swell Duration (V2SwellDUR ) – Page 18, Address 50 MSB 0 LSB 222 221 220 219 218 217 216 ..... 26 25 24 23 22 21 20 Default = 0x00 0000 Voltage swell duration, V2SwellDUR, determines the count of OWR samples utilized to determine a swell event. These are integers in the range of 0 to 8,388,607 samples. A value of zero disables the feature. 6.6.35 Voltage 2 Swell Level (V2SwellLEVEL ) – Page 18, Address 51 MSB -(20) LSB 2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23 Default = 0x7F FFFF Voltage swell level, V2SwellLEVEL, establishes an input level above which a swell event is triggered. This is a two's complement value in the range of -1.0 value 1.0, with the binary point to the right of the MSB. Negative values are not used. DS981F2 51 CS5484 6.6.36 Instantaneous Current 1 (I1) – Page 16, Address 2 MSB -(20) LSB 2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23 Default = 0x00 0000 I1 contains instantaneous current measurements for current channel 1. This is a two's complement value in the range of -1.0value1.0, with the binary point to the right of the MSB. 6.6.37 Instantaneous Voltage 1 (V1) – Page 16, Address 3 MSB -(20) LSB 2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23 Default = 0x00 0000 V1 contains instantaneous voltage measurements for voltage channel 1. This is a two's complement value in the range of -1.0 value 1.0, with the binary point to the right of the MSB. 6.6.38 Instantaneous Active Power 1 (P1) – Page 16, Address 4 MSB -(20) LSB 2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23 Default = 0x00 0000 P1 contains instantaneous power measurements for current and voltage channels 1. Values in registers I1 and V1 are multiplied to generate this value. This is a two's complement value in the range of -1.0 value 1.0, with the binary point to the right of the MSB. 6.6.39 Active Power 1 (P1AVG ) – Page 16, Address 5 MSB -(20) LSB 2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23 Default = 0x00 0000 Instantaneous power is averaged over each low-rate interval (SampleCount samples) and then added with power offset (POFF) to compute active power (PAVG). This is a two's complement value in the range of -1.0 value 1.0, with the binary point to the right of the MSB. 52 DS981F2 CS5484 6.6.40 RMS Current 1 (I1RMS ) – Page 16, Address 6 MSB 2-1 LSB 2-2 2-3 2-4 2-5 2-6 2-7 2-8 ..... 2-18 2-19 2-20 2-21 2-22 2-23 2-24 Default = 0x00 0000 I1RMS contains the root mean square (RMS) values of I1, calculated during each low-rate interval. This is an unsigned value in the range of 0 value 1.0, with the binary point to the left of the MSB. 6.6.41 RMS Voltage 1 (V1RMS ) – Page 16, Address 7 MSB 2-1 LSB 2-2 2-3 2-4 2-5 2-6 2-7 2-8 ..... 2-18 2-19 2-20 2-21 2-22 2-23 2-24 Default = 0x00 0000 V1RMS contains the root mean square (RMS) value of V1, calculated during each low-rate interval. This is an unsigned value in the range of 0 value 1.0, with the binary point to the left of the MSB. 6.6.42 Instantaneous Current 2 (I2) – Page 16, Address 8 MSB -(20) LSB 2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23 Default = 0x00 0000 I2 contains instantaneous current measurements for current channel 2. This is a two's complement value in the range of -1.0 value 1.0, with the binary point to the right of the MSB. 6.6.43 Instantaneous Voltage 2 (V2) – Page 16, Address 9 MSB -(20) LSB 2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23 Default = 0x00 0000 V2 contains instantaneous voltage measurements for voltage channel 2. This is a two's complement value in the range of -1.0 value 1.0, with the binary point to the right of the MSB. DS981F2 53 CS5484 6.6.44 Instantaneous Active Power 2 (P2) – Page 16, Address 10 MSB -(20) LSB 2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23 Default = 0x00 0000 P2 contains instantaneous power measurements for current and voltage channels 2. Values in registers I2 and V2 are multiplied to generate this value. This is a two's complement value in the range of -1.0 value 1.0, with the binary point to the right of the MSB. 6.6.45 Active Power 2 (P2AVG ) – Page 16, Address 11 MSB -(20) LSB 2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23 Default = 0x00 0000 Instantaneous power is averaged over each low-rate interval (SampleCount samples) to compute active power (P2AVG). This is a two's complement value in the range of -1.0 value 1.0, with the binary point to the right of the MSB. 6.6.46 RMS Current 2 (I2RMS) – Page 16, Address 12 MSB 2-1 LSB 2-2 2-3 2-4 2-5 2-6 2-7 2-8 ..... 2-18 2-19 2-20 2-21 2-22 2-23 2-24 Default = 0x00 0000 I2RMS contains the root mean square (RMS) value of I2, calculated during each low-rate interval. This is an unsigned value in the range of 0 value 1.0, with the binary point to the left of the MSB. 6.6.47 RMS Voltage 2 (V2RMS ) – Page 16, Address 13 MSB 2-1 LSB 2-2 2-3 2-4 2-5 2-6 2-7 2-8 ..... 2-18 2-19 2-20 2-21 2-22 2-23 2-24 Default = 0x00 0000 V2RMS contains the root mean square (RMS) value of V2, calculated during each low-rate interval. This is an unsigned value in the range of 0value 1.0, with the binary point to the left of the MSB. 54 DS981F2 CS5484 6.6.48 Reactive Power 1 (Q1Avg ) – Page 16, Address 14 MSB -(20) LSB 2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23 Default = 0x00 0000 Reactive power 1 (Q1AVG) is Q1 averaged over each low-rate interval (SampleCount samples) and corrected by QOFF. This is a two's complement value in the range of -1.0 value 1.0, with the binary point to the right of the MSB. 6.6.49 Instantaneous Quadrature Power 1 (Q1) – Page 16, Address 15 MSB -(20) LSB 2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23 Default = 0x00 0000 Instantaneous quadrature power, Q1, the product of V1 shifted 90 degrees and I1. This is a two's complement value in the range of -1.0 value 1.0, with the binary point to the right of the MSB. 6.6.50 Reactive Power 2 (Q2Avg ) – Page 16, Address 16 MSB -(20) LSB 2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23 Default = 0x00 0000 Reactive power 2 (Q2AVG) is Q2 averaged over each low-rate interval (SampleCount samples). This is a two's complement value in the range of -1.0 value 1.0, with the binary point to the right of the MSB. 6.6.51 Instantaneous Quadrature Power 2 (Q2) – Page 16, Address 17 MSB -(20) LSB 2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23 Default = 0x00 0000 Instantaneous quadrature power, Q2, the product of V2 shifted 90 degrees and I2. This is a two's complement value in the range of -1.0 value 1.0, with the binary point to the right of the MSB. DS981F2 55 CS5484 6.6.52 Peak Current 1 (I1PEAK) – Page 0, Address 37 MSB -(20) LSB 2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23 Default = 0x00 0000 Peak current1 (I1PEAK) contains the value of the instantaneous current 1 sample with the greatest magnitude detected during the last low-rate interval. This is a two's complement value in the range of -1.0 value 1.0, with the binary point to the right of the MSB. 6.6.53 Peak Voltage 1 (V1PEAK) – Page 0, Address 36 MSB -(20) LSB 2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23 Default = 0x00 0000 Peak voltage 1 (V1PEAK) contains the value of the instantaneous voltage 1 sample with the greatest magnitude detected during the last low-rate interval. This is a two's complement value in the range of -1.0 value 1.0, with the binary point to the right of the MSB. 6.6.54 Apparent Power 1 (S1) – Page 16, Address 20 MSB 0 LSB 2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23 Default = 0x00 0000 Apparent power 1 (S1) is the product of V1RMS and I1RMS or SQRT(P1AVG2 + Q1AVG2). This is an unsigned value in the range of 0 value 1.0, with the binary point to the right of the MSB. 6.6.55 Power Factor 1 (PF1) – Page 16, Address 21 MSB -(20) LSB 2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23 Default = 0x00 0000 Power factor 1 (PF1) is calculated by dividing active power 1 (P1AVG) by apparent power 1 (S1). The sign is determined by the active power (P1AVG) sign. This is a two's complement value in the range of -1.0 value 1.0, with the binary point to the right of the MSB. 56 DS981F2 CS5484 6.6.56 Peak Current 2 (I2PEAK) – Page 0, Address 39 MSB -(20) LSB 2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23 Default = 0x00 0000 Peak current, I2PEAK, contains the value of the instantaneous current 2 sample with the greatest magnitude detected during the last low-rate interval. This is a two's complement value in the range of -1.0value1.0, with the binary point to the right of the MSB. 6.6.57 Peak Voltage 2 (V2PEAK) – Page 0, Address 38 MSB -(20) LSB 2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23 Default = 0x00 0000 Peak voltage, V2PEAK, contains the value of the instantaneous voltage 2 sample with the greatest magnitude detected during the last low-rate interval. This is a two's complement value in the range of -1.0value1.0, with the binary point to the right of the MSB. 6.6.58 Apparent Power 2 (S2) – Page 16, Address 24 MSB 0 LSB 2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23 Default = 0x00 0000 Apparent power 2 (S2) is the product of V2RMS and I2RMS or SQRT(P2AVG2 + Q2AVG2). This is an unsigned value in the range of 0value 1.0, with the binary point to the right of the MSB. 6.6.59 Power Factor 2 (PF2) – Page 16, Address 25 MSB -(20) LSB 2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23 Default = 0x00 0000 Power factor 2 (PF2) is calculated by dividing active power 2 (P2AVG) by apparent power 2 (S2). The sign is determined by the active power (P2AVG) sign. This is a two's complement value in the range of -1.0 value 1.0, with the binary point to the right of the MSB. DS981F2 57 CS5484 6.6.60 Temperature (T) – Page 16, Address 27 MSB -(27) LSB 26 25 24 23 22 21 20 ..... 2-10 2-11 2-12 2-13 2-14 2-15 2-16 Default = 0x00 0000 T contains results from the on-chip temperature measurement. By default, T uses the Celsius scale and is a two's complement value in the range of -128.0value128.0 (°C), with the binary point to the right of bit 16. T can be rescaled by the application using the TGAIN and TOFF registers. 6.6.61 Total Active Power (PSUM ) – Page 16, Address 29 MSB -(20) LSB 2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23 Default = 0x00 0000 PSUM = P1AVG +P2AVG This is a two's complement value in the range of -1.0value1.0, with the binary point to the right of the MSB. 6.6.62 Total Apparent Power (SSUM ) – Page 16, Address 30 MSB 0 LSB 2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23 Default = 0x00 0000 SSUM = S1+S2 This is an unsigned value in the range of 0.0value1.0, with the binary point to the right of the MSB. 6.6.63 Total Reactive Power (QSUM ) – Page 16, Address 31 MSB -(20) LSB 2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23 Default = 0x00 0000 QSUM = Q1AVG +Q2AVG This is a two's complement value in the range of -1.0 value1.0, with the binary point to the right of the MSB. 58 DS981F2 CS5484 6.6.64 DC Offset for Current (I1DCOFF , I2DCOFF ) – Page 16, Address 32, 39 MSB -(20) LSB 2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23 Default = 0x00 0000 DC offset registers I1DCOFF and I2DCOFF are initialized to zero on reset. During DC offset calibration, selected registers are written with the inverse of the DC offset measured. The application program can also write the DC offset register values. These are two's complement values in the range of -1.0 value 1.0, with the binary point to the right of the MSB. 6.6.65 DC Offset for Voltage (V1DCOFF , V2DCOFF ) – Page 16, Address 34, 41 MSB -(20) LSB 2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23 Default = 0x00 0000 DC offset registers V1DCOFF and V2DCOFF are initialized to zero on reset. During DC offset calibration, selected registers are written with the inverse of the DC offset measured. The application program can also write the DC offset register values. These are two's complement values in the range of -1.0 value1.0, with the binary point to the right of the MSB. 6.6.66 Gain for Current (I1GAIN , I2GAIN ) – Page 16, Address 33, 40 MSB LSB 21 20 2-1 2-2 2-3 2-4 2-5 2-6 ..... 2-16 2-17 2-18 2-19 2-20 2-21 2-22 Default = 0x40 0000 (1.0) Gain registers I1GAIN and I2GAIN are initialized to 1.0 on reset. During gain calibration, selected register are written with the multiplicative inverse of the gain measured. These are unsigned fixed-point values in the range of 0 value 4.0, with the binary point to the right of the second MSB. 6.6.67 Gain for Voltage (V1GAIN , V2GAIN ) – Page 16, Address 35, 42 MSB LSB 21 20 2-1 2-2 2-3 2-4 2-5 2-6 ..... 2-16 2-17 2-18 2-19 2-20 2-21 2-22 Default = 0x40 0000 (1.0) Gain registers V1GAIN and V2GAIN are initialized to 1.0 on reset. During gain calibration, selected registers are written with the multiplicative inverse of the gain measured. These are unsigned fixed-point values in the range of 0 value4.0, with the binary point to the right of the second MSB. DS981F2 59 CS5484 6.6.68 Average Active Power Offset (P1OFF, P2OFF ) – Page 16, Address 36, 43 MSB -(20) LSB 2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23 Default = 0x00 0000 Average Active Power offset P1OFF (P2OFF ) is added to averaged power to yield P1AVG (P2AVG ) register results. It can be used to reduce systematic energy errors. These are two's complement values in the range of -1.0 value 1.0, with the binary point to the right of the MSB. 6.6.69 Average Reactive Offset (Q1OFF , Q2OFF ) – Page 16, Address 38, 45 MSB -(20) LSB 2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23 Default = 0x00 0000 Average Reactive Power offset Q1OFF (Q2OFF ) is added to averaged reactive power to yield Q1AVG (Q2AVG ) register results. It can be used to reduce systematic energy errors. These are two's complement values in the range of -1.0 value 1.0, with the binary point to the right of the MSB. 6.6.70 AC Offset for Current (I1ACOFF, I2ACOFF ) – Page 16, Address 37, 44 MSB 2-1 LSB 2-2 2-3 2-4 2-5 2-6 2-7 2-8 ..... 2-18 2-19 2-20 2-21 2-22 2-23 2-24 Default = 0x00 0000 AC offset registers I1ACOFF and I2ACOFF are initialized to zero on reset. They are used to reduce systematic errors in the RMS results.These are unsigned values in the range of 0 value 1.0, with the binary point to the left of the MSB. 6.6.71 Temperature Gain (TGAIN ) – Page 16, Address 54 MSB 27 LSB 26 25 24 23 22 21 20 ..... 2-10 2-11 2-12 2-13 2-14 2-15 2-16 Default = 0x 06 B716 Register TGAIN is used to scale the Temperature register (T), and is an unsigned fixed-point value in the range of 0.0value256.0, with the binary point to the right of bit 16. Register T can be rescaled by the application using the TGAIN and TOFF registers. Refer to section 7.3 Temperature Sensor Calibration on page 64 for more information. 60 DS981F2 CS5484 6.6.72 Temperature Offset (TOFF ) – Page 16, Address 55 MSB LSB -(27) 26 25 24 23 22 21 20 ..... 2-10 2-11 2-12 2-13 2-14 2-15 2-16 Default = 0x D5 3998 Register TOFF is used to offset the Temperature register (T), and is a two's complement value in the range of -128.0value128.0 (°C), with the binary point to the right of bit 16. Register T can be rescaled by the application using the TGAIN and TOFF registers. Refer to section 7.3 Temperature Sensor Calibration on page 64 for more information. 6.6.73 Calibration Scale (Scale) – Page18, Address 63 MSB -(20) LSB 2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23 Default = 0 x4C CCCC (0.6) The Scale register is used in the gain calibration to set the level of calibrated results of I-channel RMS. During gain calibration, the IxRMS results register is divided into the Scale register. The quotient is put into the IxGAIN register. This is a two's complement value in the range of -1.0 value 1.0, with the binary point to the right of the MSB. Negative values are not used. 6.6.74 V-Channel Zero-crossing Threshold (VZXLEVEL) – Page 18, Address 58 MSB -(20) LSB 2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23 Default = 0x10 0000 (0.125) VZXLEVEL is the level that the peak instantaneous voltage must exceed for the zero-crossing detection to function. This is a two's complement value in the range of -1.0 value<1.0, with the binary point to the right of the MSB. Negative values are not used. 6.6.75 I-Channel Zero-crossing Threshold (IZXLEVEL) – Page 18, Address 24 MSB -(20) LSB 2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23 Default = 0x10 0000 (0.125) IZXLEVEL is the level that the peak instantaneous current must exceed for the zero-crossing detection to function. This is a two's complement value in the range of -1.0 value<1.0, with the binary point to the right of the MSB. Negative values are not used. 6.6.76 Zero-crossing Number (ZXNUM) – Page 0, Address 55 MSB 223 LSB 222 221 220 219 218 217 216 ..... 26 25 24 23 22 21 20 Default = 0x00 0064 (100) ZXNUM is the number of zero crossings used for line frequency measurement. It is an integer in the range of 1 to 8,388,607. Zero should not be used. DS981F2 61 CS5484 7. SYSTEM CALIBRATION commands. The value in the SampleCount register determines the number (N) of output word rate (OWR) samples that are averaged during a calibration. The calibration procedure takes the time of N+TSETTLE OWR samples. As N is increased, the calibration takes more time, but the accuracy of the calibration results tends to increase. Component tolerances, residual ADC offset, and system noise require a meter that needs to be calibrated before it meets a specific accuracy requirement. The CS5484 provides an on-chip calibration algorithm to operate the system calibration quickly and easily. Benefiting from the excellent linearity and low noise level of the CS5484, normally a CS5484 meter only needs one calibration at a single load point to achieve accurate measurements over the full load range. The DRDY bit in the Status0 register will be set at the completion of calibration commands. If an overflow occurs during calibration, other Status0 bits may be set as well. 7.1 Calibration in General The CS5484 provides DC offset and gain calibration that can be applied to the instantaneous voltage and current measurements and AC offset calibration, which can be applied to the voltage and current RMS calculations. 7.1.1 Offset Calibration During offset calibrations, no line voltage or current should be applied to the meter; the differential signal on voltage inputs V1IN± (V2IN±) or current inputs IIN1± (IIN2±) of the CS5484 should be 0V. Since the voltage and current channels have independent offset and gain registers, offset and gain calibration can be performed on any channel independently. 7.1.1.1 DC Offset Calibration The DC offset calibration command measures and averages DC values read on specified voltage or current channels at zero input and stores the inverse result in the associated offset registers. This DC offset will be added to instantaneous measurements in subsequent conversions, removing the offset. The data flow of the calibration is shown in Figure 23. Note that in Figure 23 the AC offset registers and gain registers affect the output results differently than the DC offset registers. The DC offset and gain values are applied to the voltage/current signals early in the signal path; the DC offset register and gain register values affect all CS5484 results. This is not true for the AC offset correction. The AC offset registers only affect the results of the RMS voltage and current calculations. The gain register for the channel being calibrated should be set to 1.0 prior to performing DC offset calibration. DC offset calibration is not required if the high-pass filter is enabled on that channel because the DC component will be removed by the high-pass filter.* The CS5484 must be operating in its active state and ready to accept valid commands. Refer to section 6.1.2 Instructions on page 27 for different calibration V*, I*, P*, Q* Registers IN Modulator N Filter IDCOFF *, VDCOFF* Registers IGAIN*, VGAIN* Registers VRMS* , IRMS* Registers N N -1 I ACOFF *Ϯ Register N -1 * Denotes readable/writable register Ϯ Applies only to the current path (I1, I2) DC 0.6(Scale *Ϯ) RMS RMS Figure 23. Calibration Data Flow 62 DS981F2 CS5484 7.1.1.2 AC Offset Calibration The AC offset calibration command measures the residual RMS values on the current channel at zero input and stores the squared result in the associated AC offset register. This AC offset will be subtracted from RMS measurements in subsequent conversions, removing the AC offset on the associated current channel. The AC offset register for the channel being calibrated should first be cleared prior to performing the calibration. The high-pass filter should be enabled if AC offset calibration is used. It is recommended that TSETTLE be set to 2000 ms before performing an AC offset calibration. Note that the AC offset register holds the square of RMS value measured during calibration. Therefore, it can hold a maximum RMS noise of 0xFFFFFF . This is the maximum RMS noise that AC offset correction can remove. 7.1.2 Gain Calibration Prior to executing the gain calibration command, gain registers for any path to be calibrated (VxGAIN, IxGAIN) should be set to 1.0, and TSETTLE should be set to 2000 ms. For gain calibration, a reference signal must be applied to the meter. During gain calibration, the voltage RMS result register (VxRMS) is divided into 0.6, and the current RMS result register (IxRMS) is divided into the Scale register. The quotient is put into the associated gain register. The gain calibration algorithm attempts to adjust the gain register (VxGAIN, IxGAIN) such that the voltage RMS result register (VxRMS) equals 0.6, and the current RMS result register (IxRMS) equals the Scale register. Note that for the gain calibration, there are limitations on choosing the reference level and the Scale register value. Using a reference or a scale that is too large or too small can cause register overflow during calibration or later during normal operation. Either condition can set Status register bits I1OR (I2OR) V1OR (V2OR). The maximum value that the gain register can attain is four. Using inappropriate reference levels or scale values may also cause the CS5484 to attempt to set the gain register higher than four, therefore the gain calibration result will be invalid. The Scale register is 0.6 by default. The maximum voltage (UMAX Volts) and current (IMAX Amps) of the meter should be used as the reference signal level if the Scale register is 0.6. After gain calibration, 0.6 of the VxRMS (IxRMS) register represents UMAX Volts (IMAX Amps) for the line voltage (load current); 0.36 of the PxAVG, QxAVG, or Sx register represents UMAX ×IMAX DS981F2 Watts, Vars, or VAs for the active, reactive, or apparent power. If the calibration is performed with UMAX Volts and ICAL Amps and ICAL <IMAX, the Scale register needs to be scaled down to 0.6×ICAL /IMAX before performing gain calibration. After gain calibration, 0.6 of the VxRMS register represents UMAX Volts, 0.6xICAL /IMAX of the IxRMS register represents ICAL Amps, and 0.36 x ICAL / IMAX of the PxAVG, QxAVG, or Sx register represents UMAX xICAL Watts, Vars, or VAs. 7.1.3 Calibration Order 1. If the HPF option is enabled, then any DC component that may be present in the selected signal channel will be removed, and a DC offset calibration is not required. However, if the HPF option is disabled, the DC offset calibration should be performed. When using high-pass filters, it is recommended that the DC offset register for the corresponding channel be set to zero. Before performing DC offset calibration, the DC offset register should be set to 0, and the corresponding gain register should be set to 1. 2. If there is an AC offset in the IxRMS calculation, the AC offset calibration should be performed on the current channel. Before performing AC offset calibration, the AC offset register should be set to 0. It is recommended that TSETTLE be set to 2000ms before performing an AC offset calibration. 3. Perform the gain calibration. 4. If an AC offset calibration was performed (step 2), then the AC offset may need to be adjusted to compensate for the change in gain (step 3). This can be accomplished by restoring zero to the AC offset register and then performing an AC offset calibration. The adjustment could also be done by multiplying the AC offset register value that was calculated in step 2 by the gain calculated in step 3 and updating the AC offset register with the product. 7.2 Phase Compensation A phase compensation mechanism is provided to adjust for meter-to-meter variation in signal path delays. Phase offset between a voltage channel and its corresponding current channel can be calculated by using the power factor (PF1, PF2) register after a conversion. 1) Apply a reference voltage and current with a lagging power factor to the meter. The reference current waveform should lag the voltage with a 60° phase shift. 2) Start continuous conversion. 63 CS5484 3) Accumulate multiple readings of the PF1 or PF2 register. 4) Calculate the average power factor, PFavg. 5) Calculate phase offset = arccos(PFavg) - 60°. 6) If the phase offset is negative, then the delay should be added only to the current channel. Otherwise, add more delay to the voltage channel than to the current channel to compensate for a positive phase offset. 7.3.1 Temperature Offset and Gain Calibration To obtain the optimal temperature offset (TOFF) register value and temperature (TGAIN) register value, it is necessary to measure the temperature (T) register at a minimum of two points (T1 and T2) across the meter operating temperature range. The two temperature points must be far enough apart to yield reasonable accuracy, for example 25 °C and 85° C. Obtain a linear fit of these points ( y = m x + b ), where the slope (m) and intercept (b) can be obtained. Once the phase offset is known, the CPCCx and FPCCx bits for that channel are calculated and programmed in the PC register. The compensation resolution is 0.008789° at 50Hz and 0.010547° at 60Hz at an OWR of 4000Hz. 7.3 Temperature Sensor Calibration Temperature sensor calibration involves the adjustment of two parameters: temperature gain (TGAIN) and temperature offset (TOFF). Before calibration, TGAIN must be set to 1.0 (0x 01 0000), and TOFF must be set to 0.0 (0x 00 0000). Y= m •x +b Force Temperature (°C) CPCCx bits are used if either: • The phase offset is more than 1 output word rate (OWR) sample. • More delay is needed on the voltage channel. T2 m T1 b T Register Value Figure 24. T Register vs. Force Temp TOFF and TGAIN are calculated using the following equations: b T OFF = ----m T GAIN = m 64 DS981F2 CS5484 8. BASIC APPLICATION CIRCUITS Figure 25 shows the CS5484 configured to measure power in a single-phase, 3-wire system with two voltages and two currents. In this diagram, current transformers (CTs) are used to sense the line load currents, and resistive voltage dividers are used to sense the line voltage. +3.3V +3.3V 0.1uF L1 N 0.1uF Wh VDDA MODE VDDD L2 VIN1+ Varh +3.3V 27nF SSEL 27nF 1K 5 x 250K 1K 1K 1K 5 x 250K VIN1- DO1 VIN2- DO2 27nF 27nF DO3 DO4 VIN2+ ½ R BURDEN CT ½ R BURDEN CS 27nF 1K Interrupt TX IIN1+ 27nF Zero Crossings RX CS5484 1K +3.3V IIN1- 4.096MHz XOUT VREF+ CT ½ R BURDEN 1K IIN2+ 27nF 27nF LOA D LOA D 0.1uF VREF- ½ R BURDEN 1K Application Processor XIN IIN2- +3.3V 10K RESET GNDA GNDD 0.1 uF Figure 25. Typical Connection (Single-phase, 3-wire, 12S Electricity Meter) DS981F2 65 CS5484 9. PACKAGE DIMENSIONS 28 QFN (5mmX5mm BODY with EXPOSED PAD) PACKAGE DRAWING Dimension A A1 A3 b D D2 e E E2 L aaa bbb ddd eee MIN 0.80 0.00 0.20 3.50 3.50 0.35 mm NOM 0.90 0.02 0.20 REF 0.25 5.00 BSC 3.65 0.50 BSC 5.00 BSC 3.65 0.40 0.15 0.10 0.05 0.08 MAX 1.00 0.05 MIN 0.031 0.000 0.30 0.008 3.80 0.138 3.80 0.45 0.138 0.014 inch NOM 0.035 0.001 0.008 REF 0.010 0.197 BSC 0.144 0.020 BSC 0.197 BSC 0.144 0.016 0.006 0.004 0.002 0.003 MAX 0.039 0.002 0.012 0.150 0.150 0.018 Notes: 1. Controlling dimensions are in millimeters. 2. Dimensions and tolerances per ASME Y14.5M. 3. This drawing conforms to JEDEC outline MO-220, variation VHHD-3. 4. Recommended reflow profile is per JEDEC/IPC J-STD-020. 66 DS981F2 CS5484 10. ORDERING INFORMATION Ordering Number Container CS5484-INZ Bulk CS5484-INZR Tape & Reel Temperature Package -40 to +85 °C 28-pin QFN, Lead (Pb) Free 11. ENVIRONMENTAL, MANUFACTURING, AND HANDLING INFORMATION Part Number Peak Reflow Temp MSL Rating* Max Floor Life CS5484-INZ 260°C 3 7 Days * MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020. 12. REVISION HISTORY Revision Date PP1 APR 2012 Preliminary release. F1 APR 2012 Edited for content and clarity. F2 JUN 2012 Updated ordering information. DS981F2 Changes 67 CS5484 Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you go to www.cirrus.com IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. 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INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, the Cirrus Logic logo designs, EXL Core, and the EXL Core logo design are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. SPI is a trademark of Motorola, Inc. 68 DS981F2