CSD75204W15 www.ti.com.............................................................................................................................................................................................. SLPS221 – OCTOBER 2009 Dual P-Channel NexFET™ Power MOSFET Check for Samples: CSD75204W15 FEATURES 1 • • • • • • • • Table 1. PRODUCT SUMMARY Dual P-Ch MOSFETs Common Source Configuration Small Footprint 1.5-mm × 1.5-mm Gate-Source Voltage Clamp Gate ESD Protection –3kV Pb Free RoHS Compliant Halogen Free VD1D2 Drain to Drain Voltage –20 V Qg Gate Charge Total (-4.5V) 2.8 nC Qgd Gate Charge Gate to Drain RD1D2(on) Drain to Drain On Resistance VGS(th) Battery Management Battery Protection mΩ VGS = –2.5V 105 mΩ VGS = –4.5V 80 mΩ Threshold Voltage –0.7 Device Package Media CSD75204W15 1.5-mm × 1.5-mm Wafer Level Package 7-Inch Reel DESCRIPTION V Qty Ship 3000 Tape and Reel ABSOLUTE MAXIMUM RATINGS The device has been designed to deliver the lowest on resistance and gate charge in the smallest outline possible with excellent thermal characteristics in an ultra low profile. Low on resistance coupled with the small footprint and low profile make the device ideal for battery operated space constrained applications. Top View G1 D1 SS VALUE UNIT –20 V Gate to Source Voltage -6 V Continuous Drain to Drain Current, TC = 25°C (1) –3 A Pulsed Drain to Drain Current, TC = 25°C (2) -28 A Continuous Source Pin Current -1.2 A Pulsed Source Pin Current (2) -15 A Continuous Gate Clamp Current -0.5 A VD1D2 Drain to Drain Voltage VGS ID1D2 IG D1 D2 TA = 25°C unless otherwise stated IS D1 D2 G2 Pulsed Gate Clamp Current (2) -7 A PD Power Dissipation (1) 0.7 W TJ, TSTG Operating Junction and Storage Temperature Range –55 to 150 °C D2 (1) (2) P0109-01 Per device, both sides in conduction Pulse duration 10μs, duty cycle ≤2% RD1D2(on) vs VGS Gate Charge (Per MOSFET) 300 6 ID1D2 = −1A −VGS − Gate to Source Voltage − V RD1D2(on) − On-State Resistance − mΩ nC 140 ORDERING INFORMATION APPLICATIONS • • 0.6 VGS = –1.8V 250 200 TJ = 125°C TJ = 25°C 150 100 50 0 0 1 2 3 4 −VGS − Gate to Source Voltage − V 5 6 G006 5 ID1D2 = −1A VD1D2 = −10V 4 3 2 1 0 0.0 0.5 1.0 1.5 2.0 Qg − Gate Charge − nC 2.5 3.0 G003 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2009, Texas Instruments Incorporated CSD75204W15 SLPS221 – OCTOBER 2009.............................................................................................................................................................................................. www.ti.com ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise stated). Specifications and graphs are Per MOSFET unless otherwise stated. Drain to Drain measurements are done with both MOSFETs in series (common source configuration. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Static Characteristics BVD1D2 Drain to Drain Voltage VGS = 0V, ID1D2 = –250μA –20 BVGSS Gate to Source Voltage VD1D2 = 0V, IG = -250μA -6.1 IDDS Drain to Source Leakage Current VGS = 0V, VD1D2 = –16V IGSS Gate to Source Leakage Current VD1D2 = 0V, VGS = -6V VGS(th) Gate to Source Threshold Voltage VD1D2 = VGS, IDS = –250μA RD1D2(on) Drain to Drain On Resistance gfs Transconductance V -7.2 V –1 μA –100 nA –0.7 –0.9 V VGS = –1.8V, ID1D2 = –1A 140 175 mΩ VGS = –2.5V, ID1D2 = –1A 105 130 mΩ VGS = –4.5V, ID1D2 = –1A 80 100 mΩ VD1D2 = –10V, ID1D2 = –1A 5.3 –0.5 S Dynamic Characteristics CISS Input Capacitance VGS = 0V, VD1D2 = –10V, f = 1MHz 315 410 pF pF COSS Output Capacitance 128 165 CRSS Reverse Transfer Capacitance 43 55 pF Qg Gate Charge Total (–4.5V) 2.8 3.9 nC Qgd Gate Charge - Gate to Drain Qgs Gate Charge - Gate to Source Qg(th) Gate Charge at Vth QOSS Output Charge td(on) Turn On Delay Time tr Rise Time td(off) Turn Off Delay Time tf Fall Time VD1D2 = –10V, ID1D2 = –1A VD1D2 = –9.5V, VGS = 0V VD1D2 = –10V, VGS = –4.5V, ID1D2 = –1A, RG = 30Ω 0.6 nC 0.5 nC 0.2 nC 2.2 nC 7.8 ns 6.7 ns 45 ns 26 ns Diode Characteristics VSD Diode Forward Voltage ID1D2 = –1A, VGS = 0V 0.75 Qrr Reverse Recovery Charge Vdd = –9.5V, IF = –1A, di/dt = 200A/μs 10.5 1 nC V trr Reverse Recovery Time Vdd = –9.5V, IF = –1A, di/dt = 200A/μs 23 ns THERMAL CHARACTERISTICS (TA = 25°C unless otherwise stated) PARAMETER R θJA (1) (2) (3) 2 Thermal Resistance Junction to Ambient (1) Thermal Resistance Junction to Ambient (2) (3) (2) MIN TYP MAX UNIT 200 °C/W 94 °C/W Device mounted on FR4 material with Minimum Cu mounting area. Measured with both devices biased in a parallel condition. Device mounted on FR4 material with 1-inch2 of Cu (2oz). Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): CSD75204W15 CSD75204W15 www.ti.com.............................................................................................................................................................................................. SLPS221 – OCTOBER 2009 Max RθJA = 94°C/W when mounted on 1 inch2 (6.45 cm2) of 2-oz. (0.071-mm thick) Cu. G1 S G2 D2 D1 Max RθJA = 200°C/W when mounted on minimum pad area of 2-oz. (0.071-mm thick) Cu. G1 S G2 D2 D1 M0169-01 M0170-01 TYPICAL MOSFET CHARACTERISTICS Graphs are Per MOSFET at TA = 25°C, unless stated otherwise. Drain to Drain measurements are done with both MOSFETs in series (common source configuration). ZθJA − Normalized Thermal Impedance 10 1 0.5 0.3 0.1 0.1 0.05 Duty Cycle = t1/t2 0.02 0.01 0.01 P t1 Single Pulse t2 0.001 Typical RqJA = 161oC/W (min Cu) TJ = P x ZqJA x RqJA 0.0001 0.0001 0.001 0.01 0.1 1 10 100 t P − Pulse Duration − s 1k G012 Figure 1. Transient Thermal Impedance Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): CSD75204W15 3 CSD75204W15 SLPS221 – OCTOBER 2009.............................................................................................................................................................................................. www.ti.com TYPICAL MOSFET CHARACTERISTICS (continued) Graphs are Per MOSFET at TA = 25°C, unless stated otherwise. Drain to Drain measurements are done with both MOSFETs in series (common source configuration). 5.0 −ID1D2 − Drain to Drain Current − A −ID1D2 − Drain to Drain Current − A 5.0 4.5 4.0 VGS = −1.8V VGS = −2V 3.5 3.0 2.5 2.0 VGS = −1.5V VGS = −2.5V 1.5 1.0 VGS = −4.5V 0.5 0.0 0.0 0.5 1.0 1.5 2.0 2.5 −VD1D2 − Drain to Drain Voltage − V VD1D2 = −5V 4.5 4.0 3.5 TJ = 125°C 3.0 2.5 2.0 TJ = 25°C 1.5 1.0 TJ = −55°C 0.5 0.0 0.50 3.0 1.50 1.75 G002 400 ID1D2 = −1A VD1D2 = −10V f = 1MHz VGS = 0V 350 C − Capacitance − pF 5 4 3 2 1 300 250 COSS = CDS + CGD CISS = CGD + CGS 200 150 CRSS = CGD 100 50 0 0.0 0 0.5 1.0 1.5 2.0 2.5 Qg − Gate Charge − nC 3.0 0 5 RD1D2(on) − On-State Resistance − mΩ ID1D2 = −250µA 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 −75 −25 25 15 20 G004 Figure 5. Capacitance 1.0 0.9 10 −VD1D2 − Drain to Drain Voltage − V G003 Figure 4. Gate Charge −VGS(th) − Threshold Voltage − V 1.25 Figure 3. Transfer Characteristics 6 75 125 TJ − Junction Temperature − °C Figure 6. Threshold Voltage vs. Temperature 4 1.00 −VGS − Gate to Source Voltage − V G001 Figure 2. Saturation Characteristics −VGS − Gate to Source Voltage − V 0.75 175 300 ID1D2 = −1A 250 200 TJ = 125°C TJ = 25°C 150 100 50 0 0 1 2 3 4 −VGS − Gate to Source Voltage − V G005 5 6 G006 Figure 7. On-State Resistance vs. Gate to Source Voltage Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): CSD75204W15 CSD75204W15 www.ti.com.............................................................................................................................................................................................. SLPS221 – OCTOBER 2009 TYPICAL MOSFET CHARACTERISTICS (continued) Graphs are Per MOSFET at TA = 25°C, unless stated otherwise. Drain to Drain measurements are done with both MOSFETs in series (common source configuration). 10 ID1D2 = −1A VGS = −4.5V 1.4 −ISD − Source to Drain Current − A Normalized On-State Resistance 1.6 1.2 1.0 0.8 0.6 0.4 0.2 0.0 −75 TJ = 125°C 1 0.1 TJ = 25°C 0.01 0.001 0.0001 −25 25 75 125 TJ − Case Temperature − °C 175 0.0 0.8 1.0 1.2 1.4 G008 4.5 −ID1D2 − Drain to Drain Current − A −ID1D2 − Drain to Drain Current − A 0.6 Figure 9. Typical Diode Forward Voltage 100 10 1ms 1 10ms 0.01 0.1 0.4 −VSD − Source to Drain Voltage − V G007 Figure 8. Normalized On-State Resistance vs. Temperature 0.1 0.2 Area Limited by RD1D2(on) 100ms Single Pulse Typical RqJA = 161oC/W (min Cu) 1 DC 10 100 −VD1D2 − Drain to Drain Voltage − V Figure 10. Maximum Safe Operating Area 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 −50 −25 0 25 50 75 100 125 150 175 TJ − Junction Temperature − °C G009 G011 Figure 11. Maximum Drain Current vs. Temperature Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): CSD75204W15 5 CSD75204W15 SLPS221 – OCTOBER 2009.............................................................................................................................................................................................. www.ti.com MECHANICAL DATA CSD75202W15 Package Dimensions Solder Ball Ø 0.31 ±0.075 Pin 1 Mark 1 2 3 2 3 1 A B 1.50 B 1.00 +0.00 –0.08 0.50 A C C 1.50 +0.00 –0.08 0.62 Max Top View 0.50 Bottom View 0.04 0.62 Max 0.35 ±0.10 Side View Seating Plate Front View M0171-01 NOTE: All dimensions are in mm (unless otherwise specified) Pinout POSITION 6 DESIGNATION A1 Gate1 A2, A3, B3 Drain1 C1 Gate2 C2, C3, B2 Drain2 B1 Source Sense Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): CSD75204W15 CSD75204W15 www.ti.com.............................................................................................................................................................................................. SLPS221 – OCTOBER 2009 Land Pattern Recommendation Ø 0.25 1 2 3 1.00 0.50 A B C 0.50 M0172-01 NOTE: All dimensions are in mm (unless otherwise specified) Tape and Reel Information 4.00 ±0.10 Ø 1.50 ±0.10 4.00 ±0.10 Ø 0.50 ±0.05 0.86 ±0.05 1.60 ±0.05 5° Max 3.50 ±0.05 8.00 +0.30 –0.10 1.75 ±0.10 2.00 ±0.05 0.254 ±0.02 1.60 ±0.05 5° Max M0173-01 NOTE: All dimensions are in mm (unless otherwise specified) Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): CSD75204W15 7 CSD75204W15 SLPS221 – OCTOBER 2009.............................................................................................................................................................................................. www.ti.com Package Marking Information Location 1st Line Product Code = NNNNN, First 5 digits after CSD (Fixed Text) NNNNN XXXXX 2nd Line XXXXX = Last 5 digits of lot number (Variable Text) Pin 1 Identifier M0174-01 8 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): CSD75204W15 PACKAGE OPTION ADDENDUM www.ti.com 11-Nov-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing CSD75204W15 ACTIVE DSBGA YZF Pins Package Eco Plan (2) Qty 9 3000 TBD Lead/Ball Finish Call TI MSL Peak Temp (3) Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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