Achieving a Common Chassis Worldwide Y, C, and Synchronizing Signal Processing ICs CXA2060AS CXA2061S Sony provides an extensive lineup of Y, C, and synchronizing signal processing ICs (YCD). These ICs take advantage of earlier TV ICs and in addition adopt new technologies to incorporate even more peripheral components and functionality in the same chip. The CXA2060AS supports NTSC, PAL (including PAL-M and PAL-N), and SECAM, whereas the CXA2061S is a special-purpose NTSC YCD chip. ■ ■ ■ ■ ■ ■ Reduced peripheral components count On-chip 1H delay line On-chip SECAM decoder On-chip video switch Three crystal oscillator pin sets for PAL-M and PAL-N support The CXA2060AS and CXA2061S are pin compatible. Thus the pin compatible CXA2060AS and CXA2061S support all TV broadcast regions and can achieve a common chassis worldwide. Built-in 1H Delay Line and SECAM Decoder Worldwide Horizontal Deployment The CXA2060AS is a single-chip Y,C, and synchronizing signal processing IC (YCD) that includes both a 1H delay line and a SECAM decoder on chip, and the CXA2061S is a special-purpose NTSC YCD. While it goes without saying that these chips are pin compatible, their I2C control registers are also identical, making them software compatible as well. These two products were designed to allow a common chassis to be used in all TV broadcast regions. Figure 1 shows the block diagram of the CXA2060AS. The CXA2060AS includes an on-chip 1H delay line and an on-chip SECAM decoder. While earlier products such as the CXA2000Q required an external 1H delay line for PAL and an external SECAM decoder for SECAM, by including these circuits on chip, the CXA2060AS allows the same circuit to provide the different types of signal processing required by NTSC, PAL, and SECAM. This allows the same chassis to be used for all reception areas, including NTSC-only areas, PAL/SECAM areas, and NTSC/PAL-M/PAL-N areas. Reduced Peripheral Components Count V O I C We are finally seeing the debut of single-chip support for multiformat systems! We performed extensive field testing in developing this IC, looking for signals that are difficult to receive in all corners of the world. As a result, this IC achieves the best SECAM discrimination performance of the century! Sony’s engineers strongly recommend that you try this IC. E Figure 2 presents a sample application circuit. In addition to the components used in this system, a video switch, a 1H delay line, and a SECAM decoder would be required to construct the same system using earlier products. The CXA2060AS includes these devices on chip. (The CXA2061S only includes the video switch on chip.) Since a high-performance sync separator system for the input signal is fully included on chip, no separate sync separator circuit input signal is required. Additionally, the sample-and-hold capacitor for the autocutoff circuit (AKB) is built in, and capacitors and an oscillator element are not required for the H/V oscillator. Thus this single chip can completely support all aspects of a color system. Vertical Deployment from the Low End to the High End Since these chips also provide Y and color difference signal input/output, a feature block can be added. Since an fsc output is provided, a digital comb filter can be used. Thus these chips support flexible deployment in higher grade television systems. The CXA2060AS and the CXA2061S not only aim for extensive and complete television functionality, but also promise the achievement of a common chassis worldwide. Bell Filter <BELL F0> LIM Amp. DPIC <DPIC> <AGING> SECAM VCO CAL by 4.43MHz PLL SECAM FM Demod. Clamp DC TRAN <DC TRAN> Filter Alignment CAL. by fxc ACC Amp. (SECAM ACC Det.) Y/C Mix. RGB Clamp VPROT <<VNG>> VM Amp. (OFF YS/YM) Chroma Chroma SW ATT C1IN 2 Y SW Count Down COMB YIN 9 MON OUT 6 Monitor SW V Sync Sep. <VSS> H Sync Sep. <HSS> <HMASK> <<RF LEVEL>> (Video SW) <VIDEO SEL> <S SEL> AFC <AFC GAIN> <FH HIGH> <<HLOCK>> <<HCENT>> HSAW Gen. <HOSC> VSAW Gen. (50/60) VTIM <VTIM SEL> Phase Det. <H POSITION> <AFC BOW> <AFC ANGLE> HPROT <<HNG>> H TIM Gen. <H BLK> <LEFT HBLK> <RIGHT HBLK> 20 17 5 18 HP/HPROT COMB CIN 7 Y SW <*1> YS2/YM VD SAW Func. <VON> <S CORRECTION> <V SIZE> <V LINEARITY> <V POSITION> <EHT COMP> <ASPECT> <SCROLL> <UPPER VLIN> <LOWER VLIN> <V ZOOM> <V UNDER SCAN> VTIM CVBS1/Y1IN 4 Line Counter V TIM Gen. <FIELD FREQ> <V UNDER SCAN> <CD MODE> <<FIELD ID>> <INTERLACE> <<NO VSYNC>> I2C bus Decoder Status I/F <<*2>> DAC <*1> Wide Saw Func. SCP CVBS2/Y2IN 41 Sharpness DL Sharpness Amp. <SHARPNESS> <SHP F0> <PRE/OVER> AFCFIL TV/C2IN 43 DL PAL/NTSC 300 ± 100ns SECAM 600 ± 200ns <Y DELAY> Trap PAL : 4.43MHz NTSC : 3.58MHz SECAM : 4.2 + 4.43MHz <TRAP OFF> AKB <<IKR>> EW Parabola Func. <H SIZE> <TRAPEZIUM> <PIN AMP> <EW DC> <CORNERPIN> <HD W> IREF 1µ CVBS/S Input 1 ABL Input 10k 0.1µ XTAL1 48 2 C1 IN XTAL2 47 3 ABL IN 0.1µ 5 VTIM Glass Comb Filter 0.1µ 1µ V Parabola Output V Drive Output 10µ 1k V Protection Input SCP Output Flyback Pulse Input X-ray Protection Input H Drive Output 1µ 1µ 2.2k 4700p Vth≈5V 12k 0.1µ 1µ EB-Y IN 39 11 EW ER-Y IN 38 12 I REF 4.7µ 1µ CVBS from Tuner Input CVBS/S 2 Input GND2 40 10 GND1 EY IN 37 13 VD+ YUV SW 36 14 VD– SDA 35 15 VM OUT/VPROT SCL 34 16 REG VCC1 33 17 SCP R2 IN 32 18 HP/PROTECT G2 IN 31 19 HD B2 IN 30 20 AFC FIL 10k 0.22µ 220p ABL FIL 42 CVBS2/Y2 IN 41 9 COMB Y IN 10k VM Output TV/C2 IN 43 7 COMB C IN 8 Y CLAMP 18p VCC2 44 6 MON.OUT Monitor Output 18p APC FIL 45 0.01µ 0.01µ External YUV Input 0.01µ 2 I C 47µ 0.1µ VCC + 9V 0.01µ 0.01µ 0.01µ External RGB Input 2 (for OSD/TEXT) YS2/YM 29 21 IK IN R1 IN 28 22 R OUT G1 IN 27 23 G OUT B1 IN 26 24 B OUT YS1 25 0.01µ 0.01µ 0.01µ External RGB Input 1 (for SCART) ■ Figure 2 CXA2060AS/CXA2061S Application Circuit Example 23 GOUT 22 ROUT 35 SDA 34 SCL 14 VDN 13 VDP 11 EW 19 10 12 16 33 *1: Including all control signals enclosed in single angle brackets ( <...> ). *2: Including all status signals enclosed in double angle brackets ( <<...>> ). 18p XTAL3 46 4 CVBS1/Y1 IN V Timing Output C Board 1 APED 24 BOUT REG ■ Figure 1 CXA2060AS Block Diagram 0.01µ 21 IKIN HD Gen. VCC1 BPF PAL: 4.43MHz NTSC: 3.58MHz <C BPF> Color Amp. <COLOR> <C OFF> Axis <AXIS PAL> <AXIS NTSC> 1H Delay Line ABL/Peak ABL <ABL MODE> <ABL VTH> REG Chroma Amp. Line BLK Deemphasis 3 ABLIN Clamp RGB 1/2 IREF Color System Discriminator <XTAL> <ID LEVEL> <COL SYSTEM> <COL LOOP> <<KILLER ID OFF>> <NO COLOR> <<PAL>> <ID STOP> <<SECAM>> <ID START> <<XTAL ID>> Killer <KILLER OFF> GND1 SECAM 42 ABLFIL YSI SW <RGB SEL> YM SW YS2 SW Dynamic Color <DYNAMIC C> Picture Amp. <PICTURE> Gamma Amp. <GAMMA> Clamp Bright Cont. <BRIGHT> Drive Amp. <R/G/B DRIVE> Cutoff Cont. <R/G/B CUTOFF> R/G/B BLK <PON> <R/G/B ON> ACC Det. EYUV Clamp YUV SW <Y SEL> YUVOUT <YUV OUT> SW NTSC, PAL/ SECAM PAL/NTSC PAL/NTSC Demod. 32 31 30 29 HD CVCO FSC OUT 4.433619MHz <FSC SW> 3.579545MHz 3.575611MHz 3.582056MHz APC <HUE> B2IN (B-YOUT) EBYIN 39 38 37 36 28 27 26 25 G2IN (R-YOUT) VMOUT/VPROT 15 R2IN (YOUT) APED 1 YSI Y CLAMP 8 B1IN GND2 40 G1IN VCC2 44 R1IN XTAL3 (FSC OUT) 46 YUVSW XTAL2 47 EYIN XTAL1 48 ERYIN APCFIL 45 PAL/SECAM/NTSC: XTAL1: 4.43361875MHz XTAL2: 3.579545MHz XTAL3: Open or FSC Output PAL-M/NTSC/PAL-N: XTAL1: 3.57561149MHz XTAL2: 3.579545MHz XTAL3: 3.58205625MHz Note: In the CXA2061S, Pins 46 and 48 are unused and must be left open.