Sony CXD3057R Cd digital signal processor with built - in rf amplifier and digital servo, digital high - bass boost Datasheet

CXD3057R
CD Digital Signal Processor with Built-in RF Amplifier and Digital Servo + Digital High & Bass Boost
Description
The CXD3057R is a digital signal processor LSI for CD
players. This LSI incorporates a RF amplifier and digital servo,
high & bass boost, 1-bit DAC and analog low-pass filter.
120 pin LQFP (Plastic)
Features
• All digital signal processing during playback is performed with
a single chip
• Highly integrated mounting possible due to a built-in RF
amplifier
RF Block
• Supports 4× speed playback CD
• RF system equalizer
• Supports pickup built-in RF summing amplifier
• Gain level switch
• TE balance adjustment function
Digital Signal Processor (DSP) Block
• Supports CAV (Constant Angular Velocity) playback
• Frame jitter free
• 0.5× to 4× speed continuous playback possible
• Allows relative rotational velocity readout
• Supports variable pitch playback
• The bit clock, which strobes the EFM signal, is generated by
the digital PLL.
• EFM data demodulation
• Enhanced EFM frame sync signal protection
• Refined super strategy-based powerful error correction
C1: double correction, C2: quadruple correction
Supported during 4× speed playback
• Noise reduction during track jumps
• Auto zero-cross mute
• Subcode demodulation and subcode-Q data error detection
• Digital spindle servo
• 16-bit traverse counter
• Asymmetry correction circuit
• CPU interface on serial bus
• Error correction monitor signal, etc. output from CPU
interface
• Servo auto sequencer
• Fine search performs track jumps with high accuracy
• Digital audio interface outputs
• Digital level meter, peak meter
• Bilingual compatible
• VCO control mode
• CD TEXT data demodulation
Digital Servo (DSSP) Block
• Microcomputer software-based flexible servo control
• Offset cancel function for servo error signal
• Auto gain control function for servo loop
• E:F balance, focus bias adjustment functions
• Surf jump function supporting micro two-axis
• Tracking filter: 6 stages,
Focus filter: 5 stages
• Digital dynamics (compressor)
Volume increased by +5dB at low level
• 8× oversampling digital filter
(attenuation: 61dB, ripple within band: ±0.0075dB)
• Digital signal output possible after boost
• Serial data format selectable from (output)
20 bits/18 bits/16 bits (rearward truncation, MSB first)
• Digital attenuation: –∞, –60 to +6dB, 2048 steps (linear)
• Soft mute
• Digital de-emphasis
Applications
CD players
Structure
Silicon gate CMOS IC
Absolute Maximum
• Supply voltage 1
• Input voltage 1
• Output voltage 1
• Supply voltage 2
•
•
•
•
Ratings (Ta = 25°C)
VDD, XVDD
VSS – 0.5 to +3.5
V
VSS – 0.3 to VDD + 0.3 V
V I1
VSS – 0.3 to VDD + 0.3 V
VO1
IOVDD0 to 2, AVDD0 to 5
V
IOVSS – 0.5 to +4.5
Input voltage 2
V I2
IOVSS – 0.3 to IOVDD + 0.3 V
Output voltage 2
VO2
IOVSS – 0.3 to IOVDD + 0.3 V
Storage temperature
Tstg
–55 to +150
°C
Supply voltage difference
IOVSS, AVSS, XVSS – VSS
–0.3 to +0.3
V
XVDD – VDD
–0.3 to +0.3
V
IOVDD, AVDD, XVDD – VDD
–0.3 to +0.3
V
(IOVDD, AVDD, XVDD < 2.3V)
Recommended Operating Conditions
• Supply voltage 1
VDD, XVDD
2.5 ± 0.2
• Supply voltage 2
IOVDD0 to 2, AVDD0 to 5
3.3 ± 0.3
• Operating temperature
Topr
–40 to +85
Digital Filter, DAC and Analog Low-pass Filter Blocks
• Digital dynamic bass boost and high boost
Bass Boost: 4th-order IIR 24dB/Oct
+10dB/+14dB/+18dB/+22dB
High Boost: Second-order IIR 12dB/Oct
+4dB/+6dB/+8dB/+10dB
• Independent turnover frequency selection possible
Bass Boost: 125Hz/160Hz/200Hz
High Boost: 5kHz/7kHz
I/O Pin Capacitance
• Input capacitance CI
• Output capacitance CO
• I/O capacitance
CI/O
Note) Measurement conditions
V
V
°C
7 (Max.)
7 (Max.)
7 (Max.)
VDD = VI = 0V
fM = 1MHz
pF
pF
pF
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E04250
CXD3057R
SERVO
Block
MIRR
DFCT
FOK
SYSM
SQSO
SQCK
SBSO
EXCK
DATA
XLAT
CLOK
SENS
SCOR
C2PO
WDCK
EMPH
WFCK
XUGF
GFS
SCLK
ATSK
SSTP
COUT
Block Diagram
CPU Interface
SERVO
Interface
Bass Boost Block
LMUT
MIRR
DFCT
FOK
RMUT
LPF
LOCK
MDP
LPF
DAC
SFDR
SRDR
AOUT2
VREFR
VREL
AOUT1
EMPHI
TFDR
PWM
Generator
TRDR
LRCKI
PCMDI
FFDR
BCKI
FRDR
XTACN
SERVO
DSP
XTSL
CD Signal
Processor
Block
TEI
A/D
Converter
FEI
Clock
Generator
XTAI
XTAO
VCTL
Servo
Auto
Sequencer
VPCO
Digital
OUT
Digital
CLV
DOUT
BCK
Selector
D/A
Interface
TEO
PCMD
LRCK
TE
E
Error
Corrector
F
32K
RAM
XRST
TES1
FEO
FE
TEST
EFM
Demodulator
AVDD0 to 5
Sub Code
Processor
A
B
AVSS0 to 5
IOVDD0 to 2
SUM
C
RFamp Block
IOVSS0 to 2
Asymmetry
Corrector
D
VC
Digital
PLL
DC/DC
Converter
VSS
–2–
DDCR
DDVRSEN
DDVROUT
XPCK
PCO
FILI
FIFO
CLTV
ASYO
RFACO
ASYI
AMP
BIAS
EQ
RFACI
ATT
RFC
AC_SUM
RFDCO
LD
PD
APC
EQ_IN
VC
PDSENS
VDD
CXD3057R
PCMDI
LRCKI
LRCK
VSS
PCMD
BCK
VDD
EMPH
EMPHI
IOVDD2
DOUT
TEST
IOVSS2
TES1
NC
XVSS
XTAO
XTAI
AVDD1
XVDD
AOUT1
VREFL
AVSS1
AVSS2
VREFR
AOUT2
AVDD2
IOVDD0
NC
RMUT
Pin Configuration
90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
LMUT 91
60 BCKI
NC 92
59 NC
XTSL 93
58 DDCR
IOVSS0 94
57 AVSS5
XTACN 95
56 DDVRSEN
SQSO 96
55 DDVROUT
SQCK 97
54 AVDD5
SBSO 98
53 PCO
EXCK 99
52 FILI
XRST 100
51 FILO
SYSM 101
50 CLTV
DATA 102
49 AVSS3
103
48 VCTL
XLAT 104
47 VPCO
CLOK 105
46 ASYO
VSS
VDD 106
45 ASYI
SENS 107
44 BIAS
SCLK 108
43 AVDD3
ATSK 109
42 RFACI
WFCK 110
41 RFACO
XUGF 111
40 AVSS4
XPCK 112
39 RFC
GFS 113
38 NC
C2PO 114
37 PD
SCOR 115
36 LD
VDD 116
35 EQ_IN
C4M 117
34 AC_SUM
WDCK 118
33 PDSENS
COUT 119
32 RFDCO
NC 120
NC
D
C
B
A
SFDR
VC
IOVSS1
FEO
SSTP
FEI
MDP
TEO
LOCK
TEI
VSS
F
FOK
E
MIRR
–3–
NC
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
AVSS0
8
AVDD0
7
FRDR
6
IOVDD1
5
FFDR
4
TRDR
3
TFDR
2
SRDR
1
DFCT
31 AVDD4
CXD3057R
Pin Description
Power
supply
Pin
No.
Symbol
I/O
Description
1
MIRR
I/O
1, 0
Mirror signal input/output.
2
DFCT
I/O
1, 0
Defect signal input/output.
3
FOK
I/O
1, 0
Focus OK signal input/output.
4
VSS
—
—
5
LOCK
I/O
1, 0
6
MDP
O 1, Z, 0 Spindle motor servo control output.
7
SSTP
I
8
IOVSS1
—
—
9
SFDR
O
1, 0
Sled drive output.
10
SRDR
O
1, 0
Sled drive output.
11
TFDR
O
1, 0
Tracking drive output.
12
TRDR
O
1, 0
Tracking drive output.
13
FFDR
O
1, 0
Focus drive output.
14
FRDR
O
1, 0
Focus drive output.
15
IOVDD1
—
—
I/O digital power supply.
A/D
3.3V
16
AVDD0
—
—
Analog power supply.
17
AVSS0
—
—
Analog GND.
—
18
NC
—
—
19
E
I
E signal input.
20
F
I
F signal input.
21
TEI
I
Tracking error signal input to DSSP block.
22
TEO
O
Tracking error signal output from RF amplifier block.
23
FEI
I
Focus error signal input to DSSP block.
24
FEO
O
Focus error signal output from RF amplifier block.
25
VC
I/O
Center voltage output from RF amplifier block.
Center voltage input to DSSP block by command switch.
26
A
I
A signal input.
27
B
I
B signal input.
28
C
I
C signal input.
29
D
I
D signal input.
30
NC
—
—
31
AVDD4
—
—
32
RFDCO
I/O
33
PDSENS
I
34
AC_SUM O Analog RFAC summing amplifier output.
Digital
I/O = 3.3V
Internal =
2.5V
RFamp
3.3V
Internal digital GND.
GFS is sampled at 460Hz; when GFS is high, this pin outputs a high
signal. If GFS is low eight consecutive samples, this pin outputs low.
Or this pin inputs when LKIN = "1".
Disk innermost detection signal input.
I/O digital GND.
Analog power supply.
RFDC signal output.
RFDC signal input to DSSP block by command switch.
Reference voltage pin for PD.
–4–
CXD3057R
Power
supply
RFamp
3.3V
ASYM
3.3V
DC/DC
3.3V
—
Digital
I/O = 3.3V
Internal =
2.5V
Pin
No.
Symbol
35
EQ_IN
I
Equalizer circuit input.
36
LD
O
APC amplifier output.
37
PD
I
APC amplifier input.
38
NC
—
39
RFC
40
AVSS4
—
41
RFACO
O
RFAC signal output.
42
RFACI
I
RFAC signal input or EFM signal input.
43
AVDD3
—
44
BIAS
I
Asymmetry circuit constant current input.
45
ASYI
I
Asymmetry comparator voltage input.
46
ASYO
O
47
VPCO
O 1, Z, 0 Wide-band EFM PLL charge pump output.
48
VCTL
I
49
AVSS3
—
50
CLTV
I
51
FILO
O Analog Master PLL (slave = digital PLL) filter output.
52
FILI
I
53
PCO
O 1, Z, 0 Master PLL charge pump output.
54
AVDD5
—
55
DDVROUT
O
DC/DC converter output.
Leave open when not using.
56
DDVRSEN
I
DC/DC converter output voltage monitor pin.
Connect to analog power supply when not using.
57
AVSS5
—
58
DDCR
I
59
NC
60
BCKI
I
D/A interface bit clock input.
61
PCMDI
I
D/A interface serial data input.
(2's COMP, MSB first)
62
LRCKl
I
D/A interface LR clock input.
63
LRCK
O
1, 0
64
VSS
—
—
65
PCMD
O
1, 0
D/A interface serial data output.
(2's COMP, MSB first)
66
BCK
O
1, 0
D/A interface bit clock output.
67
VDD
—
—
Internal digital power supply.
68
EMPH
O
1, 0
69
EMPHI
I
I/O
—
I
—
Description
Equalizer cut-off frequency adjustment pin.
—
—
1, 0
Analog GND.
Analog power supply.
EFM full-swing output. (Low = VSS, High = VDD)
Wide-band EFM PLL VCO2 control voltage input.
—
Analog GND.
Multiplier VCO1 control voltage input.
Master PLL filter input.
—
—
Analog power supply.
Analog GND.
Test pin. Normally GND.
—
D/A interface LR clock output. f = Fs
Internal digital GND.
High when the playback disc has emphasis, low it has not.
High when de-emphasis is ON, low when input OFF.
–5–
CXD3057R
Power
supply
Digital
I/O = 3.3V
Internal =
2.5V
—
X'tal
2.5V
Lch
3.3V
Rch
3.3V
—
Digital
I/O = 3.3V
Internal =
2.5V
Pin
No.
Symbol
70
IOVDD2
—
—
71
DOUT
O
1, 0
72
TEST
I
Test pin. Normally GND.
73
TES1
I
Test pin. Normally GND.
74
IOVss2
—
—
75
NC
—
—
76
XVSS
—
—
77
XTAO
O
Crystal oscillation circuit output.
78
XTAI
I
Crystal oscillation circuit input.
79
XVDD
—
—
Master clock power supply.
80
AVDD1
—
—
Analog power supply.
81
AOUT1
O
Lch analog output.
82
VREFL
O
Lch reference voltage.
83
AVSS1
—
—
Analog GND.
84
AVSS2
—
—
Analog GND.
85
VREFR
O
Rch reference voltage.
86
AOUT2
O
Rch analog output.
87
AVDD2
—
—
88
NC
—
—
89
IOVDD0
—
—
90
RMUT
O
1, 0
Rch "0" detection flag.
91
LMUT
O
1, 0
Lch "0" detection flag.
92
NC
—
—
93
XTSL
94
IOVSS0
—
95
XTACN
I
96
SQSO
O
97
SQCK
I
98
SBSO
O
99
EXCK
I
SBSO readout clock input.
100 XRST
I
System reset. Reset when low.
101 SYSM
I
Mute input. Muted when high.
102 DATA
I
Serial data input from CPU.
103 VSS
104 XLAT
I/O
I
I/O digital power supply.
Digital Out output.
I/O digital GND.
Master clock GND.
Analog power supply.
I/O digital power supply.
Crystal selection input.
Low when the crystal is 16.9344MHz;
high when the crystal is 33.8688MHz.
I
—
Description
—
I/O digital GND.
Oscillation circuit control.
Self-oscillation when high, oscillation stop when low.
1, 0
Subcode Q 80-bit and PCM peak and level data output.
CD TEXT data output.
SQSO readout clock input.
1, 0
—
Subcode P to W serial output.
Internal digital GND.
Latch input from CPU. The serial data is latched at the falling edge.
–6–
CXD3057R
Power
supply
Pin
No.
Symbol
105 CLOK
I/O
I
Description
Serial data transfer clock input from CPU.
106 VDD
—
—
107 SENS
O
1, 0
108 SCLK
I
109 ATSK
I/O
1, 0
Anti-shock input/output.
110 WFCK
O
1, 0
WFCK output.
111 XUGF
O
1, 0
XUGF output.
Output MNT0, RFCK, SOUT by command switch.
112 XPCK
O
1, 0
XPCK output.
Output MNT1, SOCK by command switch.
O
1, 0
GFS output.
Output MNT2, XROF, XOLT by command switch.
O
1, 0
C2PO output.
Output MNT3, GTOP by command switch.
115 SCOR
O
1, 0
High output when the subcode sync, S0 or S1, is detected.
116 VDD
—
—
117 C4M
O
1, 0
4.2336MHz output.
1/4 frequency-division output of the V16M in CAV-W mode and
variable pitch mode.
118 WDCK
O
1, 0
Word clock output. f = 2Fs.
GRSCOR output by command switch.
119 COUT
I/O
1, 0
Track number count signal input/output.
120 NC
—
—
Digital
I/O = 3.3V 113 GFS
Internal =
2.5V
114 C2PO
Internal digital power supply.
SENS output to CPU.
SENS serial data readout clock input.
Internal digital power supply.
Notes)
• PCMD is a MSB first, two's complement output.
• GTOP is used to monitor the frame sync protection status. (High: sync protection window released.)
• XUGF is the frame sync obtained from the EFM signal, and is negative pulse. It is the signal before sync
protection.
• XPCK is the inverse of the EFM PLL clock. The PLL is designed so that the falling edge and the EFM
signal transition point coincide.
• The GFS signal goes high when the frame sync and the insertion protection timing match.
• RFCK is derived from the crystal accuracy, and has a cycle of 136µs.
• C2PO represents the data error status.
• XROF is generated when the 32K RAM exceeds the ±28 frame jitter margin.
• C4M is a 4.2336MHz output that changes in CAV-W mode and variable pitch mode.
• FSTO is the 2/3 frequency-division output of the XTAI pin.
• SOUT is the serial data output inside the servo block.
• SOCK is the serial data readout clock output inside the servo block.
• XOLT is the serial data latch output inside the servo block.
–7–
CXD3057R
Monitor Pin Output Combinations
Command bit
Output data
SRO1
MTSL1
MTSL0
0
0
0
XUGF
XPCK
GFS
C2PO
0
0
1
MNT0
MNT1
MNT2
MNT3
0
1
0
RFCK
XPCK
XROF
GTOP
0
1
1
C4M
GSTO
GFS
C2PO
1
0
0
SOUT
SOCK
XOLT
C2PO
Reset Timing when Power on
Power on with XRST pin low.
Set XRST pin high after holding it low 100ns or more to cancel reset.
–8–
CXD3057R
RF Block Pin Equivalent Circuit
Pin
No.
19
Symbol
E
I/O
I
Equivalent circuit
Description
19
VC
Tracking error amplifier input.
20
F
I
20
VC
21
TEI
I
22
TEO
O
Tracking error signal input to DSSP
block.
21
1pF
Tracking error amplifier output.
22
23
FEI
I
24
FEO
O
Focus error signal input to DSSP
block.
23
1pF
Focus error amplifier output.
24
25
VC
I/O
(AVDD4 – AVSS4)/2 voltage output.
25
–9–
CXD3057R
Pin
No.
26
Symbol
A
I/O
Equivalent circuit
Description
I
15kΩ
26
27
B
I
27
RF summing amplifier and focus
error amplifier input.
30kΩ
28
C
I
28
30kΩ
29
29
D
I
30
NC
—
—
31
AVDD4
—
—
—
Analog power supply.
10kΩ
32
RFDCO
I/O
RFDC amplifier output.
0.5pF
100Ω
32
33
PDSENS
I
34
AC_SUM
O
10kΩ
59kΩ
33
34
– 10 –
APC amplifier reference voltage
(GND signal) input.
RFAC summing amplifier output.
CXD3057R
Pin
No.
Symbol
I/O
Equivalent circuit
Description
35
4kΩ
35
EQ_IN
I
Equalizer circuit input.
4kΩ
4kΩ
4kΩ
VC
36
LD
57kΩ
O
APC amplifier output.
10kΩ
500Ω
36
37
PD
I
38
NC
—
1kΩ
APC amplifier input.
37
—
—
39
39
RFC
40
AVSS4
—
41
RFACO
O
Equalizer cut-off frequency
adjustment.
I
—
Analog GND.
25Ω
VC
41
– 11 –
RFAC amplifier output.
CXD3057R
Electrical Characteristics
1. DC Characteristics
(VDD = XVDD = 2.5 ± 0.2V, IOVDD0 to 2 = AVDD0 to 5 = 3.3 ± 0.3V, VSS = XVSS = IOVSS = AVSS = 0V,
Topr = –40 to +85°C)
Item
Input
voltage (1)
Input
voltage (2)
Input
voltage (3)
Output
voltage (1)
Output
voltage (2)
Output
voltage (3)
Output
voltage (4)
Conditions
High level
input voltage
VIH (1)
Low level
input voltage
VIL (1)
High level
input voltage
VIH (2)
Low level
input voltage
VIL (2)
Hysteresis
Vt+ –
Vt–
Input voltage
VIN (3)
Min.
Typ.
Unit
Applicable
pins
V
∗1, ∗3, ∗9
0.2VDD
V
∗2
VDD
V
∗4, ∗12
V
∗5, ∗8, ∗9
V
∗6
V
∗7
V
∗11
10
µA
∗1, ∗2, ∗9
240
µA
∗3
10
µA
∗8
Max.
0.7VDD
0.2VDD
0.7VDD
Schmitt input
0.5
Analog input
VSS
High level
VOH (1)
output voltage
IOH = –2.4mA
VDD – 0.4
Low level
VOL (1)
output voltage
IOL = 4mA
High level
VOH (2)
output voltage
IOH = –1.2mA
Low level
VOL (2)
output voltage
IOL = 2mA
High level
VOH (3)
output voltage
IOH = –2.4, –4.8,
–7.2, –9.6mA
Low level
VOL (3)
output voltage
IOL = 4, 8, 12, 16mA
High level
VOH (4)
output voltage
IOH = –0.28mA
Low level
VOL (4)
output voltage
IOL = 0.36mA
0.4
VDD – 0.4
0.4
VDD – 0.4
0.4
VDD – 0.4
0.4
Input leak current
II
VIN = VSS or VDD
–10
Input leak current
(with pull-down resistor)
IIH
VIN = VDD
40
Tri-state output leak current
(when high impedance)
IOZ
VIN = VSS or VDD
–10
– 12 –
100
CXD3057R
Applicable pins
∗1 PCMDI, EMPHI, TEST, TES1, XTSL, XTACN, SYSM, DATA
∗2 BCKI, LRCKI, SQCK, EXCK, XRST, XLAT, CLOK, SCLK
∗3 SSTP
∗4 E, F, TEI, FEI, A, B, C, D, PDSENS, EQ_IN, PD, RFC, RFACI, BIAS, ASYI, VCTL, CLTV, FILI, DDVRSEN,
DDCR
∗5 SFDR, SRDR, TFDR, TRDR, FFDR, FRDR, LRCK, PCMD, BCK, EMPH, RMUT, LMUT, SQSO, SBSO,
WFCK, XUGF, XPCK, GFS, C2PO, SCOR, C4M, WDCK
∗6 ASYO
∗7 DOUT
∗8 MDP, VPCO, PCO, SENS
∗9 MIRR, DFCT, FOK, LOCK, ATSK, COUT
∗10 TEO, FEO, AC_SUM, LD, RFACO, DDVROUT, AOUT1, VREFL, VREFR, AOUT2
∗11 FILO
∗12 VC, RFDCO
– 13 –
CXD3057R
2. AC Characteristics
(1) XTAI pin
(a) When using self-oscillation
(VDD = XVDD = 2.5 ± 0.2V, IOVDD0 to 2 = AVDD0 to 5 = 3.3 ± 0.3V, VSS = XVSS = IOVSS = AVSS = 0V,
Topr = –40 to +85°C)
Item
Oscillation
frequency
Symbol
fMAX
Conditions
Min.
Typ.
Max.
XTSL = L, $AEXX1 CKSL (1, 0) = 00
16.8
16.9344
17.1
XTSL = H, $AEXX1 CKSL (1, 0) = 00
33.5
33.8688
34.2
XTSL = H, $AEXX1 CKSL (1, 0) = 01 or 10 or 11
67.1
67.7376
68.4
(b) When inputting pulses to XTAI pin
(VDD = XVDD = 2.5 ± 0.2V, IOVDD0 to 2 = AVDD0 to 5 = 3.3 ± 0.3V, VSS = XVSS = IOVSS = AVSS = 0V,
Topr = –40 to +85°C)
Item
Symbol
Min.
High level pulse
width
tWHX
Low level pulse
width
Max.
Unit
6.6
32.7
ns
tWLX
6.6
32.7
ns
Pulse cycle
tCX
14.6
59.5
ns
Input high level
VIHX
1.7
Input low level
VILX
Rise time,
fall time
tR , t F
0
Typ.
V
0.7
V
10
ns
tCX
tWLX
tWHX
VIHX
VIHX × 0.9
XTAI
VDD/2
VIHX × 0.1
VILX
tR
tF
Note) When the pulse is input to the XTAI pin, be sure to input it via the capacitor.
– 14 –
Unit
MHz
CXD3057R
(2) CLOK, DATA, XLAT, SQCK and EXCK pins
(VDD = XVDD = 2.5 ± 0.2V, IOVDD0 to 2 = AVDD0 to 5 = 3.3 ± 0.3V, VSS = XVSS = IOVSS = AVSS = 0V,
Topr = –40 to +85°C)
Symbol
Item
Min.
Typ.
Max.
Unit
16
MHz
30000
ns
Clock frequency
fCK
Clock pulse width
tWCK
Setup time
tSU
30
ns
Hold time
tH
30
ns
Delay time
tD
300
Latch pulse width
tWL
750
ns
Command transfer interval
tWCT
750
ns
EXCK frequency
fT
EXCK pulse width
tWT
SQCK frequency
fT
SQCK pulse width
tWT
COUT frequency (during input)∗
fT
COUT pulse width (during input)∗
fWT
31.3
30000
0.65
750
750
7.5
tWCK
CLOK
DATA
tWCT
tSU
tH
tD
tWL
EXCK
SQCK
COUT
tWT
tWT
1/fT
– 15 –
0.65
MHz
120000
ns
65
kHz
µs
1/fCK
XLAT
MHz
ns
∗ Only when $44 and $45 are executed.
tWCK
ns
CXD3057R
(3) SCLK pin
XLAT
tDLS
tSPW
...
SCLK
1/fSCLK
Serial Read Out Data
(SENS)
...
MSB
LSB
(VDD = XVDD = 2.5 ± 0.2V, IOVDD0 to 2 = AVDD0 to 5 = 3.3 ± 0.3V, VSS = XVSS = IOVSS = AVSS = 0V,
Topr = –40 to +85°C)
Symbol
Item
Min.
Typ.
Max.
Unit
16
MHz
SCLK frequency
fSCLK
SCLK pulse width
tSPW
31.3
ns
Delay time
tDLS
15
µs
(4) COUT, MIRR and DFCT pins
Operating frequency
(VDD = XVDD = 2.5 ± 0.2V, IOVDD0 to 2 = AVDD0 to 5 = 3.3 ± 0.3V, VSS = XVSS = IOVSS = AVSS = 0V,
Topr = –40 to +85°C)
Item
Symbol
Min.
Typ.
Max.
Unit
Conditions
COUT maximum operation frequency
fCOUT
40
kHz
∗1
MIRR maximum operation frequency
fMIRR
40
kHz
∗2
DFCT maximum operation frequency
fDFCTH
5
kHz
∗3
∗1 When using a high-speed traverse TZC
∗2
B
A
When the RF signal continuously satisfies the following conditions during the traverse.
• A = 0.11VDD to 0.23VDD
•
B
≤ 25%
A+B
∗3 During complete RF signal omission.
When settings related to DFCT signal generation are Typ.
– 16 –
CXD3057R
1-bit DAC and LPF Block Analog Characteristics
(VDD = XVDD = 2.5V, IOVDD0 to 2 = AVDD0 to 5 = 3.3V, VSS = XVSS = IOVSS = AVSS = 0V, Topr = +25°C)
Symbol
Item
Conditions
Min.
Total harmonic
distortion
THD
1kHz sine wave, 0dB data, 20kHz LPF
Signal-to-noise
ratio
S/N
1kHz sine wave, 0dB data,
AMUT OFF (Using A-weighting filter 20kHz LPF)
Typ.
Max.
0.006 0.014
90
95
Fs = 44.1kHz in all cases.
The total harmonic distortion and signal-to-noise ratio measurement circuits are shown below.
22µF
100Ω
AOUT1 (2)
Audio Analyzer
2200pF
100kΩ
VREFL (R)
1µF
LPF external circuit diagram
DATA
Rch
A
Lch
B
RF
CXD3059AR
TEST DISC
Audio Analyzer
Block diagram of analog characteristics measurement
(VDD = XVDD = 2.5V, IOVDD0 to 2 = AVDD0 to 5 = 3.3V, VSS = XVSS = IOVSS = AVSS = 0V, Topr = +25°C)
Item
Symbol
Min.
Typ.
Output voltage
VOUT
920
928
Load resistance
RL
10
VREF pin capacitance
CVREF
1
Max.
Unit
Applicable pins
∗1
mVrms
∗1
kΩ
µF
∗2
∗ Measurement is conducted for the above circuit diagrams with the sine wave output of 1kHz and 0dB.
Applicable pins
∗1 AOUT1, AOUT2
∗2 VREFL, VREFR
– 17 –
Unit
%
dB
RF Block Electrical Characteristics
(VDD = XVDD = 2.5V, IOVDD0 to 2 = AVDD0 to 5 = 3.3V, VSS = XVSS = IOVSS = AVSS = 0V, Topr = +25°C)
Bias conditions
Measurement item
Symbol
Input impedance
(A, B, C and D)
RA,B,C,D
Input impedance
(E and F)
RE,F
Input impedance
(PD)
RPD
RF block current
consumption
(on operation)
IAVD
SW
conditions
Sending
command
AC input AC input DC input
amplitude frequency voltage
DC input
current
VDD AVDD
Connect to
VC except
measurement pins.
2.5V 3.3V
$3AF100
Min.
Typ.
Max.
Unit
Pin current
A, B,
C, D
10
15
20
kΩ
Pin current
E, F
21
30
39
kΩ
Pin current
PD
10
Pin current
AVDD4
Pin current
AVDD4
MΩ
40
70
mA
1
mA
ISTB
VC
2.5V 3.3V
RF block current
consumption
(on standby)
Output voltage
VVC
±3mA
Input voltage
VPD
0
PD input voltage which
LD, PD
LD pin voltage is 1.41V
Output voltage
(on standby)
VLDstb
0
Pin voltage
LD
AVDD
– 0.2
0
Pin voltage
LD
1.89
2.14
2.39
V
APC
– 18 –
Measurement pins
Measurement
conditions
$ADF7CC00
$AD000800
2.5V 3.3V Pin voltage
VC
0.5AVDD
– 0.1
0.5AVDD
0.5AVDD
+ 0.1
V
100
150
200
mV
V
VPDT
VPD +
12mV
VPDB
VPD –
12mV
0
Pin voltage
LD
0.43
0.68
0.93
V
Input voltage
range
2.5V 3.3V
ILD
0
1mA
Pin voltage
LD
0.34
0.64
0.94
V
Output
impedance
RLD
VPD
1mA
Pin voltage
LD
1.66
1.91
2.16
V
CXD3057R
Maximum
output current
Bias conditions
Symbol
Input voltage
range
VIR-ACSUM
Output voltage
range
VOR-ACSUM
ACSUM
Measurement item
SW
conditions
Sending
command
Input conversion
VOF-ACSUM
DC offset voltage
$3AA000
Input conversion
VDF-ACSUM
DC offset
temperature drift
$3AA01C
Offset voltage
AC input AC input DC input
amplitude frequency voltage
2.5V
– 19 –
Frequency
FSUM2
characteristics 2
Measurement
conditions
Measurement pins
Min.
Pin voltage,
A+B+C+D
RFDC
Pin voltage
Pin voltage
$3AA004
$3AA018
Max.
Unit
0.5AVDD
– 0.1
0.9AVDD
+ 0.1
V
RFDC
0.47AVDD
0.65AVDD
V
RFDC
0.5AVDD
– 0.23
0.5AVDD
+ 0.23
V
RFDC
61mVp-p
VC + VAC1/2
Typ.
µV/
°C
±6
3V
Pin voltage
0.2/6MHz
RFDC
VDD AVDD
VOFFSUM
Frequency
FSUM1
characteristics 1
20 log (V6M/V0.2M)
0.7
0.9
1.1
V
–4
0
1
dB
–4
0
1
dB
3
%
RFDC
104mVp-p
(V6M/V3M) × 100
RFDC
VIR-RFDC
Pin voltage,
A+B+C+D
RFDC
0.3AVDD
– 0.1
0.7AVDD
+ 0.1
V
VOR-RFDC
Pin voltage
RFDC
0.25AVDD
0.75AVDD
V
Pin voltage
RFDC
0.3AVDD
– 0.23
0.3AVDD
+ 0.23
V
Distortion rate
DSUM
Input voltage
range
Output voltage
range
600mVp-p
Input conversion
VOF-RFDC
DC offset voltage
$3AA000
Input conversion
VDF-RFDC
DC offset
temperature drift
$3AA01C
Frequency
FRFDC1
characteristics 1
$3AA004
3MHz
Frequency
FRFDC2
characteristics 2
3V
61mVp-p
VC + VAC1/2
20 log (V6M/V0.2M)
100kHz
–4
0
1
dB
–4
0
1
dB
RFDC
104mVp-p
1.5Vp-p
µV/
°C
±6
RFDC
0.1
%
CXD3057R
DRFDC
$3AA018
VC + VAC1/2
2.5V
0.2/6MHz
Distortion rate
DC input
current
Bias conditions
FE
Measurement item
SW
conditions
Sending
command
AC input AC input DC input
amplitude frequency voltage
DC input
current
VDD AVDD
Measurement
conditions
Measurement pins
Min.
Typ.
Max.
Unit
Input voltage
range
VIR-FE
VC reference about
(B + D) and (A + C)
FE
0.375
AVDD
0.625
AVDD
V
Output voltage
range
VOR-FE
Pin voltage
FE
0.5
AVDD
– 0.5
V
Input conversion
VOF-FE
DC offset voltage
Pin voltage
FE
0.5AVDD
– 0.03
0.5AVDD
+ 0.03
V
Input conversion
VDF-FE
DC offset
temperature drift
Offset voltage
– 20 –
TE
Symbol
2.5V
VOFFFE
Pin voltage
Frequency
FFE1
characteristics 1
$3AA104
Frequency
FFE2
characteristics 2
$3AA118
FE
30mVp-p
10/
100kHz
µV/
°C
±2.8
3V
20 log (V100k/V10k)
–0.06
0
0.06
V
–1
0
1
dB
–1
0
1
dB
3
%
FE
52mVp-p
(V50k/V100k) × 100
FE
VIR-TE
VC reference about
(B + D) and (A + C)
TE
0.4AVDD
0.6AVDD
V
VOR-TE
Pin voltage
TE
0.5
AVDD
– 0.5
V
Input conversion
VOF-TE
DC offset voltage
Pin voltage
TE
0.5AVDD
– 0.03
0.5AVDD
+ 0.03
V
Distortion rate
DFE
Input voltage
range
Output voltage
range
600mVp-p
50kHz
Input conversion
VDF-TE
DC offset
temperature drift
Offset voltage
2.5V
VOFFTE
Frequency
FTE2
characteristics 2
$3AA218
45mVp-p
DTE
$3AA200
480mVp-p
TE
28mVp-p
10/
100kHz
50kHz
20 log (V100k/V10k)
(V50k/V100k) × 100
–0.075
0
0.075
V
–1
0
1
dB
–1
0
1
dB
3
%
TE
TE
CXD3057R
$3AA204
µV/
°C
±2.5
Pin voltage
Frequency
FTE1
characteristics 1
Distortion rate
3V
Bias conditions
EQ
Measurement item
Symbol
SW
conditions
Sending
command
AC input AC input DC input
amplitude frequency voltage
DC input
current
VDD AVDD
Measurement
conditions
Measurement pins
Min.
Typ.
Max.
Unit
250
mVp-p
Input voltage
range
VIR-EQ
Distortion rate 3% or
less, no DC bias
RFACO
Output voltage
range
VOR-EQ
Pin voltage
RFACO
0.5
AVDD
– 0.5
V
Input conversion
VOF-EQ
DC offset voltage
Pin voltage
RFACO
–0.25
0.25
V
Input conversion
VDF-EQ
DC offset
temperature drift
Offset voltage
2.5V
VOFFEQ
Ta = –40 to +85°C
Pin voltage
– 21 –
Frequency
FEQ1
characteristics 1
$3AA204
Frequency
FEQ2
characteristics 2
$3AA218
45mVp-p
DEQ
$3AA200
1.2Vp-p
Distortion rate
3V
RFACO
28mVp-p
10/
100kHz
360kHz
20 log (V100k/V10k)
V
±0.1
–0.5
0
0.5
V
–1
0
1
dB
–1
0
1
dB
3
%
RFACO
(V720k/V360k) × 100 RFACO
CXD3057R
CXD3057R
Notes on Operation for RFC Pin
• Set each impedance of the heavy line shown bellow 0.1Ω or less.
• Make each wiring length of L1 to L4, L1 ≤ 20mm, L2 ≤ 20mm and L3 + L4 ≤ 40mm.
• Use the bypass condenser C with capacitance led by resistance (regulator output impedance and wiring
resistance to C) or more seeing the figure bellow.
5
Regulator
4
OUT
R [Ω]
GND
R
AVS
3
2
0.1µF
1
C
L3
L2
0
0
20
40
60
80
100
C [µF]
L1
15kΩ
0.1µF
Impedance R tolerance for bypass condenser C
L4
AVSS4
RFC
AVDD4
– 22 –
CXD3057R
DC-DC Converter Characteristics
(VDD = XVDD = 2.5 ± 0.2V, IOVDD0 to 2 = AVDD0 to 5 = 3.3 ± 0.3V, VSS = XVSS = IOVSS = AVSS = 0V,
Topr = –40 to +85°C)
Item
Symbol
Conditions
Min.
Typ.
Max.
Unit
Output voltage
VO
—
2.3
2.5
2.7
V
Output current
Iope
—
—
—
100
mA
Power supply for DC-DCEQPXGTVGT
AVDD5
DDVROUT
VOUT
DDVRSEN
C2
C1
AVSS5
GND for DC-DCEQPXGTVGT
DDCR
DC-DC converter application circuit sample
Refer to Application Notes on operation.
– 23 –
CXD3057R
CPU Interface Timing
31.3nsVQ30µs
CLOK
D0
DATA
D18
D1
D19
D20
D21
D22
D23
750ns or more
XLAT
Valid
Registers
Spindle Output
n . 236 (ns) n = 0 to 31
Acceleration
MDP
Z
132kHz
7.6µs
Deceleration
Acceleration
MDP
Z
264kHz
3.8µs
Deceleration
Servo Output
MCK
(5.6448MHz)
↑
↑
↑
↑
↑
↑
↑
Output value + A
Output value – A
Output value 0
64tMCK
64tMCK
64tMCK
SLD
SFDR
AtMCK
SRDR
AtMCK
FCS/TRK
32tMCK
FFDR/
TFDR
BtMCK
32tMCK
32tMCK
32tMCK
BtMCK
FRDR/
TRDR
BtMCK
#VQKPVGIGTPWODGT
$VQKPVGIGTPWODGT
– 24 –
BtMCK
32tMCK
32tMCK
CXD3057R
DA Interface
CDDSP output selected (1×
× speed playback LRCK = 44.1kHz, BCK = 2.1168MHz)
LRCK
2
1
3
4
5
6
7
8
9
10
11
12
24
BCK
WDCK
PCMD R0
L14 L13 L12 L11 L10 L9
Lch MSB (15)
L8
L7
L6
L5
L4
L3
L2
L1
L0
Rch MSB
DAC output selected (1×
× speed playback LRCK = 44.1kHz, BCK = 2.8224MHz)
$A5EA OBIT1 = 1, OBIT0 = 1
LRCK
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
32
BCK
WDCK
PCMD R0
L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0
Rch MSB
L16 L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0
Rch MSB
L18 L17 L16 L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0
Rch MSB
Lch MSB (15)
$A5EA OBIT1 = 1, OBIT0 = 0
Lch MSB (17)
PCMD R0
$A5EA OBIT1 = 0, OBIT0 = 0
PCMD R0
Lch MSB (19)
DAC block input timing (LRCK = 44.1kHz, BCK = 2.1168MHz)
LRCKI
1
2
3
4
5
6
7
8
9
10
11
24
12
BCKI
PCMDI R0
Lch MSB (15)
L14 L13 L12 L11 L10 L9
– 25 –
L8
L7
L6
L5
L4
L3
L2
L1
L0
Rch MSB
CXD3057R
EMPH
DOUT
RMUT
Lch
Rch
Application Circuit
BCK
PCMD
LRCK
LRCKI
PCMDI
VSS
LRCK
BCK
PCMD
VDD
EMPH
EMPHI
DOUT
IOVDD2
TES1
TEST
NC
IOVSS2
XVSS
XTAI
XTAO
XVDD
AVDD1
AOUT1
AVSS1
VREFL
AVSS2
AOUT2
NC
VREFR
91 LMUT
AVDD2
LMUT
RMUT
IOVDD0
90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
BCKI 60
92 NC
NC 59
93 XTSL
SQSO
SBSO
DDCR 58
94 IOVSS0
AVSS5 57
95 XTACN
DDVRSEN 56
96 SQSO
DDVROUT 55
97 SQCK
AVDD5 54
98 SBSO
PCO 53
SQCK
99 EXCK
FILI 52
XRST
100 XRST
FILO 51
SYSM
101 SYSM
CLTV 50
DATA
102 DATA
AVSS3 49
XLAT
103 VSS
VCTL 48
CLOK
104 XLAT
VPCO 47
SENS
105 CLOK
SCLK
106 VDD
SCOR
107 SENS
BIAS 44
FOK
108 SCLK
AVDD3 43
ASYO 46
CXD3059AR
ASYI 45
109 ATSK
RFACI 42
WFCK
110 WFCK
RFACO 41
XUGF
111 XUGF
AVSS4 40
XPCK
112 XPCK
RFC 39
GFS
C2PO
113 GFS
NC 38
114 C2PO
PD 37
115 SCOR
LD 36
116 VDD
C4M
Driver circuit
EQ_IN 35
AC_SUM 34
118 WDCK
PDSENS 33
COUT
119 COUT
RFDCO 32
RFDCO
PD
NC
D
C
B
A
AVDD4 31
VC
FEO
FEI
TEO
TEI
F
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
E
SFDR
8
NC
IOVSS1
7
AVSS0
SSTP
6
AVDD0
MDP
5
FRDR
LOCK
4
FFDR
VSS
3
TRDR
FOK
2
TFDR
DFCT
1
SRDR
MIRR
IOVDD1
117 C4M
WDCK
120 NC
DDVROUT
LD
A.GND
D
B
LOCK
MIRR
DFCT
C
A
VC
F
E
FD
TD
Driver circuit
SLED
SPDL
Limit switch
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 26 –
CXD3057R
Package Outline
Unit: mm
120PIN LQFP (PLASTIC)
18.0 ± 0.2
1.7 MAX
1.4 ± 0.1
16.0 ± 0.1
90
S
61
0.1
91
S
60
B
A
120
31
1
30
0.5
b
0.1
M
S
DETAIL A
0.125 ± 0.03
0˚ to 10˚
0.6 ± 0.15
b = 0.20 ± 0.03
(0.5)
0.25
(17.0)
0.1 ± 0.05
DETAIL B
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
LQFP-120P-L01
LEAD TREATMENT
PALLADIUM PLATING
EIAJ CODE
LQFP120-P-1616
LEAD MATERIAL
COPPER ALLOY
PACKAGE MASS
0.8g
JEDEC CODE
– 27 –
Sony Corporation
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