CXG1166ER High Power 3 × 5 Antenna Switch MMIC with Integrated Control Logic Description The CXG1166ER is a high power antenna switch MMIC for PDC handsets. There are two modes which are TDMA mode and Packet mode. The CXG1166ER is suited to connect Tx/Rx/Duplexer to one of 4 antennas. This switch has on-chip logic circuit for operation with 4 CMOS inputs. The Sony Junctiongate PHEMT (JPHEMT) process is used for low insertion loss and low voltage operation. 24 pin VQFN (Plastic) Features • Low insertion loss: 0.7dB @1.44GHz • Low loss bypass mode in TDMA • High linearity: Harmonic < – 60dBc • CMOS compatible input control • Small package: 24-pin VQFN (3.3mm × 3.3mm) Applications 3 × 5 antenna switch for digital cellular such as PDC handsets Structure GaAs Junction-gate PHEMT Absolute Maximum Ratings (Ta = 25°C) • Bias voltage VDD • Control voltage • Operating temperature • Storage temperature Vctl Topr Tstg 7 5 –35 to +85 –65 to +150 V V °C °C GaAs MMICs are ESD sensitive devices. Special handling precautions are required. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E04503-PS CXG1166ER Block Diagram F13 F1 Ext Tx F15 Dup_In F14 F2 F9 F16 GND3 F3 Ant Dup_Out F4 F17 F10 F5 GND4 F6 GND1 F7 D_Ant Rx F18 F11 F8 D_Ext F12 –2– CXG1166ER Dup_In Ant CRF (100pF) 10 GND 11 Z1 GND 12 GND CRF (100pF) GND1 Tx Pin Configuration/Recommended Circuit 9 8 7 13 GND3 Ext 6 CRF (100pF) CRF (100pF) Z3 14 5 GND 15 4 GND D_Ext CRF (100pF) GND4 Z4 Dup_Out 16 3 17 2 CRF (100pF) D_Ant CRF (100pF) 18 1 Cbypass (100pF) VDD CTLD GND 24 Cbypass (100pF) 23 Cbypass (100pF) 22 CTLC Cbypass (100pF) CTLA Rx 21 Cbypass (100pF) 20 CRF (100pF) 19 CTLB GND GND When using this IC, the following external components should be used: This capacitor is used for RF decoupling and must be used for all applications. CRF: 100pF is recommended. Cbypass: This capacitor is used for DC line filtering. 100pF is recommended. –3– CXG1166ER Truth Table A: Rx/Tx B: Main/diversity C: External/antenna D: TDMA/28.8k State On Pass A B C D F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 1 Tx – Ext H — L L H L L L L L L L L H H H H L L H H H 2 Tx – Ant H — H L L H L L L L L L H L H H H L L H H H 3 Rx – Ext L L L L L L L L H L L L L H H H L H L H H L 4 Rx – Ant L L H L L L L L L H L L H L H H L H L H H L 5 Rx – D_Ext L H L L L L L L L L L H H H H L L H L H H L 6 Rx – D_Ant L H H L L L L L L L H L H H L H L H L H H L — L H H L L L H L H L L H L H H L H H L L L — H H H L L L H L L H L H L L H L H H L L L — L L H L L H L H L L L L H H H L H H L L L — H L H L L H L L L L H L H H L L H H L L L 7 Dup_Out – Ant Rx – Ant 8 Dup_Out – Ant Rx – D_Ant 9 Dup_Out – Ext Rx – Ext 10 Dup_Out – Ext Rx – D_Ext DC Bias Condition Item (Ta = 25°C) Min. Typ. Max. Unit VDD 2.7 3.0 3.5 V Vctl (H) 2.2 3.0 3.5 V Vctl (L) 0 0.4 V –4– CXG1166ER Electrical Characteristics Item Insertion loss Isolation (Ta = 25°C) Port Symbol IL ISO. Condition Min. Typ. Max. Unit Tx – Ext ∗1 — 0.75 1.0 dB Tx – Ant ∗1 — 0.7 0.95 dB Tx – Dup_In ∗1 — 0.25 0.5 dB Rx – Ext ∗2 — 0.65 0.9 dB Rx – Ant ∗2 — 0.65 0.9 dB Rx – D_Ext ∗2 — 0.45 0.7 dB Rx – D_Ant ∗2 — 0.45 0.7 dB Dup_Out – Ext ∗1, ∗4 — 0.75 1.0 dB Rx – Ext ∗2, ∗5 — 0.8 1.05 dB Dup_Out – Ant ∗1, ∗4 — 0.9 1.15 dB Rx – Ant ∗2, ∗5 — 0.95 1.2 dB Dup_Out – Ext ∗1, ∗4 — 0.45 0.7 dB Rx – D_Ext ∗2, ∗5 — 0.5 0.75 dB Dup_Out – Ant ∗1, ∗4 — 0.45 0.7 dB Rx – D_Ant ∗2, ∗5 — 0.5 0.75 dB Tx – Ext ∗1 24 30 — dB Tx – Ant ∗1 24 30 — dB Tx – Dup_In ∗1 19 25 — dB Rx – Ext ∗2 24 30 — dB Rx – Ant ∗2 24 30 — dB Rx – D_Ext ∗2 24 30 — dB Rx – D_Ant ∗2 24 30 — dB Dup_Out – Ext ∗1, ∗4 29 35 — dB Rx – Ext ∗2, ∗5 29 35 — dB Dup_Out – Ant ∗1, ∗4 29 35 — dB Rx – Ant ∗2, ∗5 29 35 — dB Dup_Out – Ext ∗1, ∗4 24 30 — dB Rx – D_Ext ∗2, ∗5 24 30 — dB Dup_Out – Ant ∗1, ∗4 24 30 — dB Rx – D_Ant ∗2, ∗5 24 30 — dB ∗1 43 50 — dB Tx – Rx ∗1 Pin = 29.5dBm, 0/3V control, VDD = 2.7V to 3.5V, 1,429MHz to 1,453MHz ∗2 Pin = 10dBm, 0/3V control, VDD = 2.7V to 3.5V, 1,477MHz to 1,501MHz ∗3 π/4-shifted DQPSK, Pin = 29.5dBm, 0/3V control, VDD = 3.0V, 1,429MHz to 1,453MHz, ACP (±50kHz) < – 70dBc, ACP (±100kHz) < – 75dBc, 2nd harmonics < – 75dBc, 3rd harmonics < – 75dBc ∗4 Rx terminal end is OPEN (Pattern cut). ∗5 Dup_Out terminal end is OPEN (Pattern cut). –5– CXG1166ER (Ta = 25°C) Item Symbol 2fo Harmonics 3fo ±50kHz ACP ±100kHz Port Condition Min. Typ. Max. Unit Tx – Ext ∗3 — –70 –60 dBc Tx – Ant ∗3 — –70 –60 dBc Tx – Dup_In ∗3 — –75 –60 dBc Dup_Out – Ext (Main) ∗3, ∗4 — –75 –60 dBc Dup_Out – Ext (Div) ∗3, ∗4 — –70 –60 dBc Dup_Out – Ant (Main) ∗3, ∗4 — –70 –60 dBc Dup_Out – Ant (Div) ∗3, ∗4 — –70 –60 dBc Tx – Ext ∗3 — –67 –60 dBc Tx – Ant ∗3 — –67 –60 dBc Tx – Dup_In ∗3 — –70 –60 dBc Dup_Out – Ext (Main) ∗3, ∗4 — –67 –60 dBc Dup_Out – Ext (Div) ∗3, ∗4 — –67 –60 dBc Dup_Out – Ant (Main) ∗3, ∗4 — –67 –60 dBc Dup_Out – Ant (Div) ∗3, ∗4 — –67 –60 dBc Tx – Ext ∗3 — –70 –57 dBc Tx – Ant ∗3 — –70 –57 dBc Tx – Dup_In ∗3 — –70 –57 dBc Dup_Out – Ext (Main) ∗3, ∗4 — –70 –57 dBc Dup_Out – Ext (Div) ∗3, ∗4 — –70 –57 dBc Dup_Out – Ant (Main) ∗3, ∗4 — –70 –57 dBc Dup_Out – Ant (Div) ∗3, ∗4 — –70 –57 dBc Tx – Ext ∗3 — –73 –65 dBc Tx – Ant ∗3 — –73 –65 dBc Tx – Dup_In ∗3 — –73 –65 dBc Dup_Out – Ext (Main) ∗3, ∗4 — –73 –65 dBc Dup_Out – Ext (Div) ∗3, ∗4 — –73 –65 dBc Dup_Out – Ant (Main) ∗3, ∗4 — –73 –65 dBc Dup_Out – Ant (Div) ∗3, ∗4 — –73 –65 dBc Bias current IDD VDD = 3.0V 235 350 µA Control current Ictl Vctl (H) = 3.0V 15 30 µA ∗1 Pin = 29.5dBm, 0/3V control, VDD = 2.7V to 3.5V, 1,429MHz to 1,453MHz ∗2 Pin = 10dBm, 0/3V control, VDD = 2.7V to 3.5V, 1,477MHz to 1,501MHz ∗3 π/4-shifted DQPSK, Pin = 29.5dBm, 0/3V control, VDD = 3.0V, 1,429MHz to 1,453MHz, ACP (±50kHz) < – 70dBc, ACP (±100kHz) < – 75dBc, 2nd harmonics < – 75dBc, 3rd harmonics < – 75dBc ∗4 Rx terminal end is OPEN (Pattern cut). ∗5 Dup_Out terminal end is OPEN (Pattern cut). –6– CXG1166ER Pin Description Pin No. Symbol Description 2 D_Ant RF signal output (Use it, connecting capacity.) (100pF is recommended.) 4 D_Ext RF signal output (Use it, connecting capacity.) (100pF is recommended.) 6 Ext RF signal output (Use it, connecting capacity.) (100pF is recommended.) 7 Ant RF signal output (Use it, connecting capacity.) (100pF is recommended.) 12 Tx RF signal input (Use it, connecting capacity.) (100pF is recommended.) 13 Dup_In RF signal output (Use it, connecting capacity.) (100pF is recommended.) 17 Dup_Out RF signal input (Use it, connecting capacity.) (100pF is recommended.) 19 Rx RF signal input (Use it, connecting capacity.) (100pF is recommended.) 20 CTLA Logic control A 21 CTLB Logic control B 22 CTLC Logic control C 23 CTLD Logic control D 24 VDD Power supply input 1, 3, 5, 8, 9, 10, 11, 14, GND 15, 16, 18 GND –7– CXG1166ER Package Outline Unit: mm 24PIN VQFN㧔PLASTIC㧕 x4 0.2 3.3 18 S A-B C 0.4 ± 0.1 0.8 ± 0.1 Ǿ 13 غ1.5 4-R0.3 12 19 B 24 0.425 3.3 A 7 1 6 PIN 1 INDEX C 0.425 PIN 1 INDEX 0.4 S 0.05 M A-B C 0.05 S S Solder Plating MAX0.02 S + 0.09 0.14 – 0.03 TERMINAL SECTION Note:Cutting burr of lead are 0.05mm MAX. PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN LEAD TREATMENT SOLDER PLATING EIAJ CODE LEAD MATERIAL COPPER ALLOY JEDEC CODE PACKAGE MASS 0.02g SONY CODE VQFN-24P-05 LEAD PLATING SPECIFICATIONS ITEM SPEC. LEAD MATERIAL COPPER ALLOY SOLDER COMPOSITION Sn-Bi Bi:1-4wt% PLATING THICKNESS 5-18µm –8– Sony Corporation