Sony CXK591000YM-10LL 131,072-word x 9-bit high speed cmos static ram Datasheet

CXK591000TM/YM/M -55LL/70LL/10LL
131,072-word × 9-bit High Speed CMOS Static RAM
For the availability of this product, please contact the sales office.
Description
The CXK591000TM/YM/M is a high speed CMOS
static RAM organized as 131,072-words by 9 bits.
A polysilicon TFT cell technology realized
extremely low stand-by current and higher data
retention stability.
Special feature are low power consumption and
high speed.
The CXK591000TM/YM/M is a suitable RAM for
portable equipment with battery back up and parity
bit.
Features
• Fast access time
CXK591000TM/YM/M
(Access time)
-55LL
55ns (Max.)
-70LL
70ns (Max.)
-10LL
100ns (Max.)
• Low standby current
CXK591000TM/YM/M
-55LL/70LL/10LL
24µA (Max.)
• Low data retention current
CXK591000TM/YM/M
-55LL/70LL/10LL
14µA (Max.)
• Single +5V supply: 5V ± 10%.
• Low voltage date retention: 2.0V (Min.)
• Broad package line-up
CXK591000TM/YM
8mm × 20mm 32 pin TSOP Package
CXK591000M
525mil 32 pin SOP
Package
CXK591000TM
32 pin TSOP (PIastic)
CXK591000YM
32 pin TSOP (PIastic)
CXK591000M
32 pin SOP (PIastic)
Block Diagram
A10
A11
A9
A8
A13
A15
A16
A14
A12
A7
Buffer
A6
A5
A4
A3
A2
A1
A0
Buffer
OE
Function
131072 word × 9 bit static RAM
WE
CE1
CE2
Structure
Silicon gate CMOS IC
Row
Decoder
Memory
Matrix
1024 × 1152
VCC
GND
I /O Gate
Column
Decoder
Buffer
I /O Buffer
I/O1 I/O9
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E93X06-PS
CXK591000TM/YM/M
Pin Configuration (Top View)
A11
A9
A8
A13
WE
CE2
A15
Vcc
A16
A14
A12
A7
A6
A5
A4
A3
A3
A4
A5
A6
A7
A12
A14
A16
Vcc
A15
CE2
WE
A13
A8
A9
A11
Pin Description
1
2
32 OE
31 A10
3
4
30 CE1
29 I/O9
5
6
28 I/O8
27 I/O7
7
26 I/O6
25 I/O5
CXK591000TM
(Standard Pinout)
8
9
24 GND
23 I/O4
10
11
22 I/O3
21 I/O2
12
13
20 I/O1
19 A0
14
Symbol
A16 1
32 Vcc
A14 2
31 A15
A12 3
30 CE2
A7 4
29 WE
A6 5
28 A13
A5 6
27 A8
A4 7
26 A9
A3 8
25 A11
A2 9
24 OE
A1 10
23 A10
A0 11
22 CE1
16
18 A1
17 A2
I/O1 12
21 I/O9
16
17 A2
I/O2 13
20 I/O8
15
14
18 A1
I/O3 14
19 I/O7
13
20 I/O1
I/O4 15
18 I/O6
12
21 I/O2
GND 16
17 I/O5
11
22 I/O3
23 I/O4
15
19 A0
10
CXK591000YM
(Mirror Image Pinout)
9
8
24 GND
A0 to A16
Address input
I/O1 to I/O9
Data input/output
CE1, CE2
Chip enable 1, 2 input
WE
Write enable input
OE
Output enable input
VCC
Power supply
GND
Ground
CXK591000M
25 I/O5
26 I/O6
27 I/O7
7
6
28 I/O8
29 I/O9
5
4
3
30 CE1
2
31 A10
32 OE
1
Absolute Maximum Ratings
Item
(Ta = 25°C, GND = 0V)
Symbol
Rating
Unit
V
Supply voltage
VCC
Input voltage
VIN
–0.5 to +7.0
–0.5∗ to VCC + 0.5
Input and output voltage
VI/O
–0.5∗ to VCC + 0.5
V
Allowable power dissipation
PD
0.7
W
Operating temperature
Topr
0 to +70
°C
Storage temperature
Tstg
–55 to +150
°C
Soldering temperrature · time
Tsolder
235 · 10
°C · s
V
∗ VIN, VI/O = –3.0V Min. for pulse width less than 50ns.
Truth Table
CE1 CE2
OE
WE
Mode
I/O pin
VCC Current
H
×
×
×
Not selected
High Z
ISB1, ISB2
×
L
×
×
Not selected
High Z
ISB1, ISB2
L
H
H
H
Output disable
High Z
ICC1, ICC2, ICC3
L
H
L
H
Read
Data out
ICC1, ICC2, ICC3
L
H
×
L
Write
Data in
ICC1, ICC2, ICC3
×: "H" or "L"
–2–
Description
CXK591000TM/YM/M
DC Recommended Operating Conditions
Item
(Ta = 0 to +70°C, GND = 0V)
Symbol
Min.
Typ.
Max.
Unit
Supply voltage
VCC
4.5
5.0
5.5
V
Input high voltage
VIH
2.2
—
VCC + 0.3
V
Input low voltage
VIL
–0.3∗
—
0.8
V
∗ VIL = –3.0V Min. for pulse width less than 50ns.
Electrical Characteristics
• DC Characteristics
Item
(VCC = 5V ± 10%, GND = 0V, Ta = 0 to +70°C)
Test conditions
System
Min.
Typ.∗
Max.
Unit
Input leakage current
ILI
VIN = GND to VCC
–1
—
+1
µA
Output leakage
current
ILO
CE1 = VIH or CE2 = VIL or
OE = VIH or WE = VIL
VI/O = GND to VCC
–1
—
+1
µA
Operating power supply
current
ICC1
CE1 = VIL, CE2 = VIH
VIN = VIH or VIL
IOUT = 0mA
—
8
17
mA
-55LL
—
50
100
ICC2
Min. cycle
duty = 100%
IOUT = 0mA
-70LL
—
45
80
-10LL
—
40
70
—
12
24
0 to +70°C
—
—
24
0 to +40°C
—
—
5
+25°C
—
0.8
2.4
ICC3
Cycle time 1µs
duty = 100%
IOUT = 0mA
CE1 ≤ 0.2V
CE2 ≥ Vcc – 0.2V
VIL ≤ 0.2V
VIH ≥ Vcc – 0.2V
ISB1
CE2 ≤ 0.2V
CE1 ≥ Vcc – 0.2V
CE2 ≥ Vcc – 0.2V
Average operating current
Standby current
mA
mA
µA
ISB2
CE1 = VIH or CE2 = VIL
—
0.6
3
mA
Output high voltage
VOH
IOH = –1.0mA
2.4
—
—
V
Output low voltage
VOL
IOL = 2.1mA
—
—
0.4
V
∗ VCC = 5V, Ta = 25°C
–3–
CXK591000TM/YM/M
I/O capacitance
(Ta = 25°C, f = 1MHz)
Item
Symbol Test conditions
Min.
Typ.
Max.
Unit
Input capacitance
CIN
VIN = 0V
—
—
7
pF
I/O capacitance
CI/O
VI/O = 0V
—
—
8
pF
Note) This parameter is sampled and is not 100% tested.
AC Characteristics
• AC test conditions
(VCC = 5V ± 10%, Ta = 0 to +70°C)
Item
• Test circuit
Conditions
Input pulse high level
VIH = 2.2V
Input pulse low level
VIL = 0.8V
Input rise time
tr = 5ns
Input fall time
tf = 5ns
Input and output reference level
1.5V
TTL
CL
Output load conditions
-55LL
CL∗ = 30pF, 1TTL
-70LL/10LL
CL∗ = 100pF, 1TTL
∗ CL includes scope and jig capacitances.
–4–
CXK591000TM/YM/M
• Read cycle (WE = "H")
Item
tRC
Read cycle time
-55LL
Symbol
tAA
tCO1
Chip enable access time (CE1)
tCO2
Chip enable access time (CE2)
tOE
Output enable to output valid
tOH
Output hold from address change
tLZ1, tLZ2
Chip enable to output in low Z (CE1, CE2)
tOLZ
Output enable to output in low Z (OE)
Chip disable to output in high Z (CE1, CE2) tHZ1, tHZ2∗
tOHZ∗
Output disable to output in high Z (OE)
Address access time
-70LL
-10LL
Unit
Min.
Max.
Min.
Max.
Min.
Max.
55
—
70
—
100
—
ns
—
55
—
70
—
100
ns
—
55
—
70
—
100
ns
—
55
—
70
—
100
ns
—
30
—
40
—
50
ns
15
—
15
—
15
—
ns
10
—
10
—
10
—
ns
5
—
5
—
5
—
ns
—
25
—
25
—
35
ns
—
25
—
25
—
35
ns
∗ tHZ1, tHZ2 and tOHZ are defined as the time required for outputs to turn to high impedance state and are not
referred to as output voltage levels.
• Write cycle
Item
Write cycle time
Address valid to end of write
Chip enable to end of write
Data to write time overlap
Data hold from write time
Write pulse width
Address setup time
Write recovery time (WE)
Write recovery time (CE1, CE2)
Output active from end of write
Write to output in high Z
-55LL
Symbol
tWC
tAW
tCW
tDW
tDH
tWP
tAS
tWR
tWR1
tOW
tWHZ∗
-70LL
-10LL
Unit
Min.
Max.
Min.
Max.
Min.
Max.
55
—
70
—
100
—
ns
50
—
60
—
70
—
ns
50
—
60
—
70
—
ns
25
—
30
—
40
—
ns
0
—
0
—
0
—
ns
40
—
50
—
60
—
ns
0
—
0
—
0
—
ns
0
—
0
—
0
—
ns
0
—
0
—
0
—
ns
10
—
10
—
10
—
ns
—
25
—
25
—
30
ns
∗ tWHZ is defined as the time required for outputs to turn to high impedance state and is not referred to as
output voltage level.
–5–
CXK591000TM/YM/M
Timing Waveform
• Read cycle (1) : CE1 = OE = VIL, CE2 = VIH, WE = VIH
tRC
Address
tAA
tOH
Data out
Previous data valid
Data valid
• Read cycle (2) : WE = VIH
tRC
Address
tAA
CE1
tCO1
HZ
ttHZ1
tLZ1
CE2
tCO2
tLZ2
tHZ2
OE
tOE
tOHZ
tOLZ
Data out
Data valid
High impedance
–6–
CXK591000TM/YM/M
• Write cycle (1) : WE control
tWC
Address
tWR
tAW
OE
tCW
CE1
tCW
CE2
(∗1)
tWP
tAS
WE
tDW
tDH
Data valid
Data in
tWHZ
tOW
Data out
High impedance
(∗2)
(∗2)
• Write cycle (2) : CE1 control
tWC
Address
tAW
OE
tAS
tWR1 (∗3)
tCW
CE1
tCW
CE2
tWP
WE
tDW
Data valid
Data in
Data out
High impedance
–7–
tDH
CXK591000TM/YM/M
• Write cycle (3) : CE2 control
tWC
Address
tAW
OE
tCW
CE1
tWR1 (∗3)
tCW
tAS
CE2
tWP
WE
tDW
Data in
tDH
Data valid
Data out
High impedance
∗1 Write is executed when both CE1 and WE are at low and CE2 is at high simultaneously.
∗2 Do not apply the data input voltage of the opposite phase to the output while I/O pin is in output condition.
∗3 tWR1 is tested from either the rising edge of CE1 or the falling edge of CE2, whichever comes earlier, until the
end of the write cycle.
–8–
CXK591000TM/YM/M
Data retention waveform
• Low supply voltage data retention waveform (1) (CE1 control)
Data retention mode
tCDRS
tR
VCC
4.5V
2.2V
VDR
CE1
CE1 ≥ VCC – 0.2V
GND
• Low supply voltage data retention waveform (2) (CE2 control)
Data retention mode
VCC
4.5V
tCDRS
tR
CE2
VDR
0.4V
CE2 ≤ 0.2V
GND
Data Retention Characteristics
Item
Data retention
voltage
Data retention
current
(Ta = 0 to +70°C)
Symbol
VDR
ICCDR1
Test conditions
Min.
Typ.
Max.
Unit
2.0
—
5.5
V
0 to +70°C
—
—
14
0 to +40°C
—
—
3
+25°C
—
1.4
24
µA
∗1
VCC = 3.0V∗1
µA
ICCDR2
VCC = 2.0 to 5.5V∗1
—
0.5
0.8∗2
Data retention
setup time
tCDRS
Chip disable to data retention
mode
0
—
—
ns
Recovery time
tR
5
—
—
ms
∗1 CE1 ≥ Vcc – 0.2V, CE2 ≥ Vcc – 0.2V (CE1 control) or CE2 ≤ 0.2V (CE2 control)
∗2 VCC = 5V, Ta = 25°C
–9–
CXK591000TM/YM/M
Example of Representative Characteristics
Supply current vs. Supply voltage
Supply current vs. Ambient temperature
1.2
ICC1, ICC2 – Supply current (Relative Value)
ICC1, ICC2 – Supply current (Relative Value)
1.5
1.25
ICC2
1.0
ICC1
0.75
Ta = 25°C
0.5
4.5
1.1
ICC2 (Read)
1.0
ICC2 (Write)
ICC1
0.9
VCC = 5.0V
0.8
4.75
5
5.25
5.5
0
TAA, TCO1, TCO2, TOE – Access time (Relative Value)
Supply current vs. Frequency
55ns
70ns
100ns
ICC2 – Supply current (Relative Value)
1.0
Write
0.8
Read
0.6
0.4
0.2
Vcc = 5.0V
Ta = 25°C
0
0
4
8
12
16
20
Access time vs. Supply voltage
TAA, TCO1, TCO2, TOE – Access time (Relative Value)
TAA, TCO1, TCO2, TOE – Access time (Relative Value)
60
80
2.0
TOE
1.8
1.6
1.4
TAA, TCO1, TCO2
1.2
1.0
VCC = 5.0V
Ta = 25°C
0.8
0.6
0
1.2
TOE
TAA, TCO1, TCO2
0.8
Ta = 25°C
4.75
5
5.25
VCC – Supply voltage [V]
100
200
300
400
CL – Load capacity [pF]
1.4
0.6
4.5
40
Access time vs. Load capacitance
Frequency (1/tRC, 1/tWC) [MHz]
1.0
20
Ta – Ambient temperature [°C]
VCC – Supply voltage [V]
5.5
Access time vs. Ambient temperature
1.4
1.2
TOE
TCO1, TCO2, TAA
1.0
0.8
VCC = 5.0V
0.6
0
20
40
60
Ta – Ambient temperature [°C]
– 10 –
80
CXK591000TM/YM/M
Standby current vs. Ambient temperature
20
ISB1 – Standby current (Relative value)
ISB1, ISB2 – Standby current (Relative value)
Standby current vs. Supply voltage
2.0
1.5
1.0
ISB2
ISB1
0.5
Ta = 25°C
0
10
5
2
1
0.5
Vcc = 5.0V
0.2
2.0
3.0
4.0
5.0
6.0
0
VCC – Supply voltage (V)
Input voltage level vs. Supply voltage
Standby current vs. Ambient temperature
ISB2 – Standby current (Relative value)
VIL, VIH – Input voltage (Relative value)
80
1.4
1.2
1.1
VIL, VIH
1.0
0.9
Ta = 25°C
1.2
1.0
0.8
Vcc = 5.0V
0.6
0.8
4.5
4.75
5.0
5.25
0
5.5
20
40
60
80
Ta – Ambient temperature [°C]
VCC – Supply voltage [V]
Output high current vs. Output high voltage
Output low current vs. Output low voltage
1.4
IOL – Output low current (Ralative value)
IOH – Output high current (Ralative value)
20
40
60
Ta – Ambient temperature [°C]
1.2
1.0
Vcc = 5.0V
Ta = 25°C
0.8
0.6
1
2
3
4
1.8
1.4
1.0
Vcc = 5.0V
Ta = 25°C
0.6
0
5
VOH – Output high voltage [V]
0.2
0.4
0.6
VOL – Output low voltage [V]
– 11 –
0.8
CXK591000TM/YM/M
Package Outline
Unit: mm
CXK591000TM
32PIN TSOP (PLASTIC)
+ 0.2
1.07 – 0.1
8.0 ± 0.2
0.1
17
20.0 ± 0.2
∗18.4 ± 0.2
32
A
1
+ 0.08
0.2 – 0.03
+ 0.05
0.127 – 0.02
16
0.08 M
0.5
0.5 ± 0.1
0.1 ± 0.1
0° to 10°
NOTE : “∗” Dimensions do not include mold protrusion.
DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
TSOP-32P-L01
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
TSOP032-P-0820
LEAD MATERIAL
42 ALLOY
PACKAGE WEIGHT
0.3g
JEDEC CODE
CXK591000YM
32PIN TSOP (PLASTIC)
+ 0.2
1.07 – 0.1
8.0 ± 0.2
17
0.1
20.0 ± 0.2
∗18.4 ± 0.2
32
A
+ 0.05
0.127 – 0.02
1
0.08 M
0.5
0.1 ± 0.1
0.5 ± 0.1
16
+ 0.08
0.2 – 0.03
0° to 10°
NOTE: Dimension “∗” does not include mold protrusion.
DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
TSOP-32P-L01R
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
TSOP032-P-0820-B
LEAD MATERIAL
42 ALLOY
PACKAGE WEIGHT
0.3g
JEDEC CODE
– 12 –
CXK591000TM/YM/M
CXK591000M
32PIN SOP (PLASTIC)
+ 0.4
20.5 – 0.1
+ 0.15
2.9 – 0.25
0.1
14.0 ± 0.4
+ 0.3
11.2 – 0.1
11.9
17
32
A
16
+ 0.1
0.15 – 0.05
1.27
0.4 ± 0.1
0.2 ± 0.1
0.8 ± 0.2
1
0° to 10°
0.12
M
DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
SOP-32P-L02
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
SOP032-P-0525
LEAD MATERIAL
42 ALLOY
PACKAGE WEIGHT
1.2g
JEDEC CODE
– 13 –
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