Sony CXK77P36E160GB-42E 16mb lw r-l hstl high speed synchronous srams (512k x 36 or 1m x 18) Datasheet

SONY
CXK77P36E160GB / CXK77P18E160GB
16Mb LW R-L HSTL High Speed Synchronous SRAMs (512K x 36 or 1M x 18)
8Mb LW R-L w/ EC HSTL High Speed Synchronous SRAMs (256K x 36 or 512K x 18)
4/42/43/44
Preliminary
Description
The CXK77P36E160GB (organized as 524,288 words by 36 bits) and the CXK77P18E160GB (organized as 1,048,576 words
by 18 bits) are high speed CMOS synchronous static RAMs with common I/O pins. These synchronous SRAMs integrate input
registers, high speed RAM, output latches, and a one-deep write buffer onto a single monolithic IC. Register - Latch (R-L) read
operations and Late Write (LW) write operations are supported, providing a high-performance user interface.
Two distinct R-L modes of operation are supported, selectable via the M2 mode pin. When M2 is “high”, these devices function
as conventional 16Mb R-L SRAMs, and pin 2B functions as a conventional SA address input. When M2 is “low”, these devices
function as Error-Correcting (EC) 8Mb R-L SRAMs, and pin 2B is ignored.
When Error-Correcting 8Mb R-L mode is selected, the SRAM is divided into two banks internally - a “primary” bank and a
“secondary” bank. During write operations, input data is ultimately written to both banks internally (through one stage of write
pipelining). During read operations, data is read from both banks internally, and each byte of primary bank data is individually
parity-checked. If the parity of a particular byte of primary data is correct (that is, “odd”), it is driven valid externally. If the
parity of a particular byte of primary data is incorrect (that is, “even”), it is discarded, and the corresponding byte of secondary
bank data is driven valid externally. Primary / secondary bank data selection is performed on each data byte independently.
Data read from the secondary bank is NOT parity-checked.
Data read from the write buffer is NOT parity-checked.
All address and control input signals except ZZ (Sleep Mode) are registered on the rising edge of K (Input Clock).
During read operations, output data is driven valid from the falling edge of K, one half clock cycle after the address is registered.
During write operations, input data is registered on the rising edge of K, one full clock cycle after the address is registered.
The output drivers are series terminated, and the output impedance is programmable through an external impedance matching
resistor RQ. By connecting RQ between ZQ and VSS, the output impedance of all DQ pins can be precisely controlled.
Sleep (power down) mode control is provided through the asynchronous ZZ input. 250 MHz operation is obtained from a single
3.3V power supply. JTAG boundary scan interface is provided using a subset of IEEE standard 1149.1 protocol.
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
4 Speed Bins
-4 (-4A) (-4B)
-42 (-42A) (-42B)
-43 (-43A) (-43B)
-44
Cycle Time / Access Time
4.0ns / 3.9ns (3.8ns) (3.7ns)
4.2ns / 4.2ns (4.1ns) (4.0ns)
4.3ns / 4.5ns (4.4ns) (4.3ns)
4.4ns / 4.7ns
Single 3.3V power supply (VDD): 3.3V ± 5%
Dedicated output supply voltage (VDDQ): 1.9V typical
HSTL-compatible I/O interface with dedicated input reference voltage (VREF): 0.85V typical
Register - Latch (R-L) read operations
Late Write (LW) write operations
Conventional 16Mb or Error-Correcting (EC) 8Mb mode of operation, selectable via dedicated mode pin (M2)
Full read/write coherency
Byte Write capability
One cycle deselect
Differential input clocks (K/K)
Programmable impedance output drivers
Sleep (power down) mode via dedicated mode pin (ZZ)
JTAG boundary scan (subset of IEEE standard 1149.1)
119 pin (7x17), 1.27mm pitch, 14mm x 22mm Ball Grid Array (BGA) package
16Mb LW R-L and 8Mb LW R-L w/ EC, rev 1.1
1 / 25
March 2, 2001
SONY®
Preliminary
CXK77P36E160GB / CXK77P18E160GB
512K x 36 Pin Assignment (Top View)
1
2
3
4
5
6
7
A
VDDQ
SA
SA
NC
SA
SA
VDDQ
B
NC
SA (5)
SA
NC
SA
SA
NC
C
NC
SA
SA
VDD
SA
SA
NC
D
DQc
DQc
V SS
ZQ
V SS
DQb
DQb
E
DQc
DQc
V SS
SS
V SS
DQb
DQb
F
VDDQ
DQc
V SS
G (6)
V SS
DQb
VDDQ
G
DQc
DQc
SBWc
NC
SBWb
DQb
DQb
H
DQc
DQc
V SS
NC
V SS
DQb
DQb
J
VDDQ
VDD
VREF
VDD
VREF
VDD
VDDQ
K
DQd
DQd
V SS
K
V SS
DQa
DQa
L
DQd
DQd
SBWd
K
SBWa
DQa
DQa
M
VDDQ
DQd
V SS
SW
V SS
DQa
VDDQ
N
DQd
DQd
V SS
SA
V SS
DQa
DQa
P
DQd
DQd
V SS
SA
V SS
DQa
DQa
R
NC
SA
M1 (3)
VDD
M2 (4)
SA
NC
T
NC
NC (1)
SA
SA
SA
NC (1)
ZZ
U
VDDQ
TMS
TDI
TCK
TDO
RSVD (2)
VDDQ
Notes:
1. Pad Locations 2T and 6T are true no-connects. However, they are defined as SA address inputs in x18 LW SRAMs.
2. Pad Location 6U must be left unconnected. It is used by Sony for internal test purposes.
3. Pad Location 3R is defined as an M1 mode pin in LW SRAMs. However, it must be tied “high” in this device.
4. Pad Location 5R is defined as an M2 mode pin in this device. It must be tied “high” or “low”. When M2 is tied
“high”, this device functions as a conventional 16Mb R-L SRAM. When M2 is tied “low”, this device functions
as an Error-Correcting 8Mb R-L SRAM.
5. Pad Location 2B is defined as an SA address input in 16Mb LW SRAMs. However, it functions as a conventional
SA address input in this device only when M2 is tied “high”. It is ignored in this device when M2 is tied “low”.
6. Pad Location 4F is defined as a G output enable input in LW SRAMs. However, it must be tied “low” in this device.
16Mb LW R-L and 8Mb LW R-L w/ EC, rev 1.1
2 / 25
March 2, 2001
SONY®
Preliminary
CXK77P36E160GB / CXK77P18E160GB
1M x 18 Pin Assignment (Top View)
1
2
3
4
5
6
7
A
VDDQ
SA
SA
NC
SA
SA
VDDQ
B
NC
SA (5)
SA
NC
SA
SA
NC
C
NC
SA
SA
VDD
SA
SA
NC
D
DQb
NC (1b)
V SS
ZQ
V SS
DQa
NC (1b)
E
NC (1b)
DQb
V SS
SS
V SS
NC (1b)
DQa
F
VDDQ
NC (1b)
V SS
G (6)
V SS
DQ6a
VDDQ
G
NC (1b)
DQb
SBWb
NC
V SS
NC (1b)
DQa
H
DQb
NC (1b)
V SS
NC
V SS
DQa
NC (1b)
J
VDDQ
VDD
VREF
VDD
VREF
VDD
VDDQ
K
NC (1b)
DQb
V SS
K
V SS
NC (1b)
DQa
L
DQb
NC (1b)
V SS
K
SBWa
DQa
NC (1b)
M
VDDQ
DQb
V SS
SW
V SS
NC (1b)
VDDQ
N
DQb
NC (1b)
V SS
SA
V SS
DQa
NC (1b)
P
NC (1b)
DQb
V SS
SA
V SS
NC (1b)
DQa
R
NC
SA
M1 (3)
VDD
M2 (4)
SA
NC
T
NC
SA
SA
NC (1a)
SA
SA
ZZ
U
VDDQ
TMS
TDI
TCK
TDO
RSVD (2)
VDDQ
Notes:
1a. Pad Location 4T is a true no-connect. However, it is defined as an SA address input in x36 LW SRAMs.
1b. Pad Locations 2D, 7D, 1E, 6E, 2F, 1G, 6G, 2H, 7H, 1K, 6K, 2L, 7L, 6M, 2N, 7N, 1P, and 6P are true no-connects.
However, they are defined as DQ data inputs / outputs in x36 LW SRAMs.
2. Pad Location 6U must be left unconnected. It is used by Sony for internal test purposes.
3. Pad Location 3R is defined as an M1 mode pin in LW SRAMs. However, it must be tied “high” in this device.
4. Pad Location 5R is defined as an M2 mode pin in this device. It must be tied “high” or “low”. When M2 is tied
“high”, this device functions as a conventional 16Mb R-L SRAM. When M2 is tied “low”, this device functions
as an Error-Correcting 8Mb R-L SRAM.
5. Pad Location 2B is defined as an SA address input in 16Mb LW SRAMs. However, it functions as a conventional
SA address input in this device only when M2 is tied “high”. It is ignored in this device when M2 is tied “low”.
6. Pad Location 4F is defined as a G output enable input in LW SRAMs. However, it must be tied “low” in this device.
16Mb LW R-L and 8Mb LW R-L w/ EC, rev 1.1
3 / 25
March 2, 2001
SONY®
CXK77P36E160GB / CXK77P18E160GB
Preliminary
Pin Description
Symbol
Type
Description
SA
Input
Synchronous Address Inputs - Registered on the rising edge of K.
DQa, DQb
DQc, DQd
I/O
Synchronous Data Inputs / Outputs - Registered on the rising edge of K during write operations.
Driven from the falling edge of K during read operations.
DQa - indicates Data Byte a
DQb - indicates Data Byte b
DQc - indicates Data Byte c
DQd - indicates Data Byte d
K, K
Input
Differential Input Clocks
SS
Input
Synchronous Select Input - Registered on the rising edge of K.
specifies a write operation when SW = 0
SS = 0
specifies a read operation when SW = 1
specifies a deselect operation
SS = 1
SW
Input
Synchronous Global Write Enable Input - Registered on the rising edge of K.
specifies a write operation when SS = 0
SW = 0
specifies a read operation when SS = 0
SW = 1
SBWa, SBWb,
SBWc, SBWd
Input
Synchronous Byte Write Enable Inputs - Registered on the rising edge of K.
SBWa = 0 specifies write Data Byte a when SS = 0 and SW = 0
SBWb = 0 specifies write Data Byte b when SS = 0 and SW = 0
SBWc = 0 specifies write Data Byte c when SS = 0 and SW = 0
SBWd = 0 specifies write Data Byte d when SS = 0 and SW = 0
G
Input
Asynchronous Output Enable Input - Not supported. This control pin must be tied “low”.
ZZ
Input
Asynchronous Sleep Mode Input - Asserted (high) forces the SRAM into low-power mode.
M1
Input
Read Operation Protocol Select 1 - This mode pin must be tied “high” to select Register - Latch
read operations.
M2
Input
Read Operation Protocol Select 2 - This mode pin must be tied “high” or “low”.
M2 = 0
selects Error-Correcting 8Mb R-L functionality
M2 = 1
selects conventional 16Mb R-L functionality
ZQ
Input
Output Impedance Control Resistor Input
VDD
3.3V Core Power Supply - Core supply voltage.
VDDQ
Output Power Supply - Output buffer supply voltage.
VREF
Input Reference Voltage - Input buffer threshold voltage.
VSS
Ground
TCK
Input
JTAG Clock
TMS
Input
JTAG Mode Select
TDI
Input
JTAG Data In
TDO
Output
JTAG Data Out
RSVD
Reserved - This pin is used for Sony test purposes only. It must be left unconnected.
NC
No Connect - These pins are true no-connects, i.e. there is no internal chip connection to these
pins. They can be left unconnected or tied directly to VDD, VDDQ, or VSS.
16Mb LW R-L and 8Mb LW R-L w/ EC, rev 1.1
4 / 25
March 2, 2001
SONY®
Preliminary
CXK77P36E160GB / CXK77P18E160GB
•Clock Truth Table
K
ZZ
SS
(tn)
SW
(tn)
SBWx
(tn)
X
H
X
X
X
L→H
L
H
X
L→H
L
L
L→H
L
L→H
L→H
DQ
(tn)
DQ
(tn+1)
Sleep (Power Down) Mode
Hi - Z
Hi - Z
X
Deselect
Hi - Z
X
H
X
Read
Q(tn)
X
L
L
L
Write All Bytes
Hi - Z
D(tn)
L
L
L
X
Write Bytes With SBWx = L
Hi - Z
D(tn)
L
L
L
H
Abort Write
Hi - Z
X
Operation
•Dynamic M2 Mode Pin State Changes
Although M2 is defined as a static input (that is, it must be tied “high” or “low” at power-up), in some instance (such as
during device testing) it may be desirable to change its state dynamically (that is, without first powering off the SRAM)
while preserving the contents of the memory array. If so, the following criteria must be met:
1. At least two (2) consecutive deselect operations must be initiated prior to changing the state of M2, to ensure that the
most recent read or write operation completes successfully.
2. At least thirty-two (32) consecutive deselect operations must be initiated after changing the state of M2 before any read
or write operations can be initiated, to allow the SRAM sufficient time to recognize the change in state.
•Sleep (Power Down) Mode
Sleep (power down) mode is provided through the asynchronous input signal ZZ. When ZZ is asserted (high), the output
drivers will go to a Hi-Z state, and the SRAM will begin to draw standby current. Contents of the memory array will be
preserved. An enable time (tZZE) must be met before the SRAM is guaranteed to be in sleep mode, and a recovery time
(tZZR) must be met before the SRAM can resume normal operation.
•Programmable Impedance Output Drivers
These devices have programmable impedance output drivers. The output impedance is controlled by an external resistor,
RQ, connected between the SRAM’s ZQ pin and VSS, and is equal to one-fifth the value of this resistor, nominally. See
the DC Electrical Characteristics section for further information.
The output impedance is updated whenever the output drivers are in a Hi-Z state. Consequently, impedance updates will
occur during write and deselect operations. At power up, 8192 clock cycles followed by an impedance update via one of
the three methods described above are required to ensure that the output impedance has reached the desired value. After
power up, periodic impedance updates via write or deselect operations are also required to ensure that the output impedance remains within specified tolerances.
•Power-Up Sequence
For reliability purposes, Sony recommends that power supplies power up in the following sequence: VSS, VDD, VDDQ,
VREF, and Inputs. VDDQ should never exceed VDD. If this power supply sequence cannot be met, a large bypass diode
may be required between VDD and VDDQ. Please contact Sony Memory Application Department for further information.
16Mb LW R-L and 8Mb LW R-L w/ EC, rev 1.1
5 / 25
March 2, 2001
SONY®
Preliminary
CXK77P36E160GB / CXK77P18E160GB
•Absolute Maximum Ratings(1)
Item
Symbol
Rating
Units
Supply Voltage
VDD
-0.5 to +3.8
V
Output Supply Voltage
VDDQ
-0.5 to +2.3
V
VIN
-0.5 to VDDQ + 0.5
V
Input Voltage (M1, M2)
VMIN
-0.5 to VDD + 0.5 (3.8V max.)
V
Input Voltage (TCK, TMS, TDI))
VTIN
-0.5 to +3.8V
V
Operating Temperature
TA
0 to 85
°C
Junction Temperature
TJ
0 to 110
°C
Storage Temperature
TSTG
-55 to 150
°C
Input Voltage (Address, Control, Data, Clock)
(1)
Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This
is a stress rating only, and functional operation of the device at these or any other conditions other than those indicated in
the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
•BGA Package Thermal Characteristics
Item
Junction to Case Temperature
Symbol
Rating
Units
ΘJC
1.0
°C/W
•I/O Capacitance
(TA = 25oC, f = 1 MHz)
Item
Input Capacitance
Output Capacitance
Symbol
Test conditions
Min
Max
Units
Address
CADDR
VIN = 0V
---
4.2
pF
Control
CCTRL
VIN = 0V
---
4.2
pF
Clock
CCLK
VIN = 0V
---
3.5
pF
Data
CDATA
VOUT = 0V
---
4.8
pF
Note: These parameters are sampled and are not 100% tested.
16Mb LW R-L and 8Mb LW R-L w/ EC, rev 1.1
6 / 25
March 2, 2001
SONY®
Preliminary
CXK77P36E160GB / CXK77P18E160GB
•DC Recommended Operating Conditions
Item
(VSS = 0V, TA = 0 to 85oC)
Symbol
Min
Typ
Max
Units
Notes
Supply Voltage
VDD
3.13
3.3
3.47
V
Output Supply Voltage
VDDQ
1.8
1.9
2.0
V
Input Reference Voltage
VREF
0.7
0.85
1.0
V
1
Input High Voltage (Address, Control, Data)
VIH
VREF + 0.1
---
VDDQ + 0.3
V
2
Input Low Voltage (Address, Control, Data)
VIL
-0.3
---
VREF - 0.1
V
3
Input High Voltage (M1, M2)
VMIH
1.3
---
VDD + 0.3
V
Input Low Voltage (M1, M2)
VMIL
-0.3
---
0.4
V
Clock Input Signal Voltage
VKIN
-0.3
---
VDDQ + 0.3
V
Clock Input Differential Voltage
VDIF
0.2
---
VDDQ + 0.6
V
Clock Input Common Mode Voltage
VCM
0.7
---
1.3
V
1. The peak-to-peak AC component superimposed on V REF may not exceed 5% of the DC component.
2. V IH (max) AC = VDDQ + 1.0V for pulse widths less than one-quarter of the cycle time (tCYC/4).
3. V IL (min) AC = -1.0V for pulse widths less than one-quarter of the cycle time (tCYC/4).
16Mb LW R-L and 8Mb LW R-L w/ EC, rev 1.1
7 / 25
March 2, 2001
SONY®
Preliminary
CXK77P36E160GB / CXK77P18E160GB
•DC Electrical Characteristics
Item
Symbol
Input Leakage Current
(Address, Control, Clock)
ILI
Input Leakage Current
(M1, M2)
(VDD = 3.3V ± 5%, VSS = 0V, TA = 0 to 85oC)
Test Conditions
Min
Typ
Max
Units
VIN = V SS to VDDQ
-5
---
5
uA
IMLI
VMIN = VSS to V DD
-10
---
10
uA
Input Leakage Current
(Data)
IDLI
VDIN = V SS to VDDQ
-10
---
10
uA
Average Power Supply
Operating Current
IDD
---
---
750
mA
Power Supply
Standby Current
ISB
---
---
250
mA
Output High Voltage
VOH
VDDQ-0.4
---
---
V
Output Low Voltage
VOL
---
---
0.4
V
---
---
27
(25*1.1)
Ω
2,4
(RQ/5)*
0.9
RQ/5
(RQ/5)*
1.1
Ω
4
54
(60*0.9)
---
---
Ω
3,4
IOUT = 0 mA
SS = VIL, ZZ = VIL
IOUT = 0 mA
ZZ = VIH
IOH = -6.0 mA
RQ = 250 Ω
IOL = 6.0 mA
RQ = 250 Ω
VOH, VOL = VDDQ/2
RQ < 125Ω
Output Driver Impedance
ROUT
VOH, VOL = VDDQ/2
125Ω ≤ RQ ≤ 300Ω
VOH, VOL = VDDQ/2
RQ > 300Ω
Notes
1
1. This parameter applies to all speed bins (-4, -42, -43, and -44) in both device configurations (x18 and x36).
2. For maximum output drive (i.e. minimum impedance), the ZQ pin can be tied directly to VSS.
3. For minimum output drive (i.e. maximum impedance), the ZQ pin can be left unconnected or tied to VDDQ.
4. This parameter is guaranteed by design through extensive corner lot characterization.
16Mb LW R-L and 8Mb LW R-L w/ EC, rev 1.1
8 / 25
March 2, 2001
SONY®
Preliminary
CXK77P36E160GB / CXK77P18E160GB
•AC Electrical Characteristics
-4
Parameter
-42
-43
-44
Symbol
Units Notes
Min
Max
Min
Max
Min
Max
Min
Max
K Cycle Time
tKHKH
4.0
---
4.2
---
4.3
---
4.4
---
ns
K Clock High Pulse Width
tKHKL
1.5
---
1.5
---
1.5
---
1.5
---
ns
K Clock Low Pulse Width
tKLKH
1.5
---
1.5
---
1.5
---
1.5
---
ns
Address Setup Time
tAVKH
0.3
---
0.5
---
0.5
---
0.5
---
ns
1
Address Hold Time
tKHAX
0.5
---
0.5
---
0.5
---
0.5
---
ns
2
Write Enables Setup Time
tWVKH
0.3
---
0.5
---
0.5
---
0.5
---
ns
1
Write Enables Hold Time
tKHWX
0.5
---
0.5
---
0.5
---
0.5
---
ns
2
Synchronous Select Setup Time
tSVKH
0.3
---
0.5
---
0.5
---
0.5
---
ns
1
Synchronous Select Hold Time
tKHSX
0.5
---
0.5
---
0.5
---
0.5
---
ns
2
Data Input Setup Time
tDVKH
0.3
---
0.5
---
0.5
---
0.5
---
ns
1
Data Input Hold Time
tKHDX
0.5
---
0.5
---
0.5
---
0.5
---
ns
2
K Clock High to Output Valid
(“A” Sub-Bin)
(“B” Sub-Bin)
tKHQV
---
3.9
3.8
3.7
---
4.2
4.1
4.0
---
4.5
4.4
4.3
---
4.7
ns
K Clock Low to Output Valid
tKLQV
---
1.8
---
2.0
---
2.1
---
2.2
ns
K Clock Low to Output Hold
tKLQX
0.5
---
0.5
---
0.5
---
0.5
---
ns
3
K Clock Low to Output Low-Z
tKLQX1
0.5
---
0.5
---
0.5
---
0.5
---
ns
3,4
K Clock High to Output High-Z
tKHQZ
1.2
2.2
1.2
2.3
1.2
2.4
1.2
2.5
ns
3,4
Sleep Mode Enable Time
tZZE
---
15
---
15
---
15
---
15
ns
3
Sleep Mode Recovery Time
tZZR
20
---
20
---
20
---
20
---
ns
3
All parameters are specified over the range TA = 0 to 85oC.
All parameters are measured from the mid-point of the object signal to the mid-point of the reference signal, unless otherwise noted.
1. These parameters are measured from VREF ± 200mV to the clock mid-point (“-4” bin only).
2. These parameters are measured from VREF ± 200mV to the clock mid-point.
3. These parameters are sampled and are not 100% tested.
4. These parameters are measured at ± 50mV from steady state voltage.
16Mb LW R-L and 8Mb LW R-L w/ EC, rev 1.1
9 / 25
March 2, 2001
SONY®
Preliminary
CXK77P36E160GB / CXK77P18E160GB
•AC Electrical Characteristics (Guaranteed By Design)
-4
Parameter
K Clock High to Output High-Z
Symbol
tKHQZ
Min
Max
tKHQV - 2.4
2.0
Units
Notes
ns
1,2,3
1. This parameter is applicable when tKHQV ≤ 3.8ns.
2. This parameter is measured at the gate of the output driver of the SRAM.
3. Please refer to the previous page (p. 9) of this document for information concerning to what specification this parameter
is tested.
16Mb LW R-L and 8Mb LW R-L w/ EC, rev 1.1
10 / 25
March 2, 2001
SONY®
Preliminary
CXK77P36E160GB / CXK77P18E160GB
•AC Test Conditions
(VDD = 3.3V ± 5%, VDDQ = 1.9V ± 0.1V, TA = 0 to 85°C)
Item
Symbol
Conditions
Units
Input Reference Voltage
VREF
0.85
V
Address / Control Input High Level
VCAIH
1.45
V
Address / Control Input Low Level
VCAIL
0.35
V
Data Input High Level
VDIH
1.25
V
Data Input Low Level
VDIL
0.55
V
Input Rise & Fall Time
2.0
V/ns
Input Reference Level
0.85
V
Notes
Clock Input High Voltage
VKIH
1.45
V
VDIF = 0.7V
Clock Input Low Voltage
VKIL
0.75
V
VDIF = 0.7V
Clock Input Common Mode Voltage
VCM
1.10
V
Clock Input Rise & Fall Time
2.0
V/ns
Clock Input Reference Level
K/K cross
V
0.95
V
Output Reference Level
Fig.1
RQ = 250Ω
Output Load Conditions
Figure 1: AC Test Output Load
0.95 V
50 Ω
16.7 Ω
50 Ω
5 pF
DQ
16.7 Ω
0.95 V
50 Ω
16.7 Ω
50 Ω
5 pF
16Mb LW R-L and 8Mb LW R-L w/ EC, rev 1.1
11 / 25
March 2, 2001
SONY®
Preliminary
CXK77P36E160GB / CXK77P18E160GB
Timing Diagram of Read-Write-Read Operations
Synchronously Controlled via SW (SS = Low)
Figure 2
Read
Read
Read
Read
Write
Write
Write
Read
Read
Read
Read
A7
A8
A9
A10
A11
K
K
tKHKL tKLKH
tKHKH
tAVKH tKHAX
SA
A1
A2
A3
A4
A5
A6
SS = VIL
tWVKH tKHWX
SW
tWVKH tKHWX
SBWx
tKHQV
tKHQZ
tKLQV
DQ
tKLQX
Q1
tDVKH tKHDX
Q2
16Mb LW R-L and 8Mb LW R-L w/ EC, rev 1.1
Q3
Q4
D5
12 / 25
D6
tKLQX1
D7
Q8
Q9
Q10
March 2, 2001
SONY®
Preliminary
CXK77P36E160GB / CXK77P18E160GB
Timing Diagram of Read-Write-Read Operations
Synchronously Controlled via SS and Deselect Operations
Figure 3
Read
Read
Read
Deselect
Write
Write
Write
Deselect
Read
Read
Read
A7
A8
A9
K
K
tKHKL tKLKH
tKHKH
tAVKH tKHAX
SA
A1
A2
A3
A4
A5
A6
tSVKH tKHSX
SS
tWVKH tKHWX
SW
tWVKH tKHWX
SBWx
tKHQV
tKHQZ
tKLQV
DQ
tKLQX
Q1
tDVKH tKHDX
Q2
16Mb LW R-L and 8Mb LW R-L w/ EC, rev 1.1
Q3
D4
13 / 25
D5
tKLQX1
D6
Q7
Q8
March 2, 2001
SONY®
Preliminary
CXK77P36E160GB / CXK77P18E160GB
Timing Diagram of Sleep (Power-Down) Mode Operation
Asynchronously Controlled via ZZ
Figure 4
Read
(note 1)
Deselect
(note 2)
Deselect
(note 2)
(note 3)
Deselect
(note 4)
Read
(note 5)
Read
(note 5)
Read
(note 5)
A2
A3
A4
K
K
SA
A1
SS
SW
SBWx
tZZE
Begin
ISB
tZZR
ZZ
DQ
Q1
Q2
Q3
Note 1: This can be ANY valid operation. The depiction of a Read operation here is provided only as an example.
Note 2: Before ZZ is asserted, at least two (2) Deselect operations must be initiated after the last Read or Write operation is
initiated, in order to ensure the successful completion of the last Read or Write operation.
Note 3: While ZZ is asserted, all of the SRAM’s address, control, data, and clock inputs are ignored.
Note 4: After ZZ is deasserted, Deselect operations must be initiated until the specified recovery time (tZZR) has been met.
Read and Write operations may NOT be initiated during this time.
Note 5: This can be ANY valid operation. The depiction of a Read operation here is provided only as an example.
16Mb LW R-L and 8Mb LW R-L w/ EC, rev 1.1
14 / 25
March 2, 2001
SONY®
Preliminary
CXK77P36E160GB / CXK77P18E160GB
•Test Mode Description
These devices provide a JTAG Test Access Port (TAP) and Boundary Scan interface using a limited set of IEEE std.
1149.1 functions. This test mode is intended to provide a mechanism for testing the interconnect between master (processor, controller, etc.), SRAMs, other components, and the printed circuit board.
In conformance with a subset of IEEE std. 1149.1, these devices contain a TAP Controller and four TAP Registers. The
TAP Registers consist of one Instruction Register and three Data Registers (ID, Bypass, and Boundary Scan Registers).
The TAP consists of the following four signals:
TCK:
TMS:
TDI:
TDO:
Test Clock
Test Mode Select
Test Data In
Test Data Out
Induces (clocks) TAP Controller state transitions.
Inputs commands to the TAP Controller. Sampled on the rising edge of TCK.
Inputs data serially to the TAP Registers. Sampled on the rising edge of TCK.
Outputs data serially from the TAP Registers. Driven from the falling edge of TCK.
Disabling the TAP
When JTAG is not used, TCK should be tied “low” to prevent clocking the SRAM. TMS and TDI should either be tied
“high” through a pull-up resistor or left unconnected. TDO should be left unconnected.
Note: Operation of the TAP does not interfere with normal SRAM operation except when the SAMPLE-Z instruction is
selected (see page 20 for further information). Consequently, TCK, TMS, and TDI can be controlled any number of ways
without adversely affecting the functionality of the device.
(VDD = 3.3V ± 5%, TA = 0 to 85°C)
JTAG DC Recommended Operating Conditions
Parameter
Symbol
Test Conditions
Min
Max
Units
JTAG Input High Voltage
VTIH
---
1.4
3.6
V
JTAG Input Low Voltage
VTIL
---
-0.3
0.8
V
JTAG Output High Voltage (CMOS)
VTOH
ITOH = -100uA
2.6
---
V
JTAG Output Low Voltage (CMOS)
VTOL
ITOL = 100uA
---
0.1
V
JTAG Output High Voltage (TTL)
VTOH
ITOH = -8.0mA
2.3
---
V
JTAG Output Low Voltage (TTL)
VTOL
ITOL = 8.0mA
---
0.4
V
VTIN = 0V to 3.6V
-10
10
uA
JTAG Input Leakage Current
ITLI
(VDD = 3.3V ± 5%, TA = 0 to 85°C)
JTAG AC Test Conditions
Parameter
Symbol
Conditions
Units
JTAG Input High Level
VTIH
3.0
V
JTAG Input Low Level
VTIL
0.0
V
JTAG Input Rise & Fall Time
1.0
V/ns
JTAG Input Reference Level
1.5
V
JTAG Output Reference Level
1.5
V
JTAG Output Load Condition
16Mb LW R-L and 8Mb LW R-L w/ EC, rev 1.1
Notes
See Fig.1 (page 11)
15 / 25
March 2, 2001
SONY®
Preliminary
CXK77P36E160GB / CXK77P18E160GB
JTAG AC Electrical Characteristics
Parameter
Symbol
Min
Max
Unit
TCK Cycle Time
tTHTH
100
ns
TCK High Pulse Width
tTHTL
40
ns
TCK Low Pulse Width
tTLTH
40
ns
TMS Setup Time
tMVTH
10
ns
TMS Hold TIme
tTHMX
10
ns
TDI Setup Time
tDVTH
10
ns
TDI Hold TIme
tTHDX
10
ns
TCK Low to TDO Valid
tTLQV
TCK Low to TDO Hold
tTLQX
20
0
ns
ns
JTAG Timing Diagram
Figure 5
tTHTL
tTLTH
tTHTH
TCK
tMVTH
tTHMX
tDVTH
tTHDX
TMS
TDI
tTLQV
tTLQX
TDO
16Mb LW R-L and 8Mb LW R-L w/ EC, rev 1.1
16 / 25
March 2, 2001
SONY®
Preliminary
CXK77P36E160GB / CXK77P18E160GB
TAP Registers
TAP Registers are serial shift registers that capture serial input data (from TDI) on the rising edge of TCK, and drive serial
output data (to TDO) on the subsequent falling edge of TCK. They are divided into two groups: “Instruction Registers”,
of which there is one- the Instruction Register, and “Data Registers”, of which there are three - the ID Register, the Bypass
Register, and the Boundary Scan Register. Individual TAP registers are “selected” (inserted between TDI and TDO) when
the appropriate sequence of commands is given to the TAP Controller.
Instruction Register (3 bits)
The Instruction Register stores the instructions that are executed by the TAP Controller when the TAP Controller is in the
“Run-Test / Idle” state, or in any of the various “Data Register” states. It is loaded with the IDCODE instruction at powerup, or when the TAP Controller is in the “Test-Logic Reset” state or the “Capture-IR” state. It is inserted between TDI
and TDO when the TAP Controller is in the “Shift-IR” state, at which time it can be loaded with a new instruction. However, newly loaded instructions are not executed by the TAP Controller until the TAP Controller has reached the “UpdateIR” state.
The Instruction Register is 3 bits wide, and is encoded as follows:
Code
(2:0)
Instruction
Description
000
BYPASS
Inserts the Bypass Register between TDI and TDO.
001
IDCODE
Inserts the ID Register between TDI and TDO.
010
SAMPLE-Z
Captures the SRAM’s I/O ring contents in the Boundary Scan Register. Inserts the
Boundary Scan Register between TDI and TDO. Disables the SRAM’s data output drivers.
011
BYPASS
Inserts the Bypass Register between TDI and TDO.
100
SAMPLE
Captures the SRAM’s I/O ring contents in the Boundary Scan Register. Inserts the
Boundary Scan Register between TDI and TDO.
101
PRIVATE
Do not use. Reserved for manufacturer use only.
110
BYPASS
Inserts the Bypass Register between TDI and TDO.
111
BYPASS
Inserts the Bypass Register between TDI and TDO.
Bit 0 is the LSB of the Instruction Register, and Bit 2 is the MSB. When the Instruction Register is selected, TDI serially
shifts data into the MSB, and the LSB serially shifts data out through TDO.
ID Register (32 bits)
The ID Register is loaded with a predetermined device- and manufacturer-specific identification code when the IDCODE
instruction has been loaded into the Instruction Register and the TAP Controller is in the “Capture-DR” state. It is inserted
between TDI and TDO when the IDCODE instruction has been loaded into the Instruction Register and the TAP Controller is in the “Shift-DR” state.
The ID Register is 32 bits wide, and is encoded as follows:
Device
Revision Number
(31:28)
Part Number
(27:12)
Sony ID
(11:1)
Start Bit
(0)
512K x 36
xxxx
0000 0000 0100 1010
0000 1110 001
1
1M x 18
xxxx
0000 0000 0100 1011
0000 1110 001
1
Bit 0 is the LSB of the ID Register, and Bit 31 is the MSB. When the ID Register is selected, TDI serially shifts data into
the MSB, and the LSB serially shifts data out through TDO.
16Mb LW R-L and 8Mb LW R-L w/ EC, rev 1.1
17 / 25
March 2, 2001
SONY®
CXK77P36E160GB / CXK77P18E160GB
Preliminary
Bypass Register (1 bit)
The Bypass Register is one bit wide, and provides the minimum length serial path between TDI and TDO. It is loaded
with a logic “0” when the BYPASS instruction has been loaded in the the Instruction Register and the TAP Controller is
in the “Capture-DR” state. It is inserted between TDI and TDO when the BYPASS instruction has been loaded into the
Instruction Register and the TAP Controller is in the “Shift-DR” state.
Boundary Scan Register (70 bits for x36, 51 bits for x18)
The Boundary Scan Register is equal in length to the number of active signal connections to the SRAM (excluding the
TAP pins) plus a number of place holder locations reserved for density and/or functional upgrades. The Boundary Scan
Register is loaded with the contents of the SRAM’s I/O ring when the SAMPLE or SAMPLE-Z instruction has been loaded into the Instruction Register and the TAP Controller is in the “Capture-DR” state. It is inserted between TDI and TDO
when the SAMPLE or SAMPLE-Z instruction has been loaded into the Instruction Register and the TAP Controller is in
the “Shift-DR” state.
The Boundary Scan Register contains the following bits:
512K x 36
1M x 18
DQ
36
DQ
18
SA
19
SA
20
K, K
2
K, K
2
SS, SW, SBWx
6
SS, SW, SBWx
4
G, ZZ
2
G, ZZ
2
M1, M2
2
M1, M2
2
ZQ
1
ZQ
1
Place Holder
2
Place Holder
2
For deterministic results, all signals composing the SRAM’s I/O ring must meet setup and hold times with respect to TCK
(same as TDI and TMS) when sampled.
K/K are connected to a differential input receiver that generates a single-ended input clock signal to the device. Therefore,
in order to capture specific values for these signals in the Boundary Scan Register, these signals must be at opposite logic
levels when sampled.
Place Holders are required for some NC pins to allow for future density and/or functional upgrades. They are connected
to VSS internally, regardless of pin connection externally.
The Boundary Scan Order Assignment table that follows depicts the order in which the bits from the table above are arranged in the Boundary Scan Register. In the notation, Bit 1 is the LSB bit of the register. When the Boundary Scan Register is selected, TDI serially shifts data into the MSB, and the LSB serially shifts data out through TDO.
16Mb LW R-L and 8Mb LW R-L w/ EC, rev 1.1
18 / 25
March 2, 2001
SONY®
Preliminary
CXK77P36E160GB / CXK77P18E160GB
Boundary Scan Order Assignments
(By Exit Sequence)
512K x 36
1M x 18
Bit
Signal
Pad
Bit
Signal
Pad
Bit
Signal
Pad
Bit
Signal
Pad
1
M2
5R
36
SA
3B
1
M2
5R
36
SBWb
3G
2B
2
SA
6T
37
ZQ
4D
3A
3
SA
4P
38
SS
4E
2
SA
4P
37
3
SA
4T
38
SA
(2)
SA
(1)
4G
4
SA
6R
39
SA
3C
4
SA
6R
39
NC
5
SA
5T
40
SA
2C
5
SA
5T
40
NC (1)
4H
6
ZZ
7T
41
SA
2A
6
ZZ
7T
41
SW
4M
7
DQa
6P
42
DQc
2D
7
DQa
7P
42
DQb
2K
8
DQa
7P
43
DQc
1D
8
DQa
6N
43
DQb
1L
9
DQa
6N
44
DQc
2E
9
DQa
6L
44
DQb
2M
10
DQa
7N
45
DQc
1E
10
DQa
7K
45
DQb
1N
11
DQa
6M
46
DQc
2F
11
SBWa
5L
46
DQb
2P
12
DQa
6L
47
DQc
2G
12
K
4L
47
SA
3T
13
DQa
7L
48
DQc
1G
13
K
4K
48
SA
2R
14
DQa
6K
49
DQc
2H
14
G
4F
49
SA
4N
15
DQa
7K
50
DQc
1H
15
DQa
6H
50
SA
2T
16
SBWa
5L
51
SBWc
3G
16
DQa
7G
51
M1
3R
17
K
4L
52
ZQ
4D
17
DQa
6F
52
18
K
4K
53
SS
4E
18
DQa
7E
53
4G
19
DQa
6D
54
19
G
4F
54
NC
(1)
NC
(1)
20
SBWb
5G
55
4H
20
SA
6A
55
21
DQb
7H
56
SW
4M
21
SA
6C
56
22
DQb
6H
57
SBWd
3L
22
SA
5C
57
22
DQb
7G
58
DQd
1K
22
SA
5A
58
24
DQb
6G
59
DQd
2K
24
SA
6B
59
25
DQb
6F
60
DQd
1L
25
SA
5B
60
26
DQb
7E
61
DQd
2L
26
SA
3B
61
2B
62
(2)
27
DQb
6E
62
DQd
2M
27
28
DQb
7D
63
DQd
1N
28
SA
3A
63
29
DQb
6D
64
DQd
2N
29
SA
3C
64
30
SA
6A
65
DQd
1P
30
SA
2C
65
31
SA
6C
66
DQd
2P
31
SA
2A
66
32
SA
5C
67
SA
3T
32
DQb
1D
67
33
SA
5A
68
SA
2R
33
DQb
2E
68
34
SA
6B
69
SA
4N
34
DQb
2G
69
35
SA
5B
70
M1
3R
35
DQb
1H
70
SA
Note 1: NC pins at pad locations 4G and 4H are connected to VSS internally, regardless of pin connection externally.
Note 2: SA pin at pad location 2B has a small pull-down device. Consequently, if the pin is left unconnected, a logic level
“0” will be read from this location in the Boundary Scan Register. However, if the pin is NOT left unconnected, the
logic level applied to the pin will be read from this location in the Boundary Scan Register.
16Mb LW R-L and 8Mb LW R-L w/ EC, rev 1.1
19 / 25
March 2, 2001
SONY®
CXK77P36E160GB / CXK77P18E160GB
Preliminary
TAP Instructions
IDCODE
IDCODE is the default instruction loaded into the Instruction Register at power-up, and when the TAP Controller is in the
“Test-Logic Reset” state.
When the IDCODE instruction is selected, a predetermined device- and manufacturer-specific identification code is loaded into the ID Register when the TAP Controller is in the “Capture-DR” state, and the ID Register is inserted between
TDI and TDO when the TAP Controller is in the “Shift-DR” state.
Normal SRAM operation is not disrupted when the IDCODE instruction is selected.
BYPASS
When the BYPASS instruction is selected, a logic “0” is loaded into the Bypass Register when the TAP Controller is in
the “Capture-DR” state, and the Bypass Register is inserted between TDI and TDO when the TAP Controller is in the
“Shift-DR” state.
Normal SRAM operation is not disrupted when the BYPASS instruction is selected.
SAMPLE
When the SAMPLE instruction is selected, the individual logic states of all signals composing the SRAM’s I/O ring (see
the Boundary Scan Register description for the complete list of signals) are loaded into the Boundary Scan Register when
the TAP Controller is in the “Capture-DR” state, and the Boundary Scan Register is inserted between TDI and TDO when
the TAP Controller is in the “Shift-DR” state.
Normal SRAM operation is not disrupted when the SAMPLE instruction is selected.
SAMPLE-Z
When the SAMPLE-Z instruction is selected, the individual logic states of all signals composing the SRAM’s I/O ring
(see the Boundary Scan Register description for the complete list of signals) are loaded into the Boundary Scan Register
when the TAP Controller is in the “Capture-DR” state, and the Boundary Scan Register is inserted between TDI and TDO
when the TAP Controller is in the “Shift-DR” state.
Additionally, when the SAMPLE-Z instruction is selected, the SRAM’s data output drivers are disabled (that is, the DQ
I/O buffers are forced to an input state).
Consequently, normal SRAM operation is disrupted when the SAMPLE-Z instruction is selected. Read operations initiated while the SAMPLE-Z instruction is selected will fail.
16Mb LW R-L and 8Mb LW R-L w/ EC, rev 1.1
20 / 25
March 2, 2001
SONY®
Preliminary
CXK77P36E160GB / CXK77P18E160GB
TAP Controller
The TAP Controller is a 16-state state machine that controls access to the various TAP Registers and executes the operations associated with each TAP Instruction. State transitions are controlled by TMS and occur on the rising edge of TCK.
The TAP Controller enters the “Test-Logic Reset” state in one of two ways:
1. At power up.
2. When a logic “1” is applied to TMS for at least 5 consecutive rising edges of TCK.
The TDI input receiver is sampled only when the TAP Controller is in either the “Shift-IR” state or the “Shift-DR” state.
The TDO output driver is active only when the TAP Controller is in either the “Shift-IR” state or the “Shift-DR” state.
TAP Controller State Diagram
Figure 6
1
Test-Logic Reset
0
0
Run-Test / Idle
1
Select DR-Scan
1
Select IR-Scan
0
0
1
1
Capture-DR
Capture-IR
0
0
0
Shift-DR
1
1
Exit1-DR
Exit1-IR
0
0
0
Pause-DR
1
0
Exit2-IR
Update-DR
16Mb LW R-L and 8Mb LW R-L w/ EC, rev 1.1
0
21 / 25
0
1
1
1
0
Pause-IR
1
Exit2-DR
0
Shift-IR
1
1
1
Update-IR
1
0
March 2, 2001
SONY®
CXK77P36E160GB / CXK77P18E160GB
Preliminary
•Ordering Information
VDD
Size
Speed
(Cycle / Access Time)
3.3V
512K x 36
4.0ns / 3.9ns
4.0ns / 3.8ns
4.0ns / 3.7ns
CXK77P36E160GB-42E (-42F)
(-42G)
(-42H)
CXK77P36E160GB-42AE (-42AF) (-42AG) (-42AH)
CXK77P36E160GB-42BE (-42BF) (-42BG) (-42BH)
3.3V
512K x 36
4.2ns / 4.2ns
4.2ns / 4.1ns
4.2ns / 4.0ns
CXK77P36E160GB-43E (-43F)
(-43G)
(-43H)
CXK77P36E160GB-43AE (-43AF) (-43AG) (-43AH)
CXK77P36E160GB-43BE (-43BF) (-43BG) (-43BH)
3.3V
512K x 36
4.3ns / 4.5ns
4.3ns / 4.4ns
4.3ns / 4.3ns
CXK77P36E160GB-44E
(-44F)
(-44G)
(-44H)
3.3V
512K x 36
4.4ns / 4.7ns
CXK77P18E160GB-4E
CXK77P18E160GB-4AE
CXK77P18E160GB-4BE
(-4F)
(-4AF)
(-4BF)
(-4G)
(-4AG)
(-4BG)
(-4H)
(-4AH)
(-4BH)
3.3V
1M x 18
4.0ns / 3.9ns
4.0ns / 3.8ns
4.0ns / 3.7ns
CXK77P18E160GB-42E (-42F)
(-42G)
(-42H)
CXK77P18E160GB-42AE (-42AF) (-42AG) (-42AH)
CXK77P18E160GB-42BE (-42BF) (-42BG) (-42BH)
3.3V
1M x 18
4.2ns / 4.2ns
4.2ns / 4.1ns
4.2ns / 4.0ns
CXK77P18E160GB-43E (-43F)
(-43G)
(-43H)
CXK77P18E160GB-43AE (-43AF) (-43AG) (-43AH)
CXK77P18E160GB-43BE (-43BF) (-43BG) (-43BH)
3.3V
1M x 18
4.3ns / 4.5ns
4.3ns / 4.4ns
4.3ns / 4.3ns
CXK77P18E160GB-44E
3.3V
1M x 18
4.4ns / 4.7ns
Part Number
CXK77P36E160GB-4E
CXK77P36E160GB-4AE
CXK77P36E160GB-4BE
(-4F)
(-4AF)
(-4BF)
(-44F)
(-4G)
(-4AG)
(-4BG)
(-44G)
(-4H)
(-4AH)
(-4BH)
(-44H)
Note: The last character of the Part Number (“E”, “F”, “G”, or “H”) is used to distinguish between 1) the revision of
the device - Rev 1.0 or Rev 1.1, and 2) the fab location used to bump the device - Fujitsu Mie (F-MIE) or Fujitsu Tohoku
Electronics (FTE).
“E” indicates Rev 1.0 bumped at F-MIE.
“F” indicates Rev 1.0 bumped at FTE.
“G” indicates Rev 1.1 bumped at F-MIE.
“H” indicates Rev 1.1 bumped at FTE.
Please see the BGA Package Marking diagram on page 24 for further information.
Note: These devices may be manufactured at two different fab locations - Wafertech and TSMC. Please see the BGA
Package Marking diagram on page 24 for information concerning how to distinguish between devices manufactured
at the two facilities.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license
by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
16Mb LW R-L and 8Mb LW R-L w/ EC, rev 1.1
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March 2, 2001
SONY®
Preliminary
CXK77P36E160GB / CXK77P18E160GB
(7x17) 119 Pin BGA Package Dimensions
2.5 MAX
0.15 S A
13.0
0.6 ± 0.1
x4
7.62
0.35 S
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
0.15 S B
22.0
C
4-
0.
7
19.0
B
0
1.
4C
A
0.15 S
0.20
20.32
14.0
1 2 3 4 5
S
6 7
1.27
119 - φ0.75 ± 0.15
φ0.15 M S AB
P RELIMINARY
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
BGA-119P-021
BORAD TREATMENT
COPPER-CLAD LAMINATE
EIAJ CODE
BGA119-P-1422
LEAD MATERIAL
SOLDER
PACKAGE MASS
1.3g
JEDEC CODE
16Mb LW R-L and 8Mb LW R-L w/ EC, rev 1.1
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March 2, 2001
SONY®
Preliminary
CXK77P36E160GB / CXK77P18E160GB
(7x17) 119 Pin BGA Package Marking
SONY
CCCCCCCCCCCCCCC
DDDDD
BBBBBBB F F’
Description
1) C Field:
Part Number Code (up to 15 characters).
2) D Field:
Speed Bin Code (up to 5 characters). Includes character for Revision and Bump Fab Plant Code.
e.g. D = “-4AE” indicates “-4A” speed bin, Rev 1.0, Fujitsu Mie Bump Fab.
e.g. D= “-4AF” indicates “-4A” speed bin, Rev 1.0, Fujitsu Tohoku Electronics Bump Fab.
e.g. D = “-4AG” indicates “-4A” speed bin, Rev 1.1, Fujitsu Mie Bump Fab.
e.g. D= “-4AH” indicates “-4A” speed bin, Rev 1.1, Fujitsu Tohoku Electronics Bump Fab.
3) B Field:
Lot Code (up to 7 characters).
4) F Field:
Wafer Fab Plant Code (1 character).
e.g. F = “W” indicates Wafertech Fab.
e.g. F = “” (blank) indicates TSMC Fab (no character is used for TSMC).
5) F’ Field: Revised Control Code (1 character).
Example 1: Wafertech Fab
Example 2: TSMC Fab
SONY
SONY
CXK77P18E160GB
-4AE
xxxxxxx W x
CXK77P18E160GB
-4AE
xxxxxxx x
16Mb LW R-L and 8Mb LW R-L w/ EC, rev 1.1
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SONY®
CXK77P36E160GB / CXK77P18E160GB
Preliminary
•Revision History
Rev. #
Rev. date
Description of Modification
rev 0.0
05/19/00
Initial Version
rev 0.1
07/18/00
1. Removed Output Enable (G) support and associated specifications.
2. Added BGA Package Thermal Characteristics (p. 6).
1.0 °C/W
Junction to Case Temperature (ΘJC)
3. Modified DC Recommended Operating Conditions (p. 7).
Removed Single-Ended clock support.
Removed Clock Input Cross Point Voltage (VX) specification.
0.6V to 0.7V
VREF, VCM (min)
1.1V to 1.3V
VCM (max)
4. Modified DC Electrical Characteristics (p. 8).
Removed 3 MHz Average Power Supply Operating Current (IDD3) specification.
±1uA to ±5uA
ILI (min/max)
100mA to 200mA
ISB (max)
5. Modified AC Electrical Characteristics (p. 9).
Added note 1 regarding Address, Write Enables, Synchronous Select, and Data Input
Setup Times that states “these parameters are measured from VREF ± 200mV to the
clock mid-point (“-4” bin only)”.
6. Modified AC Test Conditions (p. 11).
Indicated that x18 devices are tested in both conventional 16Mb R-L mode and Error-Correcting 8Mb R-L mode, whereas x36 devices are tested in conventional 16Mb R-L
mode only.
7. Added BGA Package Dimensions (p. 23).
rev 0.2
11/03/00
1. Modified I/O Capacitance (p. 6).
3.5pF to 4.2pF
Address (CADDR) and Control (CCTRL)
4.5pF to 4.8pF
Data (CDATA)
2. Modified DC Recommended Operating Conditions (p. 7).
VREF + 0.3V to 1.3V
VMIH (min)
VREF - 0.3V to 0.4V
VMIL (max)
3. Modified DC Electrical Characteristics (p. 8).
650mA to 750mA
IDD (max)
200mA to 250mA
ISB (max)
4. Modified AC Electrical Characteristics (p. 9).
Added note 2 regarding Address, Write Enables, Synchronous Select, and Data Input Hold
Times that states “these parameters are measured from VREF ± 200mV to the clock midpoint”.
5. Modified AC Test Conditions (p. 11).
Removed notes indicating that x18 devices are tested in both conventional 16Mb R-L
mode and Error-Correcting 8Mb R-L mode, whereas x36 devices are tested in conventional 16Mb R-L mode only. x18 and x36 devices are tested in both modes.
6. Modified JTAG DC Recommended Operating Conditions (p. 15).
2.7V to 2.6V
VTOH (min) at ITOH = -100uA
2.4V to 2.3V
VTOH (min) at ITOH = -8mA
7. Added BGA Package Marking (p. 24).
rev 1.0
12/18/00
1. Modified Ordering Information (p. 22).
Added “F”, “G”, and “H” Part Numbers.
2. Modified BGA Package Marking (p. 24).
Updated “E” and added “F”, “G”, and “H” Speed Bin Code descriptions.
rev 1.1
03/02/01
1. Added “8Mb LW R-L w/ EC” to document title (p. 1).
16Mb LW R-L and 8Mb LW R-L w/ EC, rev 1.1
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March 2, 2001
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