Sony CXL5002P Cmos-ccd 1/2h delay line for ntsc Datasheet

CXL5002M/P
CMOS-CCD 1/2H Delay Line for NTSC
Description
The CXL5002M/P are general-purpose CMOS-CCD
delay line ICs that provide 1/2H delay time for NTSC.
CXL5002M
8 pin SOP (Plastic)
CXL5002P
8 pin DIP (Plastic)
Features
• Low power consumption 70mW (Typ.)
• Small size package (8-pin SOP, DIP)
• Low differential gain DG = 3% (Typ.)
• Input signal amplitude 180 IRE (= 1.28Vp-p, Max.)
• Low input clock amplitude operation 150mVp-p (Min.)
• Built-in peripheral circuits (clock driver, timing
generator, autobias, and output circuits)
Functions
• 340-bit CCD register
• Clock drivers
• Autobias circuit
• Sync tip clamp circuit
• Sample and hold circuit
Structure
CMOS-CCD
Absolute Maximum Ratings (Ta = 25°C)
• Supply voltage
VDD
11
V
• Supply voltage
VCL
6
V
• Operating temperature
Topr –10 to +60 °C
• Storage temperature
Tstg –55 to +150 °C
• Allowable power dissipation PD
CXL5002M 350 mW
CXL5002P 480 mW
Recommended Operating Conditions
Supply voltage
VDD
9 ± 5%
V
VCL
5 ± 5%
V
Recommended Clock Conditions
• Input clock amplitude
VCK
150mVp-p to 1.0Vp-p
(250mVp-p typ.)
• Clock frequency
fCK
10.7MHz
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E50586B79-PS
CXL5002M/P
IN
AUTO
FEED
OUT
Blook Diagram
8
7
6
5
ref.
AUTO BIAS CIRCUIT
(1 BIT)
CLAMP CIRCUIT
340-BIT SHIFT REGISTER
AMP
φ2
4
VDD
VCL
3
CLK
VSS
AMP
DUTY CONTROL
CIRCUIT
CLOCK DRIVERS
2
S/H
φ1
φ2
φ1
1
AMP
Pin Description
Pin No. Symbol
Description
Impedance [Ω] Pin No. Symbol
Description
Impedance [Ω]
1
VSS
GND
5
OUT
Signal output
2
VCL
5V power supply
6
FEED
Feedback DC output > 100k
3
CLK
Clock input
7
AUTO Autobias DC output
4
VDD
9V power supply
8
IN
> 100k
–2–
Signal input
600 to 1k
10k
> 100k
CXL5002M/P
Electrical Characteristics
(Ta = 25°C, VDD = 9.0V, VCL = 5.0V, fCK = 10.7MHz, VCK = 250mVp-p sine wave,
See "Electrical characteristics test circuit")
Item
Symbol
IDD
SW conditions Measuring
point
1
2
Measuring condition
—
4
5
mA
A2
—
7
9
mA
a
V1
–3
0
3
dB
b, c
b
V1
–3.0
–2.1
—
dB
—
3
5
%
e
a
S
—
3
5
deg
—
—
55
60
—
dB
V3
3.5
5.0
6.5
V
V4
3.5
5.0
6.5
V
V5
1.3
2.3
3.3
V
V6
1.7
2.7
3.7
V
a
a
IG
250kHz, 1.28Vp-p,
sine wave input
IG = 20 log (Output
voltage [Vp-p] /
1.28 [Vp-p])
a
Frequency
response
fG
Dissipation at 3.5MHz
in relation to 250kHz
fG = 20 log (V3.58MHz/
V250kHz) (Note 1)
Differential gain
DG
5-staircase wave input
Y = 140 IRE (= 1.0Vp-p)
Measure S point with
vector scope (Note 2)
Insertion gain
ICL
Differential phase DP
Allowable input
amplitude
Noise
—
—
—
S: Input = 250kHz,
1.0Vp-p
output (Vp-p)
f
a
V2
N: Input = DC ground
output (mVrms)
d
a
d
a
a
a
VIN-AC
S/N
VIN-AC
Output DC
voltage
VAUTO-DC
VFEED-DC 250kHz, 1.28Vp-p,
VOUT-DC sine wave input
Typ. Max. Unit
A1
250kHz, 1.28Vp-p,
sine wave input
Supply current
Min.
–3–
1.28 Vp-p
V2
250kHz, 300mVp-p sine wave
3.58MHz, 300mVp-p sine wave
Ground
5-staircase wave
250kHz, 1.0Vp-p sine wave
c.
d.
e.
f.
0.1µF
V3
1MΩ
a
VBIAS
100k
b
SW2
–4–
5V
A2
2
1
A1
4
9V
V6
5.1k
CLK
fCK = 10.7MHz
VCK = 250mVp-p sine wave
3
V5
0.01µF
CXL5002M/P
5
6
7
8
VSS
b.
0.1µF
IN
0.01µF
V4
AUTO
VCL
250kHz, 1.28Vp-p sine wave
SW1
FEED
CLK
a.
OUT
VDD
Electrical Characteristics Test Circuit
Note 4)
Note 3)
V1
BPF
LPF
9V
V2
Vector scope
S
CXL5002M/P
CXL5002M/P
Note 1) Frequency response measuring condition
V3.58MHz (Output signal voltage [Vp-p] at 3.58MHz input)
V250kHz (Output signal voltage [Vp-p] at 250kHz input)
Set Pin 8 (IN) voltage [V] = VIN-DC + 640mV.
[V]
3.58MHz, 300mVp-p sine wave
250kHz, 300mVp-p sine wave
640mV (adjust with VBIAS)
VIN-DC
Note 2) Differential gain and differential phase measuring condition
5-staircase wave signal
Chroma 40 IRE
140 IRE (1.0Vp-p)
40 IRE
1H 63.5µs
DG and DP are measured at output S point by vector scope.
Note 3) LPF frequency response
Note 4) BPF frequency response
[dB]
0
–3
[dB]
0
–3
–50
–50
0
5.8
10.7
Frequency [MHz]
0 50 200
4.1M 10.7M
Frequency [Hz]
–5–
CXL5002M/P
Application Circuit
9V
5.1k
0.01µF
0.1µF
0.1µF
L. P. F
signal output
Composite video signal input
8
7
6
5
2SA1175
1MΩ
CXL5002M/P
1
2
4
3
0.01µF
0.01µF
47µF
fCK = 10.7MHz
CLK VCK = 250mVp-p sine wave
0.01µF
47µF
5V
9V
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
Example of Representative Characteristics
Frequency response vs. Ambient temperature
Input = 300mVp-p
3.58MHz, sine wave
–1
–2
–3
–4
–1
–2
–3
–4
–20
0
20
40
60
Ta – Ambient temperature [°C]
4.7
Frequency response vs. Supply voltage
Input = 300mVp-p
3.58MHz, sine wave
1
–1
–2
–3
Input = 1.28Vp-p
250kHz, sine wave
0
–1
–2
–3
–4
8.5
5.0
5.3
VCL – Supply voltage [V]
Insertion gain vs. Ambient temperature
IG – Insertion gain [dB]
0
fG – Frequency response [dB]
Input = 300mVp-p
3.58MHz, sine wave
0
fG – Frequency response [dB]
0
fG – Frequency response [dB]
Frequency response vs. Supply voltage
9.0
VDD – Supply voltage [V]
9.5
–20
–6–
0
20
40
60
Ta – Ambient temperature [°C]
CXL5002M/P
Insertion gain vs. Supply voltage
Input = 1.28Vp-p
250kHz, sine wave
0
–1
–2
–3
0
–1
–2
–3
4.7
5.0
5.3
VCL – Supply voltage [V]
8.5
9.0
VDD – Supply voltage [V]
Differential gain vs. Supply voltage
4
4
DG – Differential gain [%]
DG – Differential gain [%]
Differential gain vs. Ambient temperature
3
2
3
2
1
1
0
–20
Input = 1.28Vp-p
250kHz, sine wave
1
IG – Insertion gain [dB]
1
IG – Insertion gain [dB]
Insertion gain vs. Supply voltage
0
0
20
40
60
Ta – Ambient temperature [°C]
4.7
Differential gain vs. Supply voltage
5.0
5.3
VCL – Supply voltage [V]
Frequency response
0
–1
Gain [dB]
DG – Differential gain [%]
4
3
–2
–3
2
–4
10k
1
0
8.5
100k
Frequency [Hz]
9.0
VDD – Supply voltage [V]
9.5
–7–
1M
9.5
CXL5002M/P
Package Outline
Unit: mm
CXL5002M
8PIN SOP (PLASTIC)
+ 0.4
1.85 – 0.15
+ 0.4
6.1 – 0.1
8
5
1
+ 0.2
0.1 – 0.05
6.9
7.9 ± 0.4
+ 0.3
5.3 – 0.1
0.15
0.5 ± 0.2
4
+ 0.1
0.2 – 0.05
0.45 ± 0.1
1.27
0.24 M
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
SOP-8P-L01
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
SOP008-P-0300
LEAD MATERIAL
42/COPPER ALLOY
PACKAGE MASS
0.1g
JEDEC CODE
CXL5002P
+ 0.3
6.4 – 0.1
+ 0.4
9.4 – 0.1
5
7.62
8
+ 0.1
0.05
0.25 –
8PIN DIP (PLASTIC)
0° to 15°
4
1
+ 0.4
3.7 – 0.1
3.0 MIN
0.5 MIN
2.54
0.5 ± 0.1
1.2 ± 0.15
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
DIP-8P-01
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
DIP008-P-0300
LEAD MATERIAL
COPPER ALLOY
PACKAGE MASS
0.5g
JEDEC CODE
–8–
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