Sony CXP740010 Cmos 8-bit single chip microcomputer Datasheet

CXP740056/740096/740010
CMOS 8-bit Single Chip Microcomputer
Description
The CXP740056/740096/740010 is a CMOS 8-bit
microcomputer integrating on a single chip an A/D
converter, serial interface, timer/counter, time-base
timer, capture timer/counter, remote control receive
circuit, PWM output, and the like besides the basic
configurations of 8-bit CPU, ROM, RAM, and I/O
port.
The CXP740056/740096/740010 also provides the
sleep/stop functions that enables lower power
consumption.
100 pin QFP (Plastic)
100 pin LQFP (Plastic)
Structure
Silicon gate CMOS IC
Features
• A wide instruction set (211 instructions) which covers various types of data.
— 16-bit arithmetic/multiplication and division/Boolean bit operation instructions
• Minimum instruction cycle
167ns at 24MHz operation (4.5 to 5.5V)
333ns at 12MHz operation (2.7 to 5.5V)
122µs at 32kHz operation (2.7 to 5.5V)
• Incorporated ROM capacity
56K bytes (CXP740056)
96K bytes (CXP740096)
120K bytes (CXP740010)
• Incorporated RAM capacity
4096 bytes
• Peripheral functions
— A/D converter
8 bits, 8 channels, successive approximation method
(Conversion time 10.3µs at 24MHz)
— Serial interface
Srart-stop synchronization (UART), 1 channel
Incorporated buffer RAM (Auto transfer for 1 to 32 bytes), 2 channels
8-bit clock syncronization (MSB/LSB first selectable), 1 channel
— Timer
8-bit timer 2 channels, 8-bit timer/counter 2 channels,
19-bit time-base timer, 16-bit capture timer/counter
32kHz timer/counter
— Remote control receive circuit
Noise elimination circuit
8-bit pulse measuring counter, 6-stage FIFO
— PWM output
12 bits, 2 channels
• Interruption
22 factors, 15 vectors, multi-interruption possible
• Standby mode
Sleep/stop
• Package
100-pin plastic QFP/LQFP
• Piggy/evaluation chip
CXP740000
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E98406-PS
8-BIT TIMER/COUNTER 0
8-BIT TIMER 1
8-BIT TIMER/COUNTER 2
8-BIT TIMER 3
16-BIT CAPTURE
TIMER/COUNTER 4
EC0
TO0
EC1
TO1
TO2
CINT
EC2
ADJ
SERIAL INTERFACE UNIT
(CH2)
BUFFER
RAM
BUFFER
RAM
SI2
SO2
SCK2
SERIAL
INTERFACE
UNIT (CH1)
SERIAL
INTERFACE
UNIT (CH0)
FIFO
12-BIT PWM GENERATOR 1
12-BIT PWM GENERATOR 0
UART BAUD RATE
GENERATOR
UART RECEIVER
UART TRANSMITTER
CS0
SI0
SO0
SCK0
CS1
SI1
SO1
SCK1
AVSS
A/D CONVERTER
AVDD
REMOCON IN
12
AVREF
RMC
PWM0
PWM1
TxD
RxD
AN0 to AN11
2
2
2
PRESCALER/
TIME-BASE TIMER
ROM
56K/96K/120K
BYTES
SPC 700αII
CPU CORE
PORT K
32kHz
TIMER-COUNTER
RAM
4096
BYTES
CLOCK
GENERATOR/
SYSTEM CONTROL
5
PK3 to PK7
NMI
INT0
INT1
INT2
INT3
INT4
INTERRUPT CONTROLLER
TEX
TX
EXTAL
XTAL
RST
VDD
VSS
2
PK1 to PK2
–2–
PORT I PORT H PORT G PORT F PORT E PORT D PORT C PORT B PORT A
PORT J
Block Diagram
PH0 to PH7
PI1 to PI7
8
7
PJ0 to PJ7
PG0 to PG7
8
8
PF0 to PF7
PE2 to PE7
6
8
PE0 to PE1
PD0 to PD7
PC0 to PC7
PB0 to PB7
PA0 to PA7
2
8
8
8
8
CXP740056/740096/740010
CXP740056/740096/740010
PI4/INT1/CS1
PI5/SCK1
PI3/TO0/ADJ
PI1/RMC
PI2/NMI
PK2/TEX
PK1/TX
VSS
VDD
NC
PA6
PA7
PA4
PA5
PA2
PA3
PA0
PA1
PC7
PC6
Pin Assignment (Top View) 100-pin QFP package
AA
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
PC5
1
PC4
2
PC3
3
PC2
4
PC1
5
80
PI6/SO1
79
PI7/SI1
78
PE0/INT0
77
PE1/INT2
76
PE2/PWM0
PC0
6
75
PE3/PWM1
PB7/SI2
7
74
PE4
PB6/SO2
8
73
PE5
PB5/SCK2
9
72
PE6
PB4/TO2
10
71
PE7
PB3
11
70
PG0/TxD
PB2
12
69
PG1/RxD
PB1
13
68
PG2/EC0
PB0
14
67
PG3/EC1
PJ7
15
66
PG4/EC2
PJ6
16
65
PG5/INT3
PJ5
17
64
PG6/INT4
PJ4
18
63
PG7/CINT
PJ3
19
62
AN0
PJ2
20
61
AN1
PJ1
21
60
AN2
PJ0
22
59
AN3
PD7
23
58
PF0/AN4
PD6
24
57
PF1/AN5
PD5
25
56
PF2/AN6
PD4
26
55
PF3/AN7
PD3
27
54
AVDD
PD2
28
53
AVREF
PD1
29
52
AVSS
PD0
30
51
PF4/AN8
Note) 1. NC (Pin 90) is left open.
2. VSS (Pins 41 and 88) are both connected to GND.
–3–
PF5/AN9
PF6/AN10
PF7/AN11
PK4/SO0
PK3/SCK0
PK5/SI0
PK6/CS0
XTAL
EXTAL
VSS
RST
PK7/TO1
PH0
PH1
PH2
PH3
PH4
PH6
PH5
PH7
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
CXP740056/740096/740010
PI7/SI1
PE0/INT0
PI6/SO1
PI5/SCK1
PI3/TO0/ADJ
PI4/INT1/CS1
PI1/RMC
PI2/NMI
PK2/TEX
PK1/TX
VDD
VSS
PA7
NC
PA5
PA6
PA4
PA2
PA3
PA0
PA1
PC7
PC6
PC4
PC5
Pin Assignment (Top View) 100-pin LQFP package
1
PE1/INT2
2
74
PE2/PWM0
PC1
AA
75
PC2
3
73
PE3/PWM1
PC0
4
72
PE4
PB7/SI2
5
71
PE5
PB6/SO2
6
70
PE6
PB5/SCK2
7
69
PE7
PB4/TO2
8
68
PG0/TxD
PB3
9
67
PG1/RxD
PB2
10
66
PG2/EC0
PB1
11
65
PG3/EC1
PB0
12
64
PG4/EC2
PJ7
13
63
PG5/INT3
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
PC3
PJ6
14
62
PG6/INT4
PJ5
15
61
PG7/CINT
PJ4
16
60
AN0
PJ3
17
59
AN1
PJ2
18
58
AN2
PJ1
19
57
AN3
PJ0
20
56
PF0/AN4
PD7
21
55
PF1/AN5
PD6
22
54
PF2/AN6
PD5
23
53
PF3/AN7
PD4
24
52
AVDD
PD3
25
51
AVREF
Note) 1. NC (Pin 88) is left open.
2. VSS (Pins 39 and 86) are both connected to GND.
–4–
AVSS
PF5/AN9
PF4/AN8
PF6/AN10
PF7/AN11
PK3/SCK0
PK4/SO0
PK5/SI0
EXTAL
PK6/CS0
XTAL
VSS
RST
PK7/TO1
PH0
PH1
PH2
PH4
PH3
PH5
PH6
PH7
PD0
PD1
PD2
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
CXP740056/740096/740010
Pin Description
Symbol
I/O
PA0 to PA7
I/O
PB0 to PB3
I/O
PB4/TO2
I/O/Output
PB5/SCK2
I/O/I/O
PB6/SO2
I/O/Output
PB7/SI2
I/O/Input
Description
(Port A)
8-bit I/O port. I/O can be set in a unit of single bits.
Incorporation of pull-up resistor can be set through the program in a unit of
single bits.
(8 pins)
(Port B)
8-bit I/O port. I/O can be set
in a unit of single bits.
Incorporation of pull-up
resistor can be set through
the program in a unit of
single bits.
(8 pins)
16-bit timer/counter rectangular wave output.
Serial clock I/O (CH2).
Serial data output (CH2).
Serial data input (CH2).
I/O
(Port C)
8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of pull-up
resistor can be set through the program in a unit of single bits.
(8 pins)
PD0 to PD7
I/O
(Port D)
8-bit I/O port. I/O can be set in a unit of single bits. Can drive 12mA sink
current. Incorporation of pull-up resistor can be set through the program in a
unit of single bits.
(8 pins)
PE0/INT0
Input/Input
PC0 to PC7
PE1/INT1
Input/Input
PE2/PWM0
Output/Output
PE3/PWM1
Output/Output
PE4 to PE7
Output
PF0/AN4
to
PF7/AN11
I/O
(Port E)
8-bit port. Lower 2 bits are
for input; upper 6 bits are for
output.
(8 pins)
(Port F)
8-bit I/O port. PF4 to PF7
can be set in a unit of single
bits as standby release
inputs. I/O can be set in a
unit of single bits.
Incorporation of pull-up
resistor can be set through
the program in a unit of
single bits.
(8 pins)
–5–
External interrupt inputs.
(2 pins)
12-bit PWM outputs.
(2 pins)
Analog inputs to A/D converter.
(8 pins)
CXP740056/740096/740010
I/O
Symbol
PG0/TxD
I/O/Output
PG1/RxD
I/O/Input
PG2/EC0
I/O/Input
PG3/EC1
I/O/Input
PG4/EC2
I/O/Input
PG5/INT3
I/O/Input
PG6/INT4
I/O/Input
PG7/CINT
I/O/Input
PH0 to PH7
Output
PI1/RMC
I/O/Input
PI2/NMI
I/O/Input
Description
UART transmission data output.
(Port G)
8-bit I/O port. I/O can be set
in a unit of single bits.
Incorporation of pull-up
resistor can be set through
the program in a unit of
single bits.
(8 pins)
UART reception data input.
External event input for 8-bit timer/counter 0.
External event input for 8-bit timer/counter 2.
External event input for 16-bit timer/counter.
External interrupt inputs.
(2 pins)
External capture input to 16-bit timer/counter.
(Port H)
8-bit I/O port. Operated as N-ch open drain output for medium voltage drive
(12V) and large current (12mA).
(8 pins)
Remote control receiver circuit input.
Non-maskable interrupt input.
(Port I)
7-bit I/O port. I/O can be set
in a unit of single bits.
Incorporation of pull-up
resistor can be set through
the program in a unit of
single bits.
(7 pins)
Output for the 8-bit timer/counter 1
rectanguler waves and 32-kHz oscillation
frequency demultiplication.
PI3/TO0/
ADJ
I/O/Output/
Output
PI4/INT1/
CS1
I/O/Input/
Input
PI5/SCK1
I/O/I/O
PI6/SO1
I/O/Output
Serial data output (CH1).
PI7/SI1
I/O/Input
Serial data input (CH1).
PJ0 to PJ7
I/O
PK1/TX
Input
PK2/TEX
Input/Input
PK3/SCK0
I/O/I/O
PK4/SO0
I/O/Output
PK5/SI0
I/O/Input
PK6/CS0
I/O/Input
PK7/TO1
I/O/Output
External
interrupt input.
Chip select input for serial
interface (CH1).
Serial clock I/O (CH1).
(Port J)
8-bit I/O port. I/O can be set in a unit of single bits.
Standby release input can be set in a unit of single bits.
Incorporation of pull-up resistor can be set through the program in a unit of
single bits.
(8 pins)
Crystal connectors for 32-kHz timer/counter
clock oscillation circuit.
(Port K)
7-bit port. lower 2 bits are for For usage as event count, connect clock
input; upper 5 bits are for I/O. oscillation source to TEX, and leave TX
open.
I/O can be set in a unit of
single bits.
Serial clock I/O (CH0).
For PK3 to PK7, incorporation
of pull-up resistor can be set Serial data output (CH0).
through the program in a unit Serial data input (CH0).
of single bits.
Chip select input for serial inteface (CH0).
(7 pins)
8-bit timer/counter 3 rectangular wave output.
–6–
CXP740056/740096/740010
Symbol
I/O
Description
Analog inputs to A/D converter.
(4 pins)
AN0 to AN3
Input
EXTAL
Input
Connects a crystal for system clock oscillation. When a clock is supplied
externally, input it to EXTAL pin and input a reversed phase clock to XTAL
pin.
Input
System reset; active at Low level.
XTAL
RST
NC
Not connected.
Leave this pin open for normal operation.
AVDD
Positive power supply of A/D converter.
AVREF
Input
Reference voltage input of A/D converter.
AVSS
GND of A/D converter.
VDD
Positive power supply.
VSS
GND. Connect both VSS pins to GND.
–7–
CXP740056/740096/740010
I/O Circuit Format for Pins
Pin
Circuit format
Port A
Port B
Port C
AAAA
AAAAA
AAAA
AAAAA
AAAAA
AAAAA
“0” after a reset
Ports A, B, C direction
“0” after a reset
Internal data bus
RD (Ports A, B, C)
18 pins
Port B
∗
Pull-up resistor
Ports A, B, C data
PA0 to PA7
PB0
PB2
PC0 to PC7
After a reset
AAAA
AAAA
AAAA
AAAA
AAAA
A
A
AA
AA
IP
∗ Pull-up transistors
approx. 100kΩ (VDD = 4.5 to 5.5V)
approx. 150kΩ (VDD = 2.7 to 3.3V)
∗
Pull-up resistor
“0” after a reset
Port B data
PB1
PB3
Port B direction
“0” after a reset
Internal data bus
RD (Port B)
Hi-Z
A
A
AA
AA
Hi-Z
IP
Schmitt input
∗ Pull-up transistors
approx. 100kΩ (VDD = 4.5 to 5.5V)
approx. 150kΩ (VDD = 2.7 to 3.3V)
2 pins
AAA
AAAA
AAAA
AAAA
AAAA
Port I
Port K
Pull-up resistor
∗
“0” after a reset
AA
AA
AA
TO0/ADJ, TO1
Ports I, K function
select
PB4/TO2
PI3/TO0/ADJ
PK7/TO1
“0” after a reset
Ports I, K data
Ports I, K direction
IP
“0” after a reset
Internal
data bus
RD (Ports B, I, K)
∗ Pull-up transistors
approx. 100kΩ (VDD = 4.5 to 5.5V)
approx. 150kΩ (VDD = 2.7 to 3.3V)
3 pins
–8–
Hi-Z
CXP740056/740096/740010
Circuit format
Pin
After a reset
Port B
Port I
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
Port K
∗
Pull-up resistor
“0” after a reset
Output buffer
capability
“0” after a reset
Output enable
PB5/SCK2
PI5/SCK1
PK3/SCK0
SCK2, SCK1, SCK0
Ports B, I, K function
select
“0” after a reset
Ports B, I, K data
Ports B, I, K direction
AA
AA
AA
AA
Hi-Z
IP
“0” after a reset
Internal
data bus
Schmitt input
RD (Ports B, I, K)
∗ Pull-up transistors
approx. 100kΩ (VDD = 4.5 to 5.5V)
approx. 150kΩ (VDD = 2.7 to 3.3V)
SCK2, SCK1, SCK0
3 pins
Port B
Port G
Port I
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
Port K
∗
Pull-up resistor
“0” after a reset
Output buffer
capability
PB6/SO2
PG0/TxD
PI6/SO1
PK4/SO0
“0” after a reset
Output enable
TO2, SO2, TxD, SO1, SO0
AA
AA
AA
Ports B, G, I, K
function select
“0” after a reset
Ports B, G, I, K data
Ports B, G, I, K
direction
IP
“0” after a reset
Internal
data bus
RD (Ports B, G, I, K)
∗ Pull-up transistors
approx. 100kΩ (VDD = 4.5 to 5.5V)
approx. 150kΩ (VDD = 2.7 to 3.3V)
4 pins
–9–
Hi-Z
CXP740056/740096/740010
Circuit format
Pin
Port B
Port G
PB7/SI2
PG1/RxD
PG2/EC0
PG3/EC1
PG4/EC2
PG5/INT3
PG6/INT4
PG7/CINT
PI1/RMC
PI2/NMI
PI4/INT1/CS1
PI7/SI1
PK5/SI0
PK6/CS0
Port I
Port K
AAAAA
AAAAA
AAAAA
AAAAA
AAAAA
After a reset
∗
Pull-up resistor
“0” after a reset
Ports B, G, I, K data
Ports B, G, I, K direction
AA
A
AA
A
IP
“0” after a reset
Schmitt input
Internal data bus
Hi-Z
RD (Ports B, G, I, K)
SI2, RxD, EC0, EC1, EC2, INT3, INT4, CINT,
RMC, MNI, INT1/CS1, SI1, SI0, CS0
∗ Pull-up transistors
approx. 100kΩ (VDD = 4.5 to 5.5V)
approx. 150kΩ (VDD = 2.7 to 3.3V)
14 pins
Port D
AAAA
AAAA
AAAA
AAAA
AAAA
∗2
Pull-up resistor
“0” after a reset
Port D data
PD0 to PD7
∗1
Port D direction
IP
Internal data bus
RD (Port D)
Hi-Z
∗1 Large current
12mA (VDD = 4.5 to 5.5V)
4.5mA (VDD = 2.7 to 3.3V)
∗2 Pull-up transistors
approx. 100kΩ (VDD = 4.5 to 5.5V)
approx. 150kΩ (VDD = 2.7 to 3.3V)
8 pins
Port E
AA
AA
A
AAAA
AAAA
Schmitt input
PE0/INT0
PE1/INT2
2 pins
INT0, INT2
IP
Internal data bus
RD (Port E)
– 10 –
Hi-Z
CXP740056/740096/740010
Circuit format
Pin
After a reset
Port E
AAAA
AAAA
AAAA
AAAA
AAAA
AA
AA
PWM0, PWM1
PE2/PWM0
PE3/PWM1
Port E function select
“0” after a reset
Port E data
Hi-Z
Hi-Z by writing to Port E data register or Port E
function select register → Output active
Internal data bus
2 pins
RD (Port E)
AA
AA
Port E
Port E data
PE4
PE5
Internal data bus
RD (Port E)
Hi-Z
Hi-Z by writing to Port E data
register → Output active
2 pins
Port E
AAAA
AAAA
AA
AA
Port E data
PE6
“1” after a reset
Internal data bus
1 pin
High level
RD (Port E)
Port E
∗
Internal reset signal
PE7
AAAA
AAAA
AA
AA
Port E data
“1” after a reset
Internal data bus
RD (Port E)
1 pin
AN0 to AN3
AAAA
AA
) )
Input multiplexer
A/D converter
IP
4 pins
∗ Pull-up transistors
approx. 150kΩ (VDD = 4.5 to 5.5V)
approx. 200kΩ (VDD = 2.7 to 3.3V)
"H" level
"H"level at
ON
resistance
of pull-up
transistor
during a
reset.
– 11 –
Hi-Z
CXP740056/740096/740010
Circuit format
Pin
Port F
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
After a reset
∗
Pull-up resistor
“0” after a reset
Port F data
PF0/AN4
to
PF3/AN7
Port F direction
“0” after a reset
Internal data bus
AA
AA
A
A
IP
Hi-Z
RD (Port F)
Port F
function select
“0” after a reset
A/D converter
4 pins
Port F
Input multiplexer
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
A
AAAAA
AAAA
∗ Pull-up transistors
approx. 100kΩ (VDD = 4.5 to 5.5V)
approx. 150kΩ (VDD = 2.7 to 3.3V)
∗
Pull-up resistor
“0” after a reset
Port F data
Port F direction
“0” after a reset
Internal data bus
PF4/AN8
to
PF7/AN11
RD (Port F)
AA
AA
AA
IP
Port F
function select
Hi-Z
“0” after a reset
Standby release
Edge detection
Polarity select
“0” after a reset
Input multiplexer
A/D converter
∗ Pull-up transistors
approx. 100kΩ (VDD = 4.5 to 5.5V)
approx. 150kΩ (VDD = 2.7 to 3.3V)
4 pins
– 12 –
CXP740056/740096/740010
Circuit format
Pin
Port H
AAAA
∗
Port H data
PH0 to PH7
“1” after a reset
Hi-Z
∗ High tension proof 12V
Large current
12mA (VDD = 4.5 to 5.5V)
4.5mA (VDD = 2.7 to 3.3V)
Internal data bus
RD (Port H)
8 pins
Port J
AA
AA
After a reset
AAAA
AAAA
AAAA
AAAA
AAAA
∗
Pull-up resistor
“0” after a reset
AA
AA
AA
Port J data
Port J direction
IP
“0” after a reset
PJ0 to PJ7
Internal data bus
RD (PortJ)
Hi-Z
Standby release
AAAA
A
AAAA
Edge detection
Polarity select
“0” after a reset
8 pins
∗ Pull-up transistors
approx. 100kΩ (VDD = 4.5 to 5.5V)
approx. 150kΩ (VDD = 2.7 to 3.3V)
Port K
TEX oscillation circuit control
“1” after a reset
Internal
data bus
RD (Port K)
PK1/TX
PK2/TEX
Internal
data bus
RD (Port K)
Schmitt input
PK2/TEX
IP
IP
Clock input
2 pins
PK1/TX
– 13 –
Oscillation
stop port
input
CXP740056/740096/740010
Circuit format
Pin
EXTAL
XTAL
2 pins
After a reset
AA
AA
A
AA AA A
AA
AA
EXTAL
IP
• Diagram shows circuit configuration
during oscillation.
• When program stops the oscillation,
the feedback registor disconnects,
and XTAL is driven at "H" level.
IP
Oscillation
XTAL
Pull-up resistor
RST
AA
Mask option OP
1 pin
AA
Schmitt input
IP
– 14 –
"L" level
(during a
reset)
CXP740056/740096/740010
Absolute Maximum Ratings
Item
(Vss = 0V reference)
Symbol
Rating
Unit
V
AVDD
–0.3 to +7.0
AVSS to +7.0∗1
AVSS
–0.3 to +0.3
V
AVREF
V
VDD
Supply voltage
Remarks
V
Input voltagte
VIN
AVSS to +7.0
–0.3 to +7.0∗2
Output voltage
VOUT
–0.3 to +7.0∗2
V
High level output current
IOH
–5
mA
Output (value per pin)
–50
mA
Total for all output pins
IOL
15
mA
All pins excluding large current
outputs (value per pin)
IOLC
20
mA
Large current outputs (value per pin) ∗3
Low level total output current
∑IOL
100
mA
Total for all output pins
Operating temperature
Topr
–20 to +75
°C
Storage temperature
Tstg
–55 to +150
°C
Allowable power dissipation
PD
High level total output current ∑IOH
Low level output current
600
380
V
mW
QFP package
LQFP package
∗1 AVDD and VDD must be set to the same voltage.
∗2 VIN and VOUT must not exceed VDD + 0.3V.
∗3 The large current output pins are Port D and H (PD, PH).
Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should
be conducted under the recommended operating conditions. Exceeding these conditions may adversely
affect the reliability of the LSI.
– 15 –
CXP740056/740096/740010
Recommended Operating Conditions
Item
Supply voltage
Analog voltage
Symbol
VDD
AVDD
VIH
High level input
voltage
VIHS
VIHEX
VIL
Low level input
voltage
VILS
VILEX
Operating temperature Topr
(Vss = 0V reference)
Min.
Max.
Unit
Remarks
4.5
5.5
V
2.7
5.5
V
fc = 24MHz or less Guaranteed operation
range for 1/2 and 1/4
fc = 12MHz or less frequency dividing clock.
2.7
5.5
V
Guaranteed operation range for 1/16
frequency dividing clock or sleep mode
2.7
5.5
V
Guaranteed operation range for TEX
2.5
5.5
V
2.7
5.5
V
Guaranteed data hold operation range
during stop mode
∗1
0.7VDD
VDD
V
∗2, ∗6
0.8VDD
VDD
V
∗2, ∗7
0.8VDD
VDD
V
VDD – 0.4 VDD + 0.3
V
VDD – 0.2 VDD + 0.2
V
Hysteresis input∗3
EXTAL pin∗4, ∗6, TEX pin∗5, ∗6
0
0.3VDD
V
EXTAL pin∗4, ∗7, TEX pin∗5, ∗7
∗2, ∗6
0
0.2VDD
V
∗2, ∗7
0
0.2VDD
V
–0.3
0.4
V
Hysteresis input∗3
EXTAL pin∗4, ∗6, TEX pin∗5, ∗6
–0.3
0.2
V
EXTAL pin∗4, ∗7, TEX pin∗5, ∗7
–20
+75
°C
∗1 AVDD and VDD must be set to the same voltage.
∗2 Normal input port (PA, PB0, PB2, PB4, PB6, PC, PD, PF, PG0, PI3, PI6, PJ, PK1, PK2, PK4, PK7)
∗3 RST, PB1, PB3, PB5/SCK2, PB7/SI2, PE0/INT0, PE1/INT2, PG1/RxD, PG2/EC0, PG3/EC1, PG4/EC2,
PG5/INT3, PG6/INT4, PG7/CINT, PI1/RMC, PI2/NMI, PI4/INT1/CS1, PI5/SCK1, PI7/SI1, PK3/SCK0,
PK5/SI0, PK6/CS0
∗4 Specifies only when the external clock is input.
∗5 Specifies only when the external event count is input.
∗6 This case applies to the range of 4.5 to 5.5V supply voltage (VDD).
∗7 This case applies to the range of 2.7 to 5.5V supply voltage (VDD).
– 16 –
CXP740056/740096/740010
Electrical Characteristics
(Ta = –20 to +75°C, VSS = 0V reference)
DC Characteristics (VDD = 4.5 to 5.5V)
Item
Symbol
High level
VOH
output voltage
Low level
output voltage VOL
Pins
PA to PD,
PE2 to PE7,
PF to PG,
PI to PJ,
PK3 to PK7
PB5, PB6∗1,
PG0∗1,
PI5, PI6∗1,
PK3, PK4∗1
IILE
IIHT
Input current
IILT
IILR
IIL
I/O leakage
current
IIZ
Open drain
output leakage
current
LLOH
(N-ch Tr off
state)
Min.
EXTAL
TEX
RST∗2
PA to PD∗3,
PF to PG∗3,
PI to PK∗3
PA to PD∗3,
PF to PG∗3,
PI to PK∗3,
PE,
AN0 to AN3
RST∗2
PH
Typ.
Max.
Unit
VDD = 4.5V, IOH = –0.5mA
4.0
V
VDD = 4.5V, IOH = –1.2mA
3.5
V
VDD = 4.5V, IOH = –1.0mA
4.0
V
VDD = 4.5V, IOH = –2.4mA
3.5
V
PA to PD,
VDD = 4.5V, IOL = 1.8mA
PE2 to PE7,
PF to PG,
PI to PJ,
VDD = 4.5V, IOL = 3.6mA
PK3 to PK7
PD, PH
IIHE
Conditions
VDD = 4.5V, IOL = 12.0mA
0.4
V
0.6
V
1.5
V
VDD = 5.5V, VIH = 5.5V
0.5
40
µA
VDD = 5.5V, VIL = 0.4V
–0.5
–40
µA
VDD = 5.5V, VIL = 5.5V
0.1
10
µA
VDD = 5.5V, VIL = 0.4V
–0.1
–10
µA
–1.5
–400
µA
–45
µA
VDD = 5.5V, VIL = 0.4V
VDD = 4.5V, VIL = 4.0V
–2.78
µA
VDD = 5.5V
VI = 0, 5.5V
±10
µA
VDD = 5.5V
VOH = 12V
50
µA
– 17 –
CXP740056/740096/740010
Item
Symbol
Pins
Conditions
24MHz crystal oscillation
(C1 = C2 = 15pF)
IDD1
Min.
Typ.
Max.
Unit
27
47
mA
1.0
5.0
mA
30
75
µA
12
40
µA
10
µA
20
pF
VDD = 5V ± 0.5V
Sleep mode
IDDS1
VDD = 5V ± 0.5V
Supply
current∗4
IDD2
32kHz crystal oscillation
(C1 = C2 = 47pF)
VDD
VDD = 3V ± 0.3V
Sleep mode
IDDS2
VDD = 3V ± 0.3V
IDDS3
Stop mode
(Termination of EXTAL and TEX pins
crystal oscillation)
VDD = 5V ± 0.5V
Input
capacity
CIN
PA to PD,
PE0 to PE1,
PF to PG,
Clock 1MHz
PI to PK,
0V for all pins excluding measured
AN0 to AN3, pins
EXTAL,
RST
10
∗1 This case applies that Port B buffer capability switching register (BUFB: 010F4h, bits 6 and 5 = "1, 1") and
Ports G/I/K buffer capability switching register (BUFG: 010F5h, bits 6, 5, 4, 3 and 0= "1, 1, 1, 1, 1") are ON.
∗2 RST pin specifies the input current when the pull-up resistor is selected, and specifies the leakage current
when no resistor is selected.
∗3 PA to PD, PF to PG and PI to PK pins specify the input current when the pull-up resistor is selected, and
specify the leakage current when no resistor is selected.
∗4 When all pins are open.
– 18 –
CXP740056/740096/740010
Electrical Characteristics
(Ta = –20 to +75°C, VSS = 0V reference)
DC Characteristics (VDD = 2.7 to 3.3V)
Item
Symbol
High level
VOH
output voltage
Low level
output voltage VOL
Pins
PA to PD,
PE2 to PE7,
PF to PG,
PI to PJ,
PK3 to PK7
PB5, PB6∗1,
PG0∗1,
PI5, PI6∗1,
PK3, PK4∗1
IIHE
EXTAL
IIHT
Input current
IILT
IILR
IIL
I/O leakage
current
IIZ
Open drain
output leakage
current
LLOH
(N-ch Tr off
state)
Min.
TEX
RST∗2
PA to PD∗3,
PF to PG∗3,
PI to PK∗3
PA to PD∗3,
PF to PG∗3,
PI to PK∗3,
PE,
AN0 to AN3
RST∗2
PH
Typ.
Max.
Unit
VDD = 2.7V, IOH = –0.12mA
2.5
V
VDD = 2.7V, IOH = –0.45mA
2.1
V
VDD = 2.7V, IOH = –0.24mA
2.5
V
VDD = 2.7V, IOH = –0.9mA
2.1
V
PA to PD,
VDD = 2.7V, IOL = 1.0mA
PE2 to PE7,
PF to PG,
PI to PJ,
VDD = 2.7V, IOL = 1.4mA
PK3 to PK7
PD, PH
IILE
Conditions
VDD = 2.7V, IOL = 4.5mA
0.25
V
0.4
V
0.9
V
VDD = 3.3V, VIH = 3.3V
0.3
20
µA
VDD = 3.3V, VIL = 0.3V
–0.3
–20
µA
VDD = 3.3V, VIL = 3.3V
0.1
10
µA
VDD = 3.3V, VIL = 0.4V
–0.1
–10
µA
–0.9
–200
µA
–20
µA
VDD = 3.3V, VIL = 0.3V
VDD = 3.3V, VIL = 2.7V
–1.0
µA
VDD = 3.3V
VI = 0, 3.3V
±10
µA
VDD = 3.3V
VOH = 12V
50
µA
– 19 –
CXP740056/740096/740010
Item
Symbol
Pins
12MHz crystal oscillation
(C1 = C2 = 15pF)
IDD1
Supply
current∗4
IDDS1
IDDS3
Conditions
VDD = 3.0V ± 0.3V∗3
Min.
Typ.
Max.
Unit
8
20
mA
0.3
1.5
mA
10
µA
20
pF
Sleep mode
VDD
VDD = 3.0V ± 0.3V
Stop mode
(Termination of EXTAL and TEX pins
crystal oscillation)
VDD = 3.0V ± 0.3V
Input
capacity
CIN
PA to PD,
PE0 to PE1,
PF to PG,
Clock 1MHz
PI to PK,
0V for all pins excluding measured
AN0 to AN3, pins
EXTAL,
RST
10
∗1 This case applies that Port B buffer capability switching register (BUFB: 010F4h, bits 6 and 5 = "1, 1") and
Ports G/I/K buffer capability switching register (BUFG: 010F5h, bits 6, 5, 4, 3 and 0 = "1, 1, 1, 1, 1") are ON.
∗2 RST pin specifies the input current when the pull-up resistor is selected, and specifies the leakage current
when no resistor is selected.
∗3 PA to PD, PF to PG and PI to PK pins specify the input current when the pull-up resistor is selected, and
specify the leakage current when no resistor is selected.
∗4 When all pins are open.
– 20 –
CXP740056/740096/740010
AC Characteristics
(1) Clock timing
(Ta = –20 to +75°C, VDD = 2.7 to 5.5V, Vss = 0V reference)
Item
Symbol
Pin
Conditions
Min.
VDD = 4.5 to 5.5V
fC
XTAL
EXTAL
Fig. 1, Fig. 2
System clock input pulse
width
tXL,
tXH
EXTAL
Fig. 1, Fig. 2 VDD = 4.5 to 5.5V
External clock drive
System clock input
rise time, fall time
EXTAL
Fig. 1, Fig. 2
External clock drive
EC
Fig. 3
Event count input clock
rise time, fall time
tCR,
tCF
tEH,
tEL
tER,
tEF
EC
Fig. 3
System clock frequency
fC
TEX
TX
VDD = 2.7 to 5.5V
Fig. 2 (32kHz clock applied
condition)
Event count input clock
pulse width
tTL,
tTH
tTR,
tTF
TEX
Fig. 3
TEX
Fig. 3
System clock frequency
Event count input clock
pulse width
Event count input clock
rise time, fall time
Typ.
Max.
1
24
1
12
28
Unit
MHz
ns
37.5
200
tsys + 50∗1
ns
ns
20
ms
kHz
32.768
µs
10
20
ms
∗1 tsys indicates the three values below according to the upper two bits (CPU clock selection) of the clock
control register (CLC: 000FEh).
tsys [ns] = 2000/fc (upper two bits = “00”), 4000/fc (upper two bits = “01”), 16000/fc (upper two bits = “11”)
1/fc
VDD – 0.4V (VDD = 4.5 to 5.5V)
VDD – 0.3V
EXTAL
0.4V (VDD = 4.5 to 5.5V)
0.3V
tXH
tCF
tXL
tCR
Fig. 1. Clock timing
AAAA
AAAA
AAAA
AAAAAAAAAAAA
Crystal oscillation
Ceramic oscillation
EXTAL
C1
External clock
EXTAL
XTAL
C2
32kHz clock applied condetions
crystal oscillation
TEX
XTAL
74HC04
TX
C2
C1
Fig. 2. Clock applied conditions
0.8VDD
TEX
EC0
EC1
EC2
0.2VDD
tEH
tTH
tEF
tTF
tEL
tTL
Fig. 3. Event count clock timing
– 21 –
tER
tTR
CXP740056/740096/740010
(2) Serial transfer (CH0, CH1)
Item
Symbol
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Pin
Conditions
Min.
Max.
Unit
CS↓ → SCK
delay time
tDCSK
SCK0
SCK1
Chip select transfer mode
(SCK = output mode)
1.5tsys + 200
ns
CS↑ → SCK
floating delay time
tDCSKF
SCK0
SCK1
Chip select transfer mode
(SCK = output mode)
1.5tsys + 200
ns
CS↓ → SO delay time
tDCSO
SO0
SO1
Chip select transfer mode
1.5tsys + 200
ns
CS↑ → SO floating
delay time
tDCSOF
SO0
SO1
Chip select transfer mode
1.5tsys + 200
ns
CS High level width
tWHCS
CS0
CS1
Chip select transfer mode
tsys + 200
ns
SCK cycle time
tKCY
SCK0
SCK1
Input mode
2tsys + 200
ns
8000/fc
ns
SCK High and Low
level width
tKH
tKL
SCK0
SCK1
Input mode
tsys + 100
ns
Output mode
4000/fc – 50
ns
SI input setup time
(for SCK↑)
tSIK
SI0
SI1
SCK input mode
–tsys + 100
ns
200
ns
SI input hold time
(for SCK↑)
tKSI
SI0
SI1
SCK input mode
2tsys + 200
ns
100
ns
SCK↓ → SO
delay time
tKSO
SO0
SO1
SCK input mode
Output mode
SCK output mode
SCK output mode
SCK output mode
2tsys + 200
ns
100
ns
Note 1) tsys indicates three values according to the contents of the clock control register (CLC: 000FEh)
upper 2 bits (CPU clock selection).
tsys [ns] = 2000/fc (upper 2 bits = “00”), 4000/fc (upper 2 bits = “01”), 16000/fc (upper 2 bits = “11”)
Note 2) CS, SCK, SI and SO represent CS0, SCK0, SI0 and SO0 for CH0; they represent CS1, SCK1, SI1
and SO1 for CH1, respectively.
Note 3) The load of SCK output mode and SO output delay time is 50pF + 1TTL.
Note 4) This case applies that Port I/K output buffer capability switching register (BUFG: 010F5h, bits 6, 5, 4
and 3 = "0, 0, 0, 0") is OFF.
– 22 –
CXP740056/740096/740010
Serial transfer (CH0, CH1)
Item
Symbol
(Ta = –20 to +75°C, VDD = 2.7 to 3.3V, Vss = 0V reference)
Pin
Conditions
Min.
Max.
Unit
CS↓ → SCK
delay time
tDCSK
SCK0
SCK1
Chip select transfer mode
(SCK = output mode)
1.5tsys + 250
ns
CS↑ → SCK
floating delay time
tDCSKF
SCK0
SCK1
Chip select transfer mode
(SCK = output mode)
1.5tsys + 250
ns
CS↓ → SO delay time
tDCSO
SO0
SO1
Chip select transfer mode
1.5tsys + 250
ns
CS↑ → SO floating
delay time
tDCSOF
SO0
SO1
Chip select transfer mode
1.5tsys + 250
ns
CS High level width
tWHCS
CS0
CS1
Chip select transfer mode
tsys + 200
ns
SCK cycle time
tKCY
SCK0
SCK1
Input mode
2tsys + 200
ns
8000/fc
ns
SCK High and Low
level widths
tKH
tKL
SCK0
SCK1
Input mode
tsys + 100
ns
4000/fc – 100
ns
SI input setup time
(for SCK↑)
tSIK
SI0
SI1
SCK input mode
–tsys + 100
ns
200
ns
SI input hold time
(for SCK↑)
tKSI
SI0
SI1
SCK input mode
2tsys + 200
ns
100
ns
SCK↓ → SO
delay time
tKSO
SO0
SO1
SCK input mode
Output mode
Output mode
SCK output mode
SCK output mode
SCK output mode
2tsys + 250
ns
125
ns
Note 1) tsys indicates three values according to the contents of the clock control register (CLC: 000FEh)
upper 2 bits (CPU clock selection).
tsys [ns] = 2000/fc (upper 2 bits = “00”), 4000/fc (upper 2 bits = “01”), 16000/fc (upper 2 bits = “11”)
Note 2) CS, SCK, SI and SO represent CS0, SCK0, SI0 and SO0 for CH0; they represent CS1, SCK1, SI1
and SO1 for CH1, respectively.
Note 3) The load of SCK output mode and SO output delay time is 50pF.
Note 4) This case applies that Port G/I/K output buffer capability switching register (BUFG: 010F5h, bits 6, 5,
4 and 3 = "1, 1, 1, 1") is ON.
– 23 –
CXP740056/740096/740010
tWHCS
CS0
CS1
0.8VDD
0.2VDD
tKCY
tDCSK
tKL
tDCSKF
tKH
0.8VDD
0.8VDD
SCK0
SCK1
0.2VDD
tSIK
tKSI
0.8VDD
SI0
SI1
Input data
0.2VDD
tDCSO
tKSO
tDCSOF
0.8VDD
SO0
SO1
Output data
0.2VDD
Fig. 4. Serial transfer CH0, CH1 timing
– 24 –
CXP740056/740096/740010
Serial transfer (CH2)
Item
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Symbol
Pin
SCK cycle time
tKCY
SCK2
SCK High and Low
level widths
tKH
tKL
SCK2
SI input setup time
(for SCK↑)
tSIK
SI2
SI input hold time
(for SCK↑)
tKSI
SI2
SCK↓ → SO delay time
tKSO
SO2
Conditions
Min.
Max.
Unit
1000
ns
8000/fc
ns
400
ns
4000/fc – 50
ns
SCK input mode
100
ns
SCK output mode
200
ns
SCK input mode
200
ns
SCK output mode
100
ns
Input mode
Output mode
Input mode
Output mode
SCK input mode
200
ns
SCK output mode
100
ns
Note 1) tsys indicates three values according to the contents of the clock control register (CLC: 000FEh) upper
2 bits (CPU clock selection).
tsys [ns] = 2000/fc (upper 2 bits = “00”), 4000/fc (upper 2 bits = “01”), 16000/fc (upper 2 bits = “11”)
Note 2) SCK, SI and SO represent SCK2, SI2 and SO2 for CH2, respectively.
Note 3) The load of SCK2 output mode and SO2 output delay time is 50pF+1TTL.
Note 4) This case applies that Port B output buffer capability switching register (BUFB: 010F4h, bits 6 and 5 =
“0, 0”) is OFF.
Serial transfer (CH2)
Item
(Ta = –20 to +75°C, VDD = 2.7 to 3.3V, Vss = 0V reference)
Symbol
Pin
SCK cycle time
tKCY
SCK2
SCK High and Low
level widths
tKH
tKL
SCK2
SI input setup time
(for SCK↑)
tSIK
SI2
SI input hold time
(for SCK↑)
tKSI
SI2
SCK↓ → SO delay time
tKSO
SO2
Conditions
Min.
Max.
Unit
1000
ns
8000/fc
ns
400
ns
4000/fc – 100
ns
SCK input mode
100
ns
SCK output mode
200
ns
SCK input mode
200
ns
SCK output mode
100
ns
Input mode
Output mode
Input mode
Output mode
SCK input mode
250
ns
SCK output mode
125
ns
Note 1) tsys indicates three values according to the contents of the clock control register (CLC: 000FEh) upper
2 bits (CPU clock selection).
tsys [ns] = 2000/fc (upper 2 bits = “00”), 4000/fc (upper 2 bits = “01”), 16000/fc (upper 2 bits = “11”)
Note 2) SCK, SI and SO represent SCK2, SI2 and SO2 for CH2, respectively.
Note 3) The load of SCK2 output mode and SO2 output delay time is 50pF.
Note 4) This case applies that Port B output buffer capability switching register (BUFB: 010F4h, bits 6 and 5 =
“1, 1”) is ON.
– 25 –
CXP740056/740096/740010
tKCY
tKL
tKH
0.8VDD
SCK2
0.2VDD
tSIK
tKSI
0.8VDD
SI2
Input data
0.2VDD
tKSO
0.8VDD
SO2
Output data
0.2VDD
Fig. 5. Serial transfer CH2 timing
– 26 –
CXP740056/740096/740010
(3) A/D converter characteristics
(Ta = –20 to +75°C, VDD = AVDD = 4.5 to 5.5V, AVREF = 4.0 to AVDD, Vss = AVSS = 0V reference)
Item
Symbol
Pin
Conditions
Min.
Typ.
Resolution
Ta = 25°C
VDD = AVDD = AVREF = 5.0V
VSS = AVSS = 0V
Linearity errror
Absolute error
tCONV
tSAMP
Conversion time
Sampling time
Reference input voltage VREF
AVREF
Analog input voltage
AN0 to AN11
VIAN
IREF
AVREF current
IREFS
VDD = AVDD = 4.5 to 5.5V
Unit
8
Bits
±2
LSB
±3
LSB
31/fADC∗3, ∗4
µs
10/fADC∗3, ∗4
µs
AVDD – 0.5
V
0
V
Operation mode
AVREF
Max.
0.6
Sleep mode
Stop mode
32kHz operation mode
1.0
mA
10
µA
(Ta = –20 to +75°C, VDD = AVDD = 2.7 to 3.3V, AVREF = 2.7 to AVDD, Vss = AVSS = 0V reference)
Item
Symbol
Pin
Conditions
Min.
Typ.
Resolution
Ta = 25°C
VDD = AVDD = AVREF = 3.0V
VSS = AVSS = 0V
Linearity errror
Absolute error
Conversion time
Sampling time
Reference input voltage VREF
AVREF
Analog input voltage
AN0 to AN11
IREF
AVREF current
IREFS
Digital conversion value
VDD = AVDD = 2.7 to 3.3V
Operation mode
AVREF
FFh
FEh
Linearity error
01h
00h
VFT
VZT
Unit
8
Bits
±2
LSB
±3
LSB
31/fADC∗3, ∗4
10/fADC∗3, ∗4
tCONV
tSAMP
VIAN
Max.
Analog input
Sleep mode
Stop mode
32kHz operation mode
µs
µs
AVDD – 0.3
V
0
V
0.4
0.7
mA
10
µA
∗1 VZT: Value at which the digital conversion value changes
from 00h to 01h and vice versa.
∗2 VFT: Value at which the digital conversion value changes
from FEh to FFh and vice versa.
∗3 fADC indicates the below values due to the contents of bit
6 (CKS) of the A/D control register (ADC: 000F9h).
PS3 selected
fADC = fc/4
PS4 selected
fADC = fc/8
However, when PS3 is selected, fc is 12MHz or less.
∗4 Sub clock operated tCONV = 34/fTEX
tSAMP = 10/fTEX
Fig. 6. Definition of A/D converter terms
– 27 –
CXP740056/740096/740010
(4) Interruption, reset input (Ta = –20 to +75°C, VDD = 2.7 to 5.5V, Vss = 0V reference)
Item
Symbol
Pin
External interruption
High and Low level widths
tIH
tIL
INT0
INT1
INT2
INT3
INT4
NMI
Reset input Low level width
tRSL
RST
Conditions
Min.
Unit
1
µs
32/fc
µs
tIH
INT0
INT1
INT2
INT3
INT4
NMI
(NMI is specified only for
the falling edge)
Max.
tIL
0.8VDD
0.2VDD
tIL
tIH
Fig. 7. Interruption input timing
tRSL
RST
0.2VDD
Fig. 8. RST input timing
– 28 –
CXP740056/740096/740010
Appendix
Fig. 9. Recommended oscillation circuit
AAAAA
AAAAA
AAAA
AAAAA
AAAA AAAAA
A
A
A
A
AA
(i) Main clock
EXTAL
XTAL
Rd
C1
(ii) Main clock
(iii) Sub clock
EXTAL
TEX
XTAL
TX
Rd
C2
Rd
C1
C2
C1 C2
Manufacturer
MURATA MFG
CO., LTD.
RIVER
ELETEC
CO., LTD.
KINSEKI LTD.
Seiko
Instruments Inc.
Model
fc (MHz)
CSA10.0MTZ
10.0
CSA12.0MTZ
12.0
CSA16.00MXZ040
CST10.0MTW∗
16.0
10.0
C1 (pF)
C2 (pF)
30
30
5
5
30
30
Rd (Ω)
Circuit
example
(i)
0 ∗1
CST12.0MTW∗
12.0
CST16.00MXW0C1∗
16.0
5
5
8.0
18
18
12.0
12
12
16.0
10
10
8.0
10
10
12.0
5
5
16.0
Open
Open
P3
32.768kHz
30
33
120k
(iii)
VTC-200
SP-T
32.768kHz
18
18
330k
(iii)
HC-49/U03
HC-49/U (-S)
∗ Indicates types with on-chip grounding capacitor (C1, C2).
∗1 XTAL series resistor (Rd = 500Ω or less) is hard to affect noise by ESD.
– 29 –
Remarks
(ii)
330 ∗1
(i)
0 ∗1
CL = 12.5pF
CXP740056/740096/740010
Characteristics Curve
IDD vs. VDD
IDD vs. fc
(fc = 24MHz, Ta = 25°C, Typical)
(VDD = 5.0V, Ta = 25°C, Typical)
1/2 dividing mode
1/4 dividing mode
20.0
10.0
30
IDD – Supply current [mA]
IDD – Supply current [mA]
1/16 dividing mode
5.0
Sleep mode
1.0
0.5
0.1
(100µA)
0.05
(50µA)
32kHz operation
mode
1/2 dividing mode
20
1/4 dividing mode
10
32kHz sleep mode
1/16 dividing mode
0.01
(10µA)
Sleep mode
0
2
3
4
5
0
6
10
20 24
fc – System clock [MHz]
VDD – Supply voltage [V]
IDD vs. VDD
IDD vs. fc
(fc = 12MHz, Ta = 25°C, Typical)
(VDD = 3.0V, Ta = 25°C, Typical)
1/2 dividing mode
20.0
1/4 dividing mode
30
5.0
1/16 dividing mode
Sleep mode
1.0
0.5
0.1
(100µA)
0.05
(50µA)
IDD – Supply current [mA]
IDD – Supply current [mA]
10.0
20
1/2 dividing mode
10
1/4 dividing mode
0.01
(10µA)
1/16 dividing mode
Sleep mode
0
2
3
4
5
0
6
VDD – Supply voltage [V]
– 30 –
10
20 24
fc – System clock [MHz]
CXP740056/740096/740010
Unit: mm
100PIN QFP (PLASTIC)
23.9 ± 0.4
+ 0.4
20.0 – 0.1
+ 0.1
0.15 – 0.05
80
51
+ 0.4
14.0 – 0.1
17.9 ± 0.4
15.8 ± 0.4
50
81
A
31
100
1
0.65
30
+ 0.15
0.3 – 0.1
0.13
+ 0.2
0.1 – 0.05
+ 0.35
2.75 – 0.15
M
0° to 10°
DETAIL A
0.8 ± 0.2
(16.3)
0.15
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
QFP-100P-L01
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
QFP100-P-1420
LEAD MATERIAL
42/COPPER ALLOY
PACKAGE MASS
1.7g
JEDEC CODE
100PIN LQFP (PLASTIC)
16.0 ± 0.2
∗
14.0 ± 0.1
75
51
76
(15.0)
50
0.5 ± 0.2
A
26 (0.22)
100
1
0.5
+ 0.08
0.18 – 0.03
25
0.13 M
+ 0.2
1.5 – 0.1
+ 0.05
0.127 – 0.02
0.1
0.1 ± 0.1
0° to 10°
0.5 ± 0.2
Package Outline
DETAIL A
NOTE: Dimension “∗” does not include mold protrusion.
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SOLDER PLATING
SONY CODE
LQFP-100P-L01
LEAD TREATMENT
EIAJ CODE
LQFP100-P-1414
LEAD MATERIAL
42 ALLOY
PACKAGE MASS
0.8g
JEDEC CODE
– 31 –
Similar pages