Sony CXP83412 Cmos 8-bit single chip microcomputer Datasheet

CXP83408/83412/83416
CXP83409/83413/83417
CMOS 8-bit Single Chip Microcomputer
Description
The CXP83408/83412/83416 and CXP83409/83413/
83417 are a CMOS 8-bit microcomputer which consists of
A/D converter, serial interface, timer/counter, time
base timer, 32kHz timer/counter, LCD controller/
driver, remote control receiving circuit and PWM
output, as well as basic configurations like 8-bit CPU,
ROM, RAM and I/O port. They are integrated into a
single chip.
Also CXP83408/83412/83416 and CXP83409/83413/
83417 sleep/ stop function which enables to lower power
consumption.
CXP83408/83412/83416
80 pin QFP (Plastic)
80 pin LQFP (Plastic)
CXP83409/83413/83417
80 pin QFP (Plastic)
Features
• A wide instruction set (213 instructions) which
covers various types of data
– 16-bit arithmetic/multiplication and division/
Boolean bit operation instructions
• Minimum instruction cycle
400ns at 10MHz operation (4.5 to 5.5V)
122µs at 32kHz operation (2.7 to 5.5V)
• Incorporated ROM capacity
8K bytes (CXP83408, 83409)
12K bytes (CXP83412, 83413)
16K bytes (CXP83416, 83417)
• Incorporated RAM capacity
448 bytes (LCD display data area included)
• Peripheral functions
– A/D converter
8 bits, 8 channels, successive approximation system
(Conversion time: 32µs/10MHz)
– Serial interface
Incorporated 8-bit and 8-stage FIFO
(1 to 8 bytes auto transfer), 1 circuit 2 channels
– Timer
8-bit timer, 8-bit timer/counter, 19-bit time base timer, 32kHz timer/counter
– LCD controller/driver
Maximum 128 segments display possible (During 1/4 duty)
4 common outputs, 32 segment outputs
Display method: Static, 1/2, 1/3 and 1/4 duty
Bias method: 1/2 and 1/3 bias
– Remote control receiving circuit
8-bit pulse measurement counter, 6-stage FIFO
– PWM output
14 bits 1 channel, 8 bits 1 channel
• Interruption
12 factors, 12 vectors, multi-interruption possible
• Standby mode
SLEEP/STOP
• Package
80-pin plastic QFP/LQFP
• Piggyback/evaluator
CXP83400 (CXP83408, 83412, 83416)
CXP83401 (CXP83409, 83413, 83417)
Structure
Silicon gate CMOS IC
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E93Z15C72-PS
–2–
4
COM0 to COM3
ADJ
8BIT TIMER 1
TO
FIFO
8BIT TIMER/COUNTER 0
SERIAL
INTERFACE
UNIT 0
CS0
SI0
SO0
SCK0
CS1
SI1
SO1
SCK1
FIFO
EC
REMOCON
14BIT PWM GENERATOR
8BIT PWM GENERATOR
LCD
CONTROLLER/
DRIVER
A/D CONVERTER
RMC
PWM0
PWM1
VL
VLC1
VLC2
VLC3
32
8
SEG0 to SEG31
AN0 to AN7
2
2
PRESCALER/
TIME BASE TIMER
ROM
8K/12K/16K BYTES
SPC700
CPU CORE
INTERRUPT CONTROLLER
Vss
RST
VDD
EXTAL
XTAL
TX
TEX
32kHz
TIMER/COUNTER
RAM
448 BYTES
CLOCK GENERATOR/
SYSTEM CONTROL
PB0 to PB7
8
8
PE0 to PE4
PE5 to PE6
PF0 to PF7
5
2
8
1
PH0
PD0 to PD7
8
PC0 to PC7
PA0 to PA7
8
PORT E
INT0
INT1
INT2
NMI/INT3
2
PORT A
PORT B
PORT C
PORT D
PORT F
PORT H
Block Diagram
CXP83408/83412/83416, CXP83409/83413/83417
CXP83408/83412/83416, CXP83409/83413/83417
PD7/SEG23
PF0/SEG24
PF1/SEG25
PF2/SEG26
PF3/SEG27
PF4/SEG28
PF5/SEG29
VDD
TX
TEX
NC
PF6/SEG30
PF7/SEG31
PE0/INT0/EC
PE1/INT1
PE2/INT2
Pin Assignment (Top View) CXP83408/83412/83416 (QFP package)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
1
64
PD6/SEG22
PE4/RMC
2
63
PD5/SEG21
PE5/PWM0
3
62
PD4/SEG20
PE6/TO/ADJ
4
61
PD3/SEG19
PB0/CS1
5
60
PD2/SEG18
PB1/CS0
6
59
PD1/SEG17
PB2/SCK0
7
58
PD0/SEG16
PB3/SI0
8
57
SEG15
PB4/SO0
9
56
SEG14
PB5/SCK1
10
55
SEG13
PE3/INT3/NMI
PB6/SI1
11
54
SEG12
PB7/SO1
12
53
SEG11
PC0
13
52
SEG10
PC1
14
51
SEG9
PC2
15
50
SEG8
PC3
16
49
SEG7
PC4
17
48
SEG6
PC5
18
47
SEG5
PC6
19
46
SEG4
PC7
20
45
SEG3
PH0/PWM1
21
44
SEG2
PA0/AN0
22
43
SEG1
PA1/AN1
23
42
SEG0
PA2/AN2
24
41
COM3
Note) NC (Pin 75) is always connected to VDD.
–3–
COM2
COM1
COM0
VLC1
VLC2
VLC3
VL
VSS
XTAL
EXTAL
RST
PA7/AN7
PA6/AN6
PA5/AN5
PA4/AN4
PA3/AN3
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
CXP83408/83412/83416, CXP83409/83413/83417
PD5/SEG21
PD6/SEG22
PD7/SEG23
PF0/SEG24
PF1/SEG25
PF2/SEG26
PF3/SEG27
PF4/SEG28
PF5/SEG29
VDD
TX
TEX
NC
PF6/SEG30
PF7/SEG31
PE0/INT0/EC
PE1/INT1
PE2/INT2
PE3/INT3/NMI
PE4/RMC
Pin Assignment (Top View) CXP83408/83412/83416 (LQFP package)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
PE5/PWM0
1
60
PD4/SEG20
PE6/TO/ADJ
2
59
PD3/SEG19
PB0/CS1
3
58
PD2/SEG18
PB1/CS0
4
57
PD1/SEG17
PB2/SCK0
5
56
PD0/SEG16
PB3/SI0
6
55
SEG15
PB4/SO0
7
54
SEG14
PB5/SCK1
8
53
SEG13
PB6/SI1
9
52
SEG12
PB7/SO1
10
51
SEG11
PC0
11
50
SEG10
PC1
12
49
SEG9
PC2
13
48
SEG8
PC3
14
47
SEG7
PC4
15
46
SEG6
PC5
16
45
SEG5
PC6
17
44
SEG4
PC7
18
43
SEG3
PH0/PWM1
19
42
SEG2
PA0/AN0
20
41
SEG1
Note) NC (Pin 73) is always connected to VDD.
–4–
SEG0
COM3
COM2
COM1
VLC1
COM0
VLC2
VLC3
VL
VSS
XTAL
RST
EXTAL
PA7/AN7
PA6/AN6
PA5/AN5
PA4/AN4
PA3/AN3
PA2/AN2
PA1/AN1
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
CXP83408/83412/83416, CXP83409/83413/83417
PD5/SEG21
PD6/SEG22
PD7/SEG23
PF0/SEG24
PF1/SEG25
PF2/SEG26
PF3/SEG27
PF4/SEG28
PF5/SEG29
VDD
TX
TEX
NC
PF6/SEG30
PF7/SEG31
PE0/INT0/EC
PE1/INT1
PE2/INT2
PE3/INT3/NMI
PE4/RMC
Pin Assignment (Top View) CXP83409/83413/83417 (QFP package)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
PE5/PWM0
1
60
PD4/SEG20
PE6/TO/ADJ
2
59
PD3/SEG19
PB0/CS1
3
58
PD2/SEG18
PB1/CS0
4
57
PD1/SEG17
PB2/SCK0
5
56
PD0/SEG16
PB3/SI0
6
55
SEG15
PB4/SO0
7
54
SEG14
PB5/SCK1
8
53
SEG13
PB6/SI1
9
52
SEG12
PB7/SO1
10
51
SEG11
PC0
11
50
SEG10
PC1
12
49
SEG9
PC2
13
48
SEG8
PC3
14
47
SEG7
PC4
15
46
SEG6
PC5
16
45
SEG5
PC6
17
44
SEG4
PC7
18
43
SEG3
PH0/PWM1
19
42
SEG2
20
41
SEG1
Note) NC (Pin 73) is always connected to VDD.
–5–
SEG0
COM3
COM2
COM1
VLC1
COM0
VLC2
VLC3
VL
VSS
XTAL
RST
EXTAL
PA7/AN7
PA6/AN6
PA5/AN5
PA4/AN4
PA3/AN3
PA2/AN2
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
PA1/AN1
PA0/AN0
CXP83408/83412/83416, CXP83409/83413/83417
Pin Description
Symbol
I/O
PA0/AN0
to
PA7/AN7
I/O/Analog input
PB0/CS1
I/O/Input
PB1/CS0
I/O/Input
PB2/SCK0
I/O/I/O
PB3/SI0
I/O/Input
PB4/SO0
I/O/Output
PB5/SCK1
I/O/I/O
PB6/SI1
I/O/Input
PB7/SO1
I/O/Output
PC0 to PC7
I/O
PE0/INT0/EC
Input/Input/Input
PE1/INT1
Input/Input
PE2/INT2
Input/Input
PE3/INT3/NMI Input/Input/Input
Functions
(Port A)
8-bit I/O port. I/O can be
set in a unit of single bits.
Incorporation of pull-up
resistor can be set
through the software in a
unit of 4 bits.
(8 pins)
Analog inputs to A/D converter.
(8 pins)
Chip select input for serial interface (CH1).
(Port B)
8-bit I/O port. I/O can be
set in a unit of single bits.
Incorporation of pull-up
resistor can be set
through the software in a
unit of 4 bits.
(8 pins)
Chip select input for serial interface (CH0).
Serial clock I/O (CH0).
Serial data input (CH0).
Serial data output (CH0).
Serial clock I/O (CH1).
Serial data input (CH1).
Serial data output (CH1).
(Port C)
8-bit I/O port. I/O can be set in a unit of single bits. Capable of driving
12mA sync current. Incorporation of pull-up resistor can be set through
the software in a unit of 4 bits.
(8 pins)
External event inputs
for timer/counter.
External interruption
request input. (4 pins)
(Port E)
7-bit port. Lower 5 bits
are for inputs; upper
2 bits are for outputs.
(7 pins)
Non-maskable intrruption
request input.
Remote control receiving circuit input.
PE4/RMC
Input/Input
PE5/PWM0
Output/Output
14-bit PWM output.
PE6/TO/ADJ
Output/Output/
Output
Rectangular wave output for 8-bit timer/
counter and 32kHz oscillation frequency
divider output.
PH0/PWM1
I/O/Output
(Port H)
1-bit I/O port. Incorporation
of pull-up resistor can be
set through the software.
(1 pin)
–6–
8-bit PWM output.
CXP83408/83412/83416, CXP83409/83413/83417
Symbol
I/O
PD0/SEG16
to
PD7/SEG23
Output/Output
PF0/SEG24
to
PF7/SEG31
Output/Output
Functions
(Port D)
8-bit output port.
(8 pins)
(Port F)
8-bit output port.
(8 pins)
SEG0 to SEG15 Output
LCD segment signal output.
COM0 to COM3 Output
LCD common signal output.
VLC1 to VLC3
LCD bias power supply.
LCD segment signal output.
(16 pins)
Control pin to cutt off the current flowing to external LCD bias resistor
during standby.
VL
Output
EXTAL
Input
XTAL
Output
TEX
Input
TX
Output
Crystal connectors for 32kHz timer/counter clock generation circuit.
For usage as event counter, connect clock oscillation source to TEX,
and leave TX open.
RST
Input
Low-level active, system reset.
Crystal connectors for system clock oscillation. When the clock is
supplied externally, input to EXTAL; opposite phase clock should be
input to XTAL.
NC
NC. Under normal operating conditions, connect to VDD.
VDD
Positive power supply.
Vss
GND.
–7–
CXP83408/83412/83416, CXP83409/83413/83417
I/O Circuit Format for Pins
Pin
Circuit format
When reset
Port A
∗
Pull-up resistor
“0” when reset
Port A data
PA0/AN0
to
PA7/AN7
Port A direction
IP Input protection
circuit
“0” when reset
Hi-Z
Data bus
RD (Port A)
Port A input selection
Input multiplexer
“0” when reset
A/D converter
∗ Pull-up resistors
approx. 100kΩ
8 pins
Port B
∗
Pull-up resistor
“0” when reset
Port B data
PB0/CS1
PB1/CS0
PB3/SI0
PB6/SI1
Port B direction
IP
Hi-Z
“0” when reset
Schmitt input
Data bus
RD (Port B)
CS1
CS0
SI0
SI1
4 pins
∗ Pull-up transistors
approx. 100kΩ
Port B
∗
Pull-up resistor
“0” when reset
SCK OUT
Output enable
Port B output
selection
PB2/SCK0
PB5/SCK1
“0” when reset
Hi-Z
Port B data
IP
Port B direction
“0” when reset
Schmitt input
Data bus
RD (Port B)
2 pins
∗ Pull-up transistors
approx. 100kΩ
SCK in
–8–
CXP83408/83412/83416, CXP83409/83413/83417
Pin
Circuit format
When reset
Port B
∗
Pull-up resistor
“0” when reset
SO
Output enable
Port B output
selection
“0” when reset
PB4/SO0
PB7/SO1
Port B data
Hi-Z
IP
Port B direction
“0” when reset
Data bus
RD (Port B)
∗ Pull-up transistors
approx. 100kΩ
2 pins
Port C
∗2
Pull-up resistor
“0” when reset
Port C data
PC0 to PC7
∗1
Port C direction
IP
Hi-Z
“0” when reset
Data bus
∗1 Large current 12mA
∗2 Pull-up transistors
approx. 100kΩ
RD (Port C)
8 pins
PE0/INT0/EC
PE1/INT1
PE2/INT2
PE3/INT3/NMI
PE4/RMC
Port E
Schmitt input
IP
INT0/EC
INT1
INT2
INT3/NMI
RMC
Data bus
5 pins
RD (Port E)
–9–
Hi-Z
CXP83408/83412/83416, CXP83409/83413/83417
Pin
Circuit format
When reset
Port E
PWM0
Port E output selection
“0” when reset
PE5/PWM0
High level
Port E data
“1” when reset
Data bus
1 pin
RD (Port E)
Port E
∗1
Internal reset signal
Port E data
“1” when reset
MPX
TO
∗2
PE6/TO/ADJ
High level
with pull-up
transistor ON
resistor when
reset
( )
ADJ16K
ADJ2K
Port E output selection (upper)
Port E output selection (lower)
∗1 Pull-up transistors approx. 150kΩ.
∗2 ADJ signals are frequency divider outputs
for 32kHz oscillation frequency adjustment.
ADJ2K provides usage as buzzer output.
TO Output enable
1 pin
Port H
AAAA
AAAA
AAAA
AAAA
AAAA
∗
Pull-up resistor
“0” when reset
AA
AAAA
PWM1
Port H output selection
PH0/PWM1
“0” when reset
Port H data
IP
Port H direction
“0” when reset
Data bus
1 pin
∗ Pull-up transistors
RD (Port H)
approx. 100kΩ
– 10 –
Hi-Z
CXP83408/83412/83416, CXP83409/83413/83417
Pin
Circuit format
When reset
Port D
Port F
Port data
PD0 to PD7
PF0 to PF7
PD7 to PD4 by a bit unit
PD3 to PD0 by 4-bit unit
PF7 to PF0
Segment
output
(VDD level)
Port/segment output
selection
“0” when reset
Segment data
Segment
driver
24 pins
Segment
VCH
SEG0 to SEG15
VDD level
VCL
16 pins
Common
VDD
VLC1
COM0 to COM3
VDD level
VLC2
VLC3
4 pins
VL
LCD control
(DSP bit)
1 pin
Hi-Z
“0” when reset
– 11 –
CXP83408/83412/83416, CXP83409/83413/83417
Pin
EXTAL
XTAL
Circuit format
When reset
• Diagram shows circuit
composition during oscillation.
EXTAL
IP
IP
• Feedback resistor is removed
during stop, and XTAL
becomes “High” level.
Oscillation
XTAL
2 pins
• Diagram shows circuit
composition during oscillation.
TEX
TX
TEX
IP
IP
• When the operation of the oscillation circuit is
stopped by the software, the feedback
resistor is removed and TEX and TX become
“Low” level and “High” level respectively.
TX
2 pins
AA
AA
Oscillation
Pull-up resistor
RST
Mask option
Low level
OP
IP
1 pin
– 12 –
Schmitt input
CXP83408/83412/83416, CXP83409/83413/83417
Absolute Maximum Ratings
Item
Supply voltage
(Vss = 0V reference)
Symbol
VDD
Rating
Unit
–0.3 to +7.0
V
Input voltage
VLC1, VLC2,
–0.3 to +7.0∗1
VLC3
–0.3 to +7.0∗1
VIN
Output voltage
VOUT
High level output current
High level total output current
LCD bias voltage
Remarks
V
V
–0.3 to +7.0∗1
V
IOH
–5
mA
Output (value per pin)
∑IOH
–50
mA
Total for all output pins
IOL
15
mA
IOLC
20
mA
All pins excluding large current output
(value per pin)
Large current outputs (value per pin∗2)
Low level total output current
∑IOL
100
mA
Total for all output pins
Operating temperature
Topr
–20 to +75
°C
Storage temperature
Tstg
–55 to +150
°C
600
mW
QFP-80P-L01
380
mW
LQFP-80P-L01
380
mW
QFP-80P-L03
Low level output current
Allowable power dissipation
PD
∗1 VIN and VOUT must not exceed VDD + 0.3V.
∗2 The large current drive transistor is the N-ch transistor of Port C (PC).
Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should
be conducted under the recommended operating conditions. Exceeding these conditions may adversely
affect the reliability of the LSI.
– 13 –
CXP83408/83412/83416, CXP83409/83413/83417
Recommended Operating Conditions
Item
Supply voltage
Symbol
(Vss = 0V reference)
Min.
Max.
4.5
5.5
3.5
5.5
2.7
5.5
Guaranteed operation range with TEX clock
2.5
5.5
Guaranteed data hold range during STOP
Vss
VDD
V
LCD power supply range∗4
VIH
0.7VDD
VDD
V
∗1
VIHS
0.8VDD
VDD
V
VIHEX
VDD – 0.4
VDD + 0.3
V
Hysteresis input∗2
EXTAL∗3
VIL
0
0.3VDD
V
∗1
VILS
0
0.2VDD
V
VILEX
–0.3
0.4
V
Topr
–20
+75
°C
VDD
Unit
Remarks
During 1/2 and 1/4 frequency division
operating modes guaranteed operation range
V
During 1/16 frequency division operating mode
or sleep mode quaranteed operation range
VLC1
LCD bias voltage
VLC2
VLC3
High level input voltage
Low level input voltage
Operating temperature
∗1
∗2
∗3
∗4
Hysteresis input∗2
EXTAL∗3
Value for each pin of normal input ports (PA, PB4, PB7, PC and PH0).
Value of the following pins: RST, CS0, CS1, SI0, SI1, SCK0, SCK1, EC/INT0, INT1, INT2, NMI/INT3, and RMC.
Specifies only during external clock input.
Optimal values are determined by LCD used.
– 14 –
CXP83408/83412/83416, CXP83409/83413/83417
Electrical Characteristics
DC Characteristics
Item
Symbol
High level
VOH
output current
Low level
output current
(Ta = –20 to +75°C, Vss = 0V reference)
VOL
Pins
PA, PB,
PC, PD∗1,
PE5, PE6,
PF, PH0,
VL (VoL only)
PC
IIHE
IILE
EXTAL
IIHT
Input current
IILT
IILR
IIL
IIH
I/O leakage
current
IIZ
Common
output
impedance
RCOM
Segment
output
impedance
RSEG
TEX
RST∗2
PA to PC∗3,
PH∗3,
PE0 to PE4,
RST∗2
IDDS1
IDDS2
Max.
Unit
V
VDD = 4.5V, IOH = –1.2mA
3.5
V
VDD = 4.5V, IOL = 1.8mA
0.4
V
VDD = 4.5V, IOL = 3.6mA
0.6
V
VDD = 4.5V, IOL = 12.0mA
1.5
V
VDD = 5.5V, VIH = 5.5V
0.5
40
V
VDD = 5.5V, VIL = 0.4V
–0.5
–40
µA
VDD = 5.5V, VIH = 5.5V
0.1
10
µA
–0.1
–10
µA
–1.5
–400
mA
–45
µA
VDD = 5.5V,
VIL = 0.4V
VDD = 4.5V, VIH = 4.0V
–2.78
µA
VDD = 5.5V,
VI = 0, 5.5V
High-speed mode operation
(1/2 frequency divider clock)
VDD = 5.5V, 10MHz crystal oscillation
(C1 = C2 = 15pF)
VDD = 3V, 32kHz crystal oscillation
(C1 = C2 = 47pF)
VDD
Typ.
4.0
VDD = 5V,
VLC1 = 3.75V
SEG0 to SEG15, VLC2 = 2.5V
VLC3 = 1.25V
SEG16 to
∗
1
SEG31
IDD2
Min.
VDD = 4.5V, IOH = –0.5mA
COM0
to
COM3
IDD1
Supply
current∗4
Conditions
±10
µA
3
5
kΩ
5
15
kΩ
18
40
mA
35
100
µA
1.1
8
mA
9
30
µA
10
µA
SLEEP mode
VDD = 5.5V, 10MHz crystal oscillation
(C1 = C2 = 15pF)
VDD = 3V, 32kHz crystal oscillation
(C1 = C2 = 47pF)
STOP mode
IDDS3
VDD = 5.5V termination of 10MHz
and 32kHz crystal oscillation
– 15 –
CXP83408/83412/83416, CXP83409/83413/83417
Item
Input capacity
Symbol
CIN
Pins
PA to PC,
PE1 to PE4,
EXTAL, TEX,
RST
Conditions
Clock 1MHz
0V for all pins excluding
measured pins
Min.
Typ.
Max.
Unit
10
20
pF
∗1 Common pins of PD0/SEG16 to PD7/SEG23, PF0/SEG24, PF7/SEG31, PD and PF are the case when the
common pin is selected as port; SEG16 to SEG31 is when the common pin is selected as segment output.
∗2 RST specifies the input current when pull-up resistor has been selected; leakage current when no resistor
has been selected.
∗3 PA to PC, and PH0 specify the input current when pull-up resistor has been selected; leakage current when
no resistor has been selected. (PE0 to PE4 specify the leakage current.)
∗4 When all output pins are left open.
– 16 –
CXP83408/83412/83416, CXP83409/83413/83417
AC Characteristics
(1) Clock timing
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Item
Symbol
System clock frequency
fC
System clock input
pulse width
Event count input clock
rise and fall time
tXL,
tXH
tCR,
tCF
tEH,
tEL
tER,
tEF
System clock frequency
fC
Event count input clock
input pulse width
tTL,
tTH
tTR,
tTF
System clock input
rise and fall time
Event count input clock
pulse width
Event count input clock
rise and fall time
Pin
Conditions
Min.
XTAL
EXTAL
Fig. 1, Fig. 2
EXTAL
Fig. 1, Fig. 2
External clock drive
EXTAL
Fig. 1, Fig. 2
External clock drive
EC
Fig. 3
EC
Fig. 3
TEX
TX
VDD = 2.7 to 5.5V
Fig. 2 (32kHz clock
applied condition)
TEX
Fig. 3
TEX
Fig. 3
Typ.
Max.
Unit
10
MHz
1
ns
37.5
200
tsys + 50∗1
ns
ns
20
ms
kHz
32.768
µs
10
20
ms
∗1 tsys indicates the three values below according to the upper two bits (CPU clock selection) of the clock
control registor (CLC: 00FEH).
tsys (ns) = 2000/fc (upper two bits = “00”), 4000/fc (upper two bits = “01”), 16000/fc (upper two bits = “11”)
1/fc
Fig. 1. Clock timing
VDD – 0.4V
EXTAL
0.4V
tCF
tXH
tXL
tCR
Fig. 2. Clock applied conditions
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA AAAAAAAA
Crystal oscillation
Ceramic oscillation
EXTAL
External clock
EXTAL
XTAL
C1
C2
32kHz clock applied condition
Crystal oscillation
TEX
XTAL
74HC04
TX
C1
C2
Fig. 3. Event count clock timing
0.8VDD
TEX
EC
0.2VDD
tEH
tTH
tEF
tTF
– 17 –
tEL
tTL
tER
tTR
CXP83408/83412/83416, CXP83409/83413/83417
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
(2) Serial transfer
Item
Symbol
CS0 ↓ → SCK0 (CS1 ↓ → SCK1)
delay time
tDCSK
CS0 ↑ → SCK0 (CS1 ↑ → SCK1)
floating delay time
tDCSKF SCK0 Chip select transfer mode
CS0 ↓ → SO0 (CS1 ↓ → SO1)
delay time
tDCSO
CS0 ↑ → SO0 (CS1 ↑ → SO1)
floating delay time
Pin
Conditions
Min.
SCK0 Chip select transfer mode
(SCK1) (SCK0 (SCK1) = output mode)
Unit
tsys + 200 ns
tsys + 200 ns
(SCK1) (SCK0 (SCK1) = output mode)
SO0
(SO1)
Max.
Chip select transfer mode
tsys + 200 ns
tDCSOF SO0
Chip select transfer mode
tsys + 200 ns
CS0 (CS1) high level width
tWHCS CS0
Chip select transfer mode
SCK0 (SCK1) cycle time
tKCY
SCK0 (SCK1)
high and low level widths
(SO1)
tsys + 200
ns
SCK0 Input mode
(SCK1) Output mode
2tsys + 200
ns
16000/fc
ns
tKH
tKL
SCK0 Input mode
(SCK1) Output mode
tsys + 100
ns
8000/fc – 50
ns
SI0 (SI1) input setup time
(for SCK0↑ (SCK1↑) )
SI0
(SI1)
SCK0 (SCK1) input mode
100
ns
tSIK
SCK0 (SCK1) output mode
200
ns
SI0 (SI1) input hold time
(for SCK0↑ (SCK1↑) )
SI0
(SI1)
SCK0 (SCK1) input mode
tsys + 200
ns
tKSI
100
ns
SCK0 ↓ → SO0 (SCK1 ↓ → SO1)
delay time
tKSO
SO0
(SO1)
SCK0 (SCK1) input mode
(CS1)
SCK0 (SCK1) output mode
SCK0 (SCK1) output mode
tsys + 200
ns
100
ns
Note 1) tsys indicates the three values below according to the upper two bits (CPU clock selection) of the
clock control register (CLC: 00FEH).
tsys (ns) = 2000/fc (upper two bits = “00”), 4000/fc (upper two bits = “01”), 16000/fc (upper two bits = “11”)
Note 2) The load condition for the SCK0 (SCK1) output mode, SO0 (SO1) output delay time is 50pF + 1TTL.
– 18 –
CXP83408/83412/83416, CXP83409/83413/83417
Fig. 4. Serial transfer CH0 timing
tWHCS
CS0
(CS1)
0.8VDD
0.2VDD
tKCY
tDCSK
tKL
tDCSKF
tKH
0.8VDD
0.8VDD
SCK0
(SCK1)
0.2VDD
tSIK
tKSI
0.8VDD
Input
data
SI0
(SI1)
0.2VDD
tDCSO
tKSO
tDCSOF
0.8VDD
SO0
(SO1)
Output data
0.2VDD
– 19 –
CXP83408/83412/83416, CXP83409/83413/83417
(3) A/D converter characteristics
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, AVREF = 4.0 to AVDD, Vss = 0V reference)
Item
Symbol
Pin
Conditions
Min.
Typ.
Max.
Unit
8
Bits
±3
LSB
Resolution
Linearity error
Ta = 25°C
VDD = 5.0V
VSS = 0V
Zero transition voltage VZT∗1
Full-scale transition
voltage
VFT∗2
Conversion time
Sampling time
tCONV
tSAMP
Analog input voltage
VIAN
–10
10
70
mV
4910
4970
5030
mV
160/fADC∗3
12/fADC∗3
0
AN0 to AN7
µs
µs
VDD + 0.3
V
Fig. 5. Definition of A/D converter terms
Digital conversion value
FFH
FEH
∗1 VZT: Value atwhich the digital conversion value changes
from 00H to 01H and vice versa.
∗2 VFT: Value at which the digital conversion value changes
from FEH to FFH and vice versa.
∗3 fADC indicates the below values due to the contents of bit 6
(CK3) of the A/D control registor (ADC: 00F9H) and bit 7
(PCK1) and bit 6 (PCK0) of the clock control resistor (CLC:
00FEH).
Linearity error
01H
CKS
00H
VFT
VZT
Analog input
PCK1, PCK0
0 (φ/2 selection)
0 (φ selection)
00 (φ = fEX/2)
fADC = fc/2
fADC = fc
01 (φ = fEX/4)
fADC = fc/4
fADC = fc/2
11 (φ = fEX/16)
fADC = fc/16
fADC = fc/8
– 20 –
CXP83408/83412/83416, CXP83409/83413/83417
(4) Interruption, reset input
Item
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Symbol
Pin
External interruption
high and low level widths
tIH
tIL
INT0
INT1
INT2
NMI/INT3
Reset input low level width
tRSL
Conditions
Min.
Max.
Unit
1
µs
RST
32/fc
µs
tIH
tIL
Fig 6. Interruption input timing
0.8VDD
INT0
INT1
INT2
NMI/INT3
(NMI is specified only for
the falling edge)
0.2VDD
tIL
tIH
Fig. 7. RST input timing
tRSL
RST
0.2VDD
– 21 –
CXP83408/83412/83416, CXP83409/83413/83417
Appendix
Fig. 8. SPC700 Series recommended oscillation circuit
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
(i) Main clock
EXTAL
EXTAL
XTAL
Rd
(iii) Sub clock
EXTAL
TEX
XTAL
Rd
C2
C1
AAAAA
AAAAA
AAAAA
(ii) Main clock
XTAL
TX
Rd
C2
C1
C 1 C2
Model
Manufacturer
MURATA
MFG
CO., LTD.
fc (MHz)
CSA4.19MG
4.19
CSA8.00MG
8.00
CSA10.0MT
10.00
CST4.19MGW∗1
CST8.00MTW∗1
CST10.00MTW∗1
C1 (pF)
C2 (pF)
HC-49/U03
30
30
(ii)
8.00
10.00
15
8.00
15
8.00
22
22
560
18
18
0
10.00
Models with an asterisk (∗1) have the built-in ground capacitance (C1, C2).
Mask Option Table
Item
Reset pin pull-up resistor
Content
Non-existent
Existent
Package Table
Product name
2.2k
470
4.19
HC-49/U (-S)
0
4.19
10.00
KINSEKI
LTD.
Circuit
example
(i)
4.19
RIVER
ELETEC
CO., LTD.
Rd (Ω)
Package
CXP83408/83412/83416
80-pin plastic QFP/LQFP
CXP83409/83413/83417
80-pin plastic QFP (0.65mm pitch)
– 22 –
(i)
CXP83408/83412/83416, CXP83409/83413/83417
Characteristic Curves
IDD vs. VDD
IDD vs. fc
(fc = 10MHz, Ta = 25°C, Typical)
(VDD = 5V, Ta = 25°C, typical)
1/2 dividing mode
20.0
SLEEP mode
20
5.0
IDD – Supply current [mA]
IDD – Supply current [mA]
10.0
1.0
0.5
32kHz mode
(instruction)
0.1
(100µA)
0.05
(50µA)
1/2 dividing mode
15
10
32kHz
SLEEP mode
5
0.01
(10µA)
SLEEP mode
2
3
4
6
5
7
10
5
fc – System clock [MHz]
0
VDD – Supply voltage [V]
Package Outline
Unit : mm
CXP83408/83412/83416
80PIN QFP (PLASTIC)
23.9 ± 0.4
+ 0.1
0.15 – 0.05
+ 0.4
20.0 – 0.1
64
0.15
41
65
16.3
17.9 ± 0.4
+ 0.4
14.0 – 0.1
40
A
+ 0.2
0.1 – 0.05
25
1
24
0.8
0.12
M
+ 0.15
0.35 – 0.1
+ 0.35
2.75 – 0.15
0° to 10°
DETAIL A
PACKAGE STRUCTURE
SONY CODE
QFP-80P-L01
EIAJ CODE
∗QFP080-P-1420-A
JEDEC CODE
PACKAGE MATERIAL
EPOXY RESIN
LEAD TREATMENT
SOLDER PLATING
LEAD MATERIAL
COPPER / 42 ALLOY
PACKAGE WEIGHT
1.6g
– 23 –
0.8 ± 0.2
80
16
CXP83408/83412/83416, CXP83409/83413/83417
CXP83408/83412/83416
80PIN LQFP (PLASTIC)
14.0 ± 0.2
∗
12.0 ± 0.1
60
41
40
(13.0)
61
0.5 ± 0.2
A
21
(0.22)
80
1
20
+ 0.08
0.18 – 0.03
0.5 ± 0.08
+ 0.2
1.5 – 0.1
+ 0.05
0.127 – 0.02
0.1
0.5 ± 0.2
0.1 ± 0.1
0° to 10°
NOTE: Dimension “∗” does not include mold protrusion.
DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY / PHENOL RESIN
SONY CODE
LQFP-80P-L01
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
∗QFP080-P-1212-A
LEAD MATERIAL
42 ALLOY
PACKAGE WEIGHT
0.5g
JEDEC CODE
CXP83409/83413/83417
80PIN QFP (PLASTIC)
+ 0.35
1.5 – 0.15
+ 0.1
0.127 – 0.05
16.0 ± 0.4
+ 0.4
14.0 – 0.1
60
0.1
41
40
80
21
(15.0)
61
+ 0.15
0.3 – 0.1
20
± 0.12 M
0° to 10°
0.5 ± 0.2
1
0.65
+ 0.15
0.1 – 0.1
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
QFP-80P-L03
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
LQFP080-P-1414
LEAD MATERIAL
COPPER / 42 ALLOY
PACKAGE WEIGHT
0.6g
JEDEC CODE
– 24 –
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