Sony CXP84332M Cmos 8-bit single chip microcomputer Datasheet

CXP84332M/84340M
CMOS 8-bit Single Chip Microcomputer
Description
CXP84332M/84340M is a CMOS 8-bit single chip
microcomputer integrating on a single chip an A/D
converter, serial interface, timer/counter, time base
timer, capture timer/counter, remote control reception
circuit, PWM output, and 32kHz timer/counter besides
the basic configurations of 8-bit CPU, ROM, RAM,
and I/O port.
The CXP84332M/84340M also provides a sleep/stop
function that enables lower power consumption.
80 pin QFP (Plastic)
Features
• Wide-range instruction system (213 instructions) to cover various types of data
— 16-bit arithmetic/multiplication and division/boolean bit operation instructions
• Minimum instruction cycle
200ns at 20MHz operation
122µs at 32kHz operation
• Incorporated ROM capacity
32K bytes (CXP84332M)
40K bytes (CXP84340M)
• Incorporated RAM capacity
1120 bytes
• Peripheral functions
— A/D converter
8 bits, 8 channels, successive approximation method
(Conversion time of 16µs/20MHz)
— Serial interface
8-bit, 8-stage FIFO incorporated
(Auto transfer for 1 to 8 bytes), 1 channel
8-bit clock synchronization, 1 channel
— Timers
8-bit timer
8-bit timer/counter
19-bit time base timer
16-bit capture timer/counter
32kHz timer/counter
— Remote control reception circuit 8-bit pulse measuring counter, 6-stage FIFO
— PWM output
14 bits, 1 channel
• Interruption
15 factors, 15 vectors, multi-interruption possible
• Standby mode
SLEEP/STOP
• Package
80-pin plastic QFP
• Piggyback/evaluation chip
CXP84300 80-pin ceramic QFP
Structure
Silicon gate CMOS IC
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E95X06-ST
AVREF
–2–
TO
CINT
EC1
ADJ
8 BIT TIMER/COUNTER 0
EC0
16 BIT CAPTURE
TIMER/COUNTER2
8 BIT TIMER 1
SERIAL INTERFACE UNIT 1
FIFO
SI1
SO1
SCK1
SERIAL
INTERFACE
UNIT 0
CS0
SI0
SO0
SCK0
FIFO
14 BIT PWM GENERATOR
A/D CONVERTER
REMOCON
8
AVss
RMC
PWM
AN0 to AN7
2
2
2
INT0
INT1
INT2
INT3
INTERRUPT CONTROLLER
Block Diagram
PRESCALER/
TIME BASE TIMER
ROM
32K/40K BYTES
SPC700
CPU CORE
TEX
TX
EXTAL
XTAL
RST
VDD
Vss
32kHz
TIMER/COUNTER
RAM
1120 BYTES
CLOCK
GENERATOR/
SYSTEM CONTROL
8
8
8
PI0 to PI7
PH0 to PH7
PG0 to PG7
PF0 to PF7
PE4 to PE5
2
8
PE0 to PE3
PD0 to PD7
PC0 to PC7
PB7
PB0 to PB6
PA0 to PA7
4
8
8
7
8
CXP84332M/84340M
PORT I PORT H PORT G PORT F PORT E PORT D PORT C PORT B PORT A
NMI
CXP84332M/84340M
PI5
PI6
PI7
PG0
PG1
PG2
PG3
VDD
NC
PG4
PG5
PG6
PG7
PF0
PF1
PF2
Pin Assignment (Top View)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
1
64
PI4
PF4
2
63
PI3/INT3
PF5
3
62
PI2/INT2
PF6
4
61
PI1/INT1
PF7
5
60
PI0/INT0
PD0
6
59
PE5/TO/ADJ
PD1
7
58
PE4/PWM
PD2
8
57
PE3/NMI
PD3
9
56
PE2/RMC
PD4
10
55
PE1/EC1
PD5
11
54
PE0/EC0
PD6
12
53
PB7/SO1
PD7
13
52
PB6/SI1
PC0
14
51
PB5/SCK1
PC1
15
50
PB4/SO0
PC2
16
49
PB3/SI0
PC3
17
48
PB2/SCK0
PC4
18
47
PB1/CS0
PC5
19
46
PB0/CINT
PC6
20
45
PA7/AN7
PC7
21
44
PA6/AN6
PH0
22
43
PA5/AN5
PH1
23
42
PA4/AN4
PH2
24
41
PA3/AN3
Note) NC (Pin 73) must be connected to VDD.
–3–
PA2/AN2
PA1/AN1
PA0/AN0
AVSS
AVREF
TEX
TX
VSS
XTAL
EXTAL
RST
PH7
PH6
PH5
PH4
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
PH3
PF3
CXP84332M/84340M
Pin Description
Pin code
I/O
PA0/AN0
to
PA7/AN7
I/O/Analog input
PB0/CINT
I/O/Input
PB1/CS0
I/O/Input
PB2/SCK0
I/O/I/O
PB3/SI0
I/O/Input
PB4/SO0
I/O/Output
PB5/SCK1
I/O/I/O
PB6/SI1
I/O/Input
PB7/SO1
Output/Output
Functions
(Port A)
8-bit I/O port. I/O can be
set in a unit of single bits.
Incorporation of the
pull-up resistance can be
set through the software
in a unit of 4 bits.
(8 pins)
(Port B)
Lower 7-bit I/O port in
which I/O can be set in a
unit of single bits. Also,
an uppermost bit (PB7)
exclusively for output.
Incorporation of pull-up
resistor can be set
through the software in a
unit of 4 bits.
(8 pins)
Analog inputs to A/D converter.
(8 pins)
External capture input to 16-bit timer/counter.
Chip select input for serial interface (CH0).
Serial clock I/O (CH0).
Serial data input (CH0).
Serial data output (CH0).
Serial clock I/O (CH1).
Serial data input (CH1).
Serial data output (CH1).
I/O
(Port C)
8-bit I/O port. I/O can be set in a unit of single bits. Capable of driving
12mA sync current. Incorporation of pull-up resistor can be set through
the software in a unit of 4 bits.
(8 pins)
PD0 to PD7
I/O
(Port D)
8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of pullup resistor can be set through the software in a unit of 4 bits.
(8 pins)
PE0/EC0
Input/Input
PE1/EC1
Input/Input
PE2/RMC
Input/Input
PE3/NMI
Input/Input
PE4/PWM
Output/Output
PE5/TO/ADJ
Output/Output/
Output
PC0 to PC7
PF0 to PF7
I/O
External event inputs for timer/counter.
(2 pins)
(Port E)
6-bit port. Lower 4 bits
are for inputs; upper
2 bits are for outputs.
(6 pins)
Remote control reception circuit input.
Non-maskable interruption request input.
14-bit PWM output.
Rectangular wave output for 16-bit
timer/counter and output for 32kHz
oscillation frequency demultiplication.
(Port F)
8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of
pull-up resistor can be set through the software in a unit of 4 bits.
(8 pins)
–4–
CXP84332M/84340M
Pin code
I/O
Functions
I/O
(Port G)
8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of pullup resistor can be set through the software in a unit of 4 bits.
(8 pins)
PH0 to PH7
I/O
(Port H)
8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of pullup resistor can be set through the software in a unit of 4 bits.
(8 pins)
PI0/INT0
to
PI3/INT3
I/O/Input
PI4 to PI7
I/O
EXTAL
Input
XTAL
Output
TEX
Input
TX
Output
Crystal connectors for 32kHz timer/counter clock oscillaton circuit.
For usage as event counter, input to TEX, and open TX.
RST
Input
Low-level active, system reset.
PG0 to PG7
NC
AVREF
(Port I)
8-bit I/O ports. I/O can be set in a unit of single
bits. Incorporation of pull-up resistor can be set
through the software in a unit of 4 bits.
(8 pins)
External interruption
request inputs.
(4 pins)
Crystal connectors for system clock oscillation. When the clock is supplied
externally, input to EXTAL; opposite phase clock should be input to XTAL.
NC. Under normal operating conditions, connect to VDD.
Input
Reference voltage input for A/D converter.
AVss
A/D converter GND.
VDD
Vcc supply.
Vss
GND
–5–
CXP84332M/84340M
I/O Circuit Format for Pins
Pin
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
When reset
Circuit format
Port A
∗
Pull-up resistance
"0" when reset
Port A data
PA0/AN0
to
PA7/AN7
Port A direction
"0" when reset
Data bus
AA
AA
AA
IP
Input protection
circuit
Hi-Z
RD (Port A)
Port A input selection
"0" when reset
A/D converter
8 pins
Port B
AAAA
AAAA
AAAA
AAAA
AAAA
Input multiplexer
∗ Pull-up transistors
approx. 10kΩ
∗
Pull-up resistance
"0" when reset
AA
AA
AA
Port B data
PB0/CINT
PB1/CS0
PB3/SI0
PB6/SI1
Port B direction
IP
"0" when reset
Data bus
Hi-Z
Schmitt input
RD (Port B)
CINT
CS0
SI0
SI1
4 pins
Port B
∗ Pull-up transistors
approx. 10kΩ
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
∗
Pull-up resistance
"0" when reset
SCK OUT
Output enable
AA
AA
AA
Port B output
selection
"0" when reset
PB2/SCK0
PB5/SCK1
IP
Port B data
Port B direction
"0" when reset
Schmitt input
Data bus
RD (Port B)
2 pins
SCK in
–6–
∗ Pull-up transistors
approx. 10kΩ
Hi-Z
CXP84332M/84340M
Pin
When reset
Circuit format
Port B
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
∗
Pull-up resistance
"0" when reset
SO
Output enable
AA
AA
AA
Port B output
selection
"0" when reset
PB4/SO0
IP
Port B data
Port B direction
Hi-Z
"0" when reset
Data bus
RD (Port B)
∗ Pull-up transistors
approx. 10kΩ
1 pin
Port B
Internal reset signal
SO
AAAA
AAAA
AAAA
AA(
Output enable
PB7/SO1
∗
Port B output
selection
"1" when reset
High level
with approx.
200kΩ
resistor
when reset
Port B data
∗ Pull-up transistors
approx. 200kΩ
Data bus
1 pin
RD (Port B)
Port C
AAAA
AAAA
AAAA
AAAA
AAAA
∗2
Pull-up resistance
"0" when reset
Port C data
PC0 to PC7
∗1
Port C direction
"0" when reset
Data bus
RD (Port C)
Port E
4 pins
AA
A
AA
A
IP
Hi-Z
∗1 Large current 12mA
∗2 Pull-up transistors
approx. 10kΩ
8 pins
PE0/EC0
PE1/EC1
PE2/RMC
PE3/NMI
)
AAAA
AAAA
Schmitt input
EC0
EC1
RMC/NMI
IP
Data bus
RD (Port E)
–7–
Hi-Z
CXP84332M/84340M
Pin
When reset
Circuit format
Port E
AAAA
AAAA
AAAA
AA
AA
PWM
Port E output
selection
"0" when reset
PE4/PWM
Port E data
High level
"1" when reset
Data bus
1 pin
RD (Port E)
Port E
PE5/TO/ADJ
AA
AAA
AA
AAA
AAA
AAA
AAA
Output enable
TO
ADJ16K
ADJ2K
Port E output
selection
Port E output
selection
"00" when reset
MPX
AA
Port E output
selection
"0" when reset
High level
Port E data
∗ ADJ signals are frequency dividing outputs
for 32kHz oscillation frequency adjustment
ADJ2K provides usage as buzzer output.
"1" when reset
Data bus
RD (Port E)
1 pin
Port D
Port F
Port G
Port H
PD0 to PD7
PF0 to PF7
PG0 to PG7
PH0 to PH7
PI4 to PI7
Port I
AAAAAA
AAAAAA
AAAAAA
AAAAAA
AAAAAA
∗
Pull-up resistance
"0" when reset
Ports D, F, G, H, I data
Ports D, F, G, H, I directon
"0" when reset
Data bus
RD (Ports D, F, G, H, I)
A
AA
A
AA
IP
∗ Pull-up transistors
approx. 10kΩ
36 pins
–8–
Hi-Z
CXP84332M/84340M
Pin
AAAA
AAAA
AAAA
AAAA
AAAA
When reset
Circuit format
Port I
∗
Pull-up resistance
A
AA
A
AA
"0" when reset
Port I data
PI0/INT0
to
PI3/INT3
Port I direction
IP
"0" when reset
Schmitt input
Data bus
RD (Port I)
INT0
INT1
INT2
INT3
4 pins
EXTAL
XTAL
2 pins
TEX
TX
2 pins
∗ Pull-up transistors
approx. 10kΩ
AA
AA
A
AA
AA
A
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
IP
EXTAL
Hi-Z
IP
• Diagram shows
circuit composition
during oscillation.
• Feedback resistor
is removed during stop.
Oscillation
XTAL
TEX
IP
IP
• Diagram shows
circuit composition
during oscillation.
Oscillation
• When the operation of the oscillation
circuit is stopped by the software, the
feedback resistor is removed, and TEX
and TX become “Low” level and “High”
level respectively.
TX
Pull-up resistance
RST
AA
Mask option OP
1 pin
AA
Schmitt input
IP
–9–
Low level
CXP84332M/84340M
Absolute Maximum Ratings
Item
(Vss = 0V reference)
Symbol
Supply voltage
Ratings
Unit
VDD
–0.3 to +7.0
V
AVSS
V
Remarks
Input voltage
VIN
–0.3 to +0.3
–0.3 to +7.0∗1
Output voltage
VOUT
–0.3 to +7.0∗1
V
High level output current
IOH
–5
mA
Output per pin
–50
mA
Total for all output pins
IOL
15
mA
IOLC
20
mA
Value per pin, excluding large current outputs
Value per pin∗2 for large current outputs
Low level total output current
∑IOL
100
mA
Total for all output pins
Operating temperature
Topr
–20 to +75
°C
Storage temperature
Tstg
–55 to +150
°C
Allowable power dissipation
PD
600
mW
High level total output current ∑IOH
Low level output current
V
∗1) VIN and VOUT must not exceed VDD + 0.3V.
∗2) The large current drive transistor is the N-ch transistor of Port C (PC).
Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should
be conducted under the recommended operating conditions. Exceeding these conditions may adversely
affect the reliability of the LSI.
Recommended Operating Conditions
Item
Supply voltage
High level input
voltage
Symbol
Min.
Max.
4.5
5.5
3.5
5.5
2.7
5.5
Guaranteed operation range with TEX clock
2.5
5.5
VIH
0.7VDD
VDD
V
Guaranteed data hold range during STOP
∗2
VIHS
0.8VDD
VDD
V
VDD
VIHEX
Low level input
voltage
Operating temperature
(Vss = 0V reference)
Unit
VDD – 0.4 VDD + 0.3
Remarks
Guaranteed operation range for high speed
mode∗1
V
Guaranteed operation range for low speed
mode∗1
V
Hysteresis input∗3
EXTAL∗4
∗2
VIL
0
0.3VDD
V
VILS
0
0.2VDD
V
VILEX
–0.3
0.4
V
Topr
–20
+75
°C
Hysteresis input∗3
EXTAL∗4
∗1) High speed mode is 1/2 frequency dividing clock selection; low-speed mode is 1/16 frequency dividing
clock selection.
∗2) Value for each pin of normal input ports (PA, PB3, PB4, PB6, PC, PD, PF to PH, PI4 to PI7).
∗3) Value of the following pins: RST, CINT, CS0, SCK0, SCK1, EC0, EC1, RMC, NMI, INT0, INT1, INT2,
INT3.
∗4) Specifies only during external clock input.
– 10 –
CXP84332M/84340M
Electrical Characteristics
DC Characteristics
Item
High level
output current
Low level
output current
(Ta = –20 to +75°C, Vss = 0V reference)
Symbol
Pins
VOH
PA to PD,
PE4, PE5,
PF to PI
VOL
PC
IIHE
IILE
EXTAL
IIHT
Input current
I/O leakage
current
IILT
TEX
IILR
RST∗1
IIL
PA to PD∗2,
PF to PI∗2
IIZ
IDDS2
Typ.
Unit
4.0
V
VDD = 4.5V, IOH = –1.2mA
3.5
V
VDD = 4.5V, IOL = 1.8mA
0.4
V
VDD = 4.5V, IOL = 3.6mA
0.6
V
VDD = 4.5V, IOL = 12.0mA
1.5
V
VDD = 5.5V, VIH = 5.5V
0.5
40
µA
VDD = 5.5V, VIL = 0.4V
–0.5
–40
µA
VDD = 5.5V, VIL = 5.5V
0.1
10
µA
–0.1
–10
µA
–1.5
–400
µA
–2.0
mA
VDD = 5.5V,
VIL = 0.4V
VDD = 4.5V, VIL = 4.0V
VDD = 5.5V, 20MHz crystal oscillation
(C1 = C2 = 15pF)
VDD = 3V, 32kHz crystal oscillation
(C1 = C2 = 47pF)
VDD
Max.
VDD = 4.5V, IOH = –0.5mA
High-speed mode operation
(1/2 frequency dividing clock)
IDD2
IDDS1
Min.
µA
–10
PE0 to PE3, VDD = 5.5V,
VI = 0, 5.5V
RST∗1
IDD1
Power supply
current∗3
Conditions
±10
µA
32
52
mA
38
100
µA
1.4
10
mA
9
30
µA
10
µA
20
pF
SLEEP mode
VDD = 5.5V, 20MHz crystal oscillation
(C1 = C2 = 15pF)
VDD = 3V, 32kHz crystal oscillation
(C1 = C2 = 47pF)
STOP mode
IDDS3
Input capacity
CIN
VDD = 5.5V, termination of 20MHz
and 32kHz crystal oscillation
PA,
PB0 to PB6,
PC, PD,
Clock 1MHz
PE0 to PE3,
0V for all pins excluding measured
PF to PI,
pins
EXTAL,
XTAL, TEX,
TX, RST
10
∗1) RST specifies the input current when pull-up resistance has been selected; leakage current when no
resistance has been selected.
∗2) PA to PD, and PF to PI pins specifie the input current when pull-up resistance has been selected; leakage
current when no resistance has been selected. (Excludes output PB7)
∗3) When all pins are open.
– 11 –
CXP84332M/84340M
AC Characteristics
(1) Clock timing
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Item
Symbol
System clock frequency
fC
System clock input pulse
width
Event count input clock
rise time, fall time
tXL,
tXH
tCR,
tCF
tEH,
tEL
tER,
tEF
System clock frequency
fC
Event count input clock
input pulse width
tTL,
tTH
tTR,
tTF
System clock input
rise time, fall time
Event count input clock
pulse width
Event count input clock
rise time, fall time
Pin
Conditions
Min.
XTAL
Fig. 1, Fig. 2
EXTAL
Typ.
1
EXTAL
Fig. 1, Fig. 2
External clock drive
EXTAL
Fig. 1, Fig. 2
External clock drive
EC0
EC1
Fig. 3
EC0
EC1
Fig. 3
TEX
TX
VDD = 2.7 to 5.5V
Fig. 2 (32kHz clock
applied condition)
TEX
Fig. 3
TEX
Fig. 3
Max.
Unit
20
MHz
ns
23.0
200
tsys + 50∗1
ns
ns
20
ms
kHz
32.768
µs
10
20
ms
∗1) tsys indicates the three values below according to the upper two bits (CPU clock selected) of the control
clock register (address: 00FEH).
tsys (ns) = 2000/fc (upper two bits = “00”), 4000/fc (upper two bits = “01”), 16000/fc (upper two bits = “11”)
1/fc
Fig. 1. Clock timing
VDD – 0.4V
EXTAL
0.4V
tXH
tCF
tXL
tCR
AAAAAAAAA AAAA
AAAAA
AAAA
AAAA
AAAAAAAAA AAAA
Fig. 2. Clock applied conditions
Crystal oscillation
Ceramic oscillation
EXTAL
XTAL
C1
External clock
EXTAL
TEX
XTAL
74HC04
C2
32kHz clock applied condition
Crystal oscillation
C1
TX
C2
Fig. 3. Event count clock timing
TEX
EC0
EC1
0.8VDD
0.2VDD
tEH
tTH
tEF
tTF
– 12 –
tEL
tTL
tER
tTR
CXP84332M/84340M
(2) Serial transfer (CH0)
Item
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss reference)
Symbol
Condition
Pin
Min.
Max.
Unit
CS0 ↓ → SCK0
delay time
tDCSK
SCK0
Chip select transfer mode
(SCK0 = output mode)
tsys + 200
ns
CS0 ↑ → SCK0
float delay time
tDCSKF SCK0
Chip select transfer mode
(SCK0 = output mode)
tsys + 200
ns
CS0 ↓ → SO0
delay time
tDCSO
SO0
Chip select transfer mode
tsys + 200
ns
CS0 ↑ → SO0
float delay time
tDCSOF SO0
Chip select transfer mode
tsys + 200
ns
CS0 High level width
tWHCS CS0
Chip select transfer mode
tsys + 200
ns
SCK0 cycle time
tKCY
Input mode
2tsys + 200
ns
16000/fc
ns
tsys + 100
ns
8000/fc – 50
ns
SCK0 input mode
100
ns
SCK0 output mode
200
ns
tsys + 200
ns
100
ns
SCK0
SCK0
High, Low level width
tKH
tKL
SCK0
SI0 input set-up time
(for SCK0 ↑)
tSIK
SI0
SI0 input hold time
(for SCK0 ↑)
tKSI
SCK0 ↓ → SO0
delay time
tKSO
SI0
SO0
Output mode
Input mode
Output mode
SCK0 input mode
SCK0 output mode
SCK0 input mode
SCK0 output mode
tsys+200
ns
100
ns
Note 1) tsys indicates the three values below according to the upper two bits (CPU clock selected) of the
control clock register (address: 00FEH).
tsys (ns) = 2000/fc (upper two bits = “00”), 4000/fc (upper two bits = “01”), 16000/fc (upper two bits = “11”)
Note 2) The load condition for the SCK0 output mode, SO0 output delay time is 50pF + 1TTL.
– 13 –
CXP84332M/84340M
Fig. 4. Serial transfer CH0 timing
tWHCS
CS0
0.8VDD
0.2VDD
tKCY
tDCSK
tKL
tDCSKF
tKH
0.8VDD
0.8VDD
SCK0
0.2VDD
tSIK
tKSI
0.8VDD
Input
data
SI0
0.2VDD
tDCSO
tKSO
tDCSOF
0.8VDD
SO0
Output data
0.2VDD
– 14 –
CXP84332M/84340M
Serial transfer (CH1)
Item
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Symbol
Pin
SCK1 cycle time
tKCY
SCK1
SCK1 High, Low level width
tKH
tKL
SCK1
SI1 input set-up time
(for SCK1 ↑)
tSIK
SI1
SI1 input hold time
(for SCK1 ↑)
tKSI
SI1
SCK1 ↓ → SO1 delay time
tKSO
SO1
Condition
Min.
Input mode
Max.
1000
ns
16000/fc
ns
400
ns
8000/fc – 50
ns
SCK1 input mode
100
ns
SCK1 output mode
200
ns
SCK1 input mode
200
ns
SCK1 output mode
100
ns
Output mode
Input mode
Output mode
SCK1 input mode
200
ns
SCK1 output mode
100
ns
Note) The load condition for the SCK1 output mode, SO1 output delay time is 50pF + 1TTL.
Fig. 5. Serial transfer CH1 timing
tKCY
tKL
tKH
SCK1
0.8VDD
0.2VDD
tSIK
tKSI
0.8VDD
Input data
SI1
Unit
0.2VDD
tKSO
0.8VDD
Output data
SO1
0.2VDD
– 15 –
CXP84332M/84340M
(3) A/D converter characteristics
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, AVREF = 4.0 to VDD, Vss = AVSS = 0V reference)
Item
Symbol
Max.
Unit
Resolution
8
Bits
Linearity error
±5
LSB
Zero transition voltage
VZT∗1
Full-scale transition
voltage
VFT∗2
Conversion time
tCONV
tSAMP
Sampling time
Pin
Condition
Ta = 25°C
VDD = AVREF = 5.0V
VSS = AVSS = 0V
AVREF
Analog input voltage
AN0 to AN7
–10
10
110
mV
4870
4970
5070
mV
AVREF
IREFS
µs
µs
VDD – 0.5
VDD
V
0
AVREF
V
1.0
mA
10
µA
0.6
Operation mode
IREF
AVREF current
Typ.
160/fADC∗3
12/fADC∗3
Reference input voltage VREF
VIAN
Min.
SLEEP mode
STOP mode
32kHz operation mode
Fig. 6. Definition of A/D converter terms
Digital conversion value
FFH
FEH
∗1) VZT : Value at which the digital transfer value changes
from 00H to 01H and vice versa.
∗2) VFT : Value at which the digital transfer value changes
from FEH to FFH and vice versa.
∗3) fADC indicates the values below due to the contents of
Linearity error
bit 6 (CKS) of the A/D control register (ADC: 00F9H)
and bits 7 (PCK1) and 6 (PCK0) of the clock control register
(CLC: 00FEH).
01H
00H
VFT
VZT
Analog input
CKS
PCK1, 0
0 (φ/2 selection)
1 (φ selection)
00 (φ = fEX/2)
fADC = fC/2
fADC = fC
01 (φ = fEX/4)
fADC = fC/4
fADC = fC/2
11 (φ = fEX/16)
fADC = fC/16
fADC = fC/8
– 16 –
CXP84332M/84340M
(4) Interruption, reset input
Item
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Symbol
Pin
External interruption
High, Low level width
tIH
tIL
INT0
INT1
INT2
INT3
NMI
Reset input Low level width
tRSL
RST
Condition
Min.
Max.
Unit
1
µs
32/fc
µs
Fig 7. Interruption input timing
tIH
tIL
0.8VDD
INT0
INT1
INT2
INT3
NMI
(NMI specifies only for
the falling edge.)
0.2VDD
tIL
tIH
Fig. 8. RST input timing
tRSL
RST
0.2VDD
– 17 –
CXP84332M/84340M
Appendix
Fig. 9. Recommended oscillation circuit
AAAA
AAAA
AAAA
(i) Main clock
EXTAL
XTAL
Rd
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
(ii) Main clock
EXTAL
(iii) Sub clock
EXTAL
TEX
XTAL
Rd
C1
XTAL
TX
Rd
C2
C2
C1
Products List
Manufacturer
MURATA MFG CO., LTD.
RIVER ELETEC CO., LTD.
KINSEKI LTD.
C1 (pF)
C2 (pF)
Rd (Ω)
Circuit
example
0
0
0
(i)
16.00
8
8
20.00
6
6
0
(ii)
32.768kHz
50
22
1M
(iii)
Model
fc (MHz)
CSA16.00MXZ072
16.00
CSA20.00MXZ046
20.00
HC-49/U03
P3
Mask option table
Item
Reset pin pull-up resistance
Content
Non-existent
Existent
– 18 –
CXP84332M/84340M
Example of Representative Characteristics
IDD vs. VDD
IDD vs. fc
(fc = 20MHz, Ta = 25°C, Typical)
(VDD = 5V, Ta = 25°C, Typical)
50
1/2 dividing mode
1/4 dividing mode
30
20
30
1/2 dividing mode
10
IDD – Supply curren [mA]
5
SLEEP mode
1
0.5
(500µA)
32kHz mode
(instruction)
0.1
(100µA)
IDD – Supply current [mA]
1/16 dividing mode
20
1/4 dividing mode
10
1.05
(50µA)
32kHz
SLEEP mode
1/16 dividing mode
SLEEP mode
0.01
(10µA)
0
1
2
3
4
5
6
7
0
VDD – Supply voltage [V]
5
10
Frequency [MHz]
– 19 –
15
20
CXP84332M/84340M
Package Outline
Unit: mm
80PIN QFP (PLASTIC)
23.9 ± 0.4
+ 0.1
0.15 – 0.05
+ 0.4
20.0 – 0.1
64
0.15
41
65
16.3
17.9 ± 0.4
+ 0.4
14.0 – 0.1
40
A
+ 0.2
0.1 – 0.05
25
1
24
0.8
0.2
M
+ 0.15
0.35 – 0.1
+ 0.35
2.75 – 0.15
0° to 10°
DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SOLDER PLATING
SONY CODE
QFP-80P-L01
LEAD TREATMENT
EIAJ CODE
QFP080-P-1420
LEAD MATERIAL
42/COPPER ALLOY
PACKAGE MASS
1.6g
JEDEC CODE
– 20 –
0.8 ± 0.2
80
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