Sony CXP87452 Cmos 8-bit single chip microcomputer Datasheet

CXP87452/87460
CMOS 8-bit Single Chip Microcomputer
Description
The CXP87452/87460 is a CMOS 8-bit microcomputer which consists of A/D converter, serial
interface (2ch independently), timer/counter, time
base timer, vector interruption, high precision timing
pattern generation circuit (PPG 2ch independently,
RTG 2ch independently), PWM generator, general
purpose prescaler, PWM for tuner, VCR vertical
sync separation circuit and the measuring circuit
which measure signals of capstan FG and drum
FG/PG and other servo systems, as well as basic
configurations like 8-bit CPU, ROM, RAM and I/O
port. They are integrated into a single chip.
Also CXP87452/87460 provides power on reset
function, sleep/stop function which enables to lower
power consumption .
100 pin QFP (PIastic)
100 pin LQFP (PIastic)
Structure
Silicon gate CMOS IC
Features
• A wide instruction set (213 instructions) which cover various types of data
— 16-bit arithmetic instruction/multiplication and division instructions/boolean bit operation instruction
• Minimum instruction cycle
During operation 333ns/12MHz (3.0 to 5.5V)
During operation 250ns/16MHz (4.5 to 5.5V)
• Incorporated ROM capacity
52K bytes (CXP87452)
60K bytes (CXP87460)
• Incorporated RAM capacity
1568 bytes
• Peripheral functions
— A/D converter
8-bit, 12-channel, successive approximation system
(Conversion time: 20µs/16MHz)
— Serial interface
Incorporated buffer RAM (1 to 32 bytes auto transfer) 1-channel
Incorporated 8-bit and 8-stage FIFO
(1 to 8 bytes auto transfer) 1-channel
— Timer
8-bit timer, 8-bit timer/counter, 19-bit time base timer
— High precision timing pattern generator PPG 19 pins 32-stage programmable
PPG 10 pins 21-stage programmable
RTG 5 pins 2-channel
— PWM/DA gate output
PWM 12-bit, 2-channel (Repetitive frequency 62.5kHz/16MHz)
DA gate pulse 12-bit, 4-channel
— Servo input control
Capstan FG, Drum FG/PG, CTL input
— VSYNC separator
— FRC capture unit
Incorporated 26-bit and 8-stage FIFO
— PWM output
14-bit, 1-channel
— General purpose prescaler
10-bit (System clock asynchronous)
— Pulse cycle measurement circuit
• Interruption
18 factors, 14 vectors, multi-interruption possible
• Standby mode
SLEEP/STOP
• Package
100-pin plastic QFP/LQFP
• Piggyback/evaluation chip
CXP87400 100-pin ceramic QFP/LQFP
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E95111-PS
PG4/PMI
PG7/PMSK
PE2/PWM0
PE4/DAA0
PE6/DAB0
PE3/PWM1
PE5/DAA1
PE7/DAB1
PI2/PWM
PI0/PCK/OSCI
PK0/OSCO
PI1/PO
PE0/XOUT
PG0/CFG
PG1/DFG
PG2/DPG
PG3/PBCTL
PG4/SYNC0
PG5/SYNC1
PG6/EXI0
PG7/EXI1
PE1/EC
PI3/TO
PI5/SCK1
PI7/SI1
PI6/SO1
AVDD
SERVO INPUT
CONTROL
PULSE MEASURE UNIT
12BIT PWM GENERATOR CH1
12BIT PWM GENERATOR CH0
14BIT PWM GENERATOR
PROGRAMMABLE PRESCALER
CTL
DRUM
CAPSTAN
V SYNC SEPARATOR
8BIT TIMER 1
8BIT TIMER/COUNTER 0
FIFO
SERIAL
INTERFACE UNIT
(CH1)
2
2
3
4
4
2
2
PE1/INT2
PI4/INT1
19
19
PROGRAMMABLE
PATTERN
GENERATOR (CH0)
FRC
CAPTURE
UNIT
INTERRUPT CONTROLLER
AVREF
BUFFER
RAM
AVss
SERIAL
INTERFACE UNIT
(CH0)
2
SPC700
CPU CORE
ROM
52K/60K BYTES
RAM
FIFO
PPO000 to PPO018
A/D CONVERTER
PPO100
to
CS0
SI0
SO0
SCK0
12
PPO107
AN0 to AN3
PF0/AN4
to
PF7/AN11
2
VDD
Vss
MP
RST
EXTAL
10
10
CH0
5
CH1
REALTIME
PULSE
GENERATOR
2
RAM
PRESCALER/
TIME BASE TIMER
RAM
1568 BYTES
CLOCK
GENERATOR/
SYSTEM CONTROL
XTAL
PROGRAMMABLE
PATTERN
GENERATOR (CH1)
PPO112
to
PPO113
PC0 to PC7
PD0 to PD7
PE0 to PE1
PE2 to PE7
8
8
2
6
PG0 to PG7
PH0 to PH7
PI0
PI1 to PI7
PJ0 to PJ7
8
8
1
7
8
1
PK0
PF4 to PF7
PF0 to PF3
PB0 to PB7
8
4
PA0 to PA7
8
4
PORT G
PORT H
PORT I
–2–
RTO3
to
RTO7
PORT A
PORT B
PORT C
PORT D
PORT E
PORT F
PORT J
PORT K
Block Diagram
CXP87452/87460
PE0/INT0
CXP87452/87460
PI4/INT1
PI5/SCK1
PI3/TO
PI1/PO
PI2/PWM
Mask
option
PI0/PCK/OSCI
VSS
PK0/OSCO
VDD
PA7/PPO007/PPO107
NC
PA6/PPO006/PPO106
PA4/PPO004/PPO104
PA5/PPO005/PPO105
PA2/PPO002/PPO102
PA3/PPO003/PPO103
PA0/PPO000/PPO100
PA1/PPO001/PPO101
PB7/PPO015
PB6/PPO014
Pin Configuration 1 (Top View) 100 pin QFP Package
AA
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
PB5/PPO013/PPO113
1
PB4/PPO012/PPO112
2
PB3/PPO011
3
PB2/PPO010
4
PB1/PPO009
5
PB0/PPO008
80
PI6/SO1
79
PI7/SI1
78
PE0/INT0/XOUT
77
PE1/EC/INT2
76
PE2/PWM0
6
75
PE3/PWM1
PC7/RTO7
7
74
PE4/DAA0
PC6/RTO6
8
73
PE5/DAA1
PC5/RTO5
9
72
PE6/DAB0
PC4/RTO4
10
71
PE7/DAB1
PC3/RTO3
11
70
PG0/CFG
PC2/PPO018
12
69
PG1/DFG
PC1/PPO017
13
68
PF2/DPG
PC0/PPO016
14
67
PG3/PBCTL
PJ7
15
66
PG4/SYNC0/PMI
PJ6
16
65
PG5/SYNC1
PJ5
17
64
PG6/EXI0
PJ4
18
63
PG7/EXI1/PMSK
PJ3
19
62
AN0
PJ2
20
61
AN1
PJ1
21
60
AN2
PJ0
22
59
AN3
PD7
23
58
PF0/AN4
PD6
24
57
PF1/AN5
PD5
25
56
PF2/AN6
PD4
26
55
PF3/AN7
PD3
27
54
AVDD
PD2
28
53
AVREF
PD1
29
52
AVSS
PD0
30
51
PF4/AN8
Note)
PF5/AN9
PF6/AN10
PF7/AN11
SO0
SCK0
SI0
CS0
XTAL
EXTAL
VSS
MP
RST
PH1
PH0
PH2
PH3
PH4
PH5
PH6
PH7
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
1. NC (Pin 90) is always connected to VDD.
2. Vss (Pins 41 and 88) are both connected to GND.
–3–
CXP87452/87460
PI7/SI1
PE0/INT0/XOUT
PI5/SCK1
PI6/SO1
PI4/INT1
PI3/TO
PI1/PO
PI2/PWM
Mask
option
PI0/PCL/OSCI
VSS
PK0/OSCO
VDD
NC
PA6/PPO006/PPO106
PA7/PPO007/PPO107
PA5/PPO005/PPO005
PA3/PPO003/PPO103
PA4/PPO004/PPO104
PA1/PPO001/PPO101
PA2/PPO002/PPO102
PB7/PPO015
PA0/PPO000/PPO100
PB6/PPO014
PB5/PPO013/PPO113
PB4/PPO012/PPO112
Pin Configuration 2 (Top View) 100 pin LQFP Package
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
PB3/PPO011
1
PB2/PPO010
2
PB1/PPO009
3
PB0/PPO008
4
PC7/RTO7
5
PC6/RTO6
6
PC5/RTO5
AA
AA
75
PE1/EC/INT2
74
PE2/PWM0
73
PE3/PWM1
72
PE4/DAA0
71
PE5/DAA1
70
PE6/DAB0
7
69
PE7/DAB1
PC4/RTO4
8
68
PG0/CFG
PC3/RTO3
9
67
PG1/DFG
PC2/PPO018
10
66
PF2/DPG
PC1/PPO017
11
65
PG3/PBCTL
PC0/PPO016
12
64
PG4/SYNC0/PMI
PJ7
13
63
PG5/SYNC1
PJ6
14
62
PG6/EXI0
PJ5
15
61
PG7/EXI1/PMSK
PJ4
16
60
AN0
PJ3
17
59
AN1
PJ2
18
58
AN2
PJ1
19
57
AN3
PJ0
20
56
PF0/AN4
PD7
21
55
PF1/AN5
PD6
22
54
PF2/AN6
PD5
23
53
PF3/AN7
PD4
24
52
AVDD
PD3
25
51
AVREF
Note)
1. NC (Pin 88) is always connected to VDD.
2. Vss (Pins 39 and 86) are both connected to GND.
–4–
AVSS
PF4/AN8
PF5/AN9
PF6/AN10
SCK0
PF7/AN11
SI0
SO0
CS0
EXTAL
XTAL
VSS
RST
MP
PH1
PH0
PH3
PH2
PH4
PH5
PH6
PH7
PD0
PD1
PD2
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
CXP87452/87460
Pin Description
Symbol
I/O
PA0/PPO000
/PPO100
to
PA7/PPO007
/PPO107
Output/
Real time
output
PB0/PPO008
to
PB7/PPO015
Output/
Real time
output
PC0/PPO016
to
PC2/PPO018
I/O/
Real time
output
PC3/RTO3
to
PC7/RTO7
I/O/
Real time
output
Description
(Port A)
8-bit output port. Data is gated
with PPO0 and PPO1 contents
by OR-gate and they are output.
(8 pins)
Programmable pattern generator
(PPG0, PPG1) output.
(Port B)
8-bit output port. Data is gated Functions as high precision real time
with PPO0 and PPO1 contents pulse output port.
PPG0 19 pins
by OR-gate and they are output.
PPG1 10 pins
(8 pins)
(
(Port C)
8-bit I/O port. Enables to
specify I/O by bit unit.
Data is gated with PPO or
RTO contents by OR-gate
and they are output.
(8 pins)
)
Real time pulse generator (RTG) output.
Functions as high precision real time
pulse output port. (5 pins)
(Port D)
8-bit I/O port. Enable to specify I/O by 4-bit unit.
Enables to drive 12mA sinc current. (During 5V ± 0.5V operation)
(8 pins)
PD0 to PD7
I/O
PE0/INT0
/XOUT
Input/input/output
Input pin to request
1/2 dividing clock
external interruption.
output of XTAL
Active when falling edge. or OSCO.
PE1/EC/INT2
Input/input/input
External event
input pin for
timer/counter.
PE2/PWM0
Output/output
PE3/PWM1
Output/output
PE4/DAA0
Output/output
PE5/DAA1
Output/output
PE6/DAB0
Output/output
PE7/DAB1
Output/output
AN0 to AN3
Input
Analog input pins to A/D converter. (12 pins)
PF0/AN4
to
PF3/AN7
Input/input
PF4/AN8
to
PF7/AN11
Output/input
(Port F)
Lower 4 bits are input port and upper 4 bits are output port.
Lower 4 bits also serve as standby release input pin.
(8 pins)
SCK0
I/O
Serial clock (CH0) I/O pin.
SO0
Ouput
Serial data (CH0) output pin.
SI0
Input
Serial data (CH0) input pin.
CS0
Input
Serial chip select (CH0) input pin.
(Port E)
8-bit port. Lower 2 bits are
input port and upper 6 bits
are output port.
(8 pins)
Input pin to request
external interruption.
Active when falling edge.
PWM output pins.
(2 pins)
DA gate pulse output pins.
(4 pins)
–5–
CXP87452/87460
Symbol
I/O
PG0/CFG
Input/input
Capstan FG input pin.
PG1/DFG
Input/input
Drum FG input pin.
PG2/DPG
Input/input
Drum PG input pin.
PG3/PBCTL
Input/input
PG4/SYNC0
/PMI
Input/input/input
PG5/SYNC1
Input/input
PG6/EXI0
Input/input
PG7/EXI1/
PMSK
Input/input/input
PH0 to PH7
Output
Description
(Port G)
8-bit input port.
(8 pins)
Playback CTL pulse input pin.
Composite sync
signal input pin.
External input pin to
FRC capture unit.
Measuring pulse signal input pin
of pulse cycle measuring unit.
Measuring enable signal input pin
of pulse cycle measuring unit.
(Port H)
8-bit output port; large current, N-ch open drain output.
(8 pins)
External clock input
pin of general
purpose prescaler.
Connecting pin of crystal
oscillation circuit for general
purpose prescaler. (Mask option)
PI0/PCK
/OSCI
Input/input/input
PI1/PO
I/O/output
PI2/PWM
I/O/output
PI3/TO
I/O/output
PI4/INT1
I/O/input
PI5/SCK1
I/O/I/O
PI6/SO1
I/O/output
Serial data (CH1) output pin.
PI7/SI1
I/O/input
Serial data (CH1) input pin.
PJ0 to PJ7
I/O
(Port I)
Lower 1 bit is
input port
(mask option)
and upper 7 bits
are I/O port.
I/O port can be
specified by bit
unit.
(8 pins)
General purpose prescaler output pin.
14-bit PWM output pin.
Timer/counter, output pin. (duty = 50%)
Input pin to request external interruption.
Active when falling edge.
Serial clock (CH1) I/O pin.
(Port J)
8-bit I/O port. Function as standby release input can be specified by bit
unit. I/O can be specified by bit unit.
–6–
CXP87452/87460
Symbol
I/O
Description
Connecting pin of crystal
oscillation circuit for general
purpose prescaler. (Mask opiton)
PK0/OSCO
Input/output
Input port. (Mask option)
EXTAL
Input
XTAL
Output
Connecting pin of crystal oscillator for system clock. When supplying
the external clock, input the external clock to EXTAL pin and input
opposite phase clock to XTAL pin.
RST
I/O
System reset pin of active "L" level. RST pin is I/O pin, which output
"L" level by incorporated power on reset function when power on.
(Mask option)
MP
Input
Microprocessor mode input pin. Always connect to GND.
Positive power supply pin of A/D converter.
AVDD
AVREF
Input
Reference voltage input pin of A/D converter.
AVSS
GND pin of A/D converter.
VDD
Positive power supply pin.
VSS
GND pin. Connect both Vss pins to GND.
–7–
CXP87452/87460
Input/Output Circuit Format for Pins
Pin
PA0/PPO000
/PPO100
to
PA7/PPO007
/PPO107
PB4/PPO012
/PPO112
to
PB5/PPO013
/PPO113
10 pins
Circuit format
When reset
AA
AA
Port A
Port B
AAAA
AAAA
PPO0 data
PPO1 data
Port A or Port B
Data bus
Hi-Z
Output becomes active from high
impedance by data writing to port register.
RD
Port B
PB0/PPO008
to
PB3/PPO011
PB6/PPO014
to
PB7/PPO015
AAAA
AAAA
AA
AA
PPO0 data
Port A or Port B
Data bus
6 pins
Output becomes active from high
impedance by data writing to port register.
RD
Port C
PC0/PPO016
to
PC2/PPO018
PC3/RTO3
to
PC7/RTO7
AAAA
AAAA
AAAA
PPO, RTO data
(Every bit)
RD (Port C)
Port D
AAAA
AAAA
AAAA
AA
AA
AA
AA
Large
current
12mA
Port D data
IP
Port D direction
(Every 4 bits)
PD0 to 3
PD4 to 7
Data bus
8 pins
Hi-Z
IP
Port C direction
Data bus
PD0
to
PD7
AA
AA
AA
Input
protection
circuit
Port C data
8 pins
Hi-Z
RD (Port D)
–8–
Hi-Z
CXP87452/87460
Pin
Circuit format
AA
AA
AAAA
AA
AA
AA
AA
AAA
AA
AAA
Port E
When reset
Schmitt input
IP
PE1/EC/INT2
1 pin
Port E
RD (Port E)
PS1
MPX
1/2
OSCO
PE0/INT0
/XOUT
Port E function
select register
Data bus
1 pin
AAA
AAA
AAAA
AAA
AAAA
AAA
AAAA
RD (Port E)
Port E
DA gate output or
PWM output
MPX
Hi-Z control
PE2/PWM0
PE3/PWM1
PE4/DAA0
PE5/DAA1
Port E data
Hi-Z
Data bus
AA
AA
AA
AA
IP
Hi-Z
To interruption
circuit
AA
AA
Hi-Z
Port E function
select register
Data bus
4 pins
RD (Port E)
Port E
AA
AA
AAA
AA
AAA
AA
AAA
AAA
DA gate output
MPX
Hi-Z control
PE6/DAB0
PE7/DAB1
Port E data
Port E function
select register
Data bus
2 pins
RD (Port E)
–9–
AA
AA
H level
CXP87452/87460
AA
AA
AAAA
AA
AA
AAAA
Pin
Circuit format
AN0
to
AN3
When reset
Input multiplexer
IP
4 pins
Port F
Hi-Z
A/D converter
Input multiplexer
IP
PF0/AN4
to
PF3/AN7
A/D converter
Hi-Z
Data bus
RD (Port F)
4 pins
AAAA
AA
AAAAAAAA AAAA
AAAA
Port F
PF4/AN8
to
PF7/AN11
Port F data
Data bus
IP
RD
(Port F)
4 pins
Hi-Z
Port/AD select
Input multiplexer
A/D converter
Port G
PG0/CFG
PG1/DFG
PG2/DPG
PG3/PBCTL
PG4/SYNC0/PMI
PG5/SYNC1
PG6/EXI0
PG7/EXI1/PMSK
AAAA
AA
Schmitt input
Pulse cycle measurement unit input
Servo input
IP
Data bus
Hi-Z
RD (Port G)
Note) For PG4/SYNC0, PG5/SYNC1, CMOS schmitt input and TTL schmitt input
can be selected with the mask option.
8 pins
Port H
PH0
to
PH7
AAA
AAA
AA
AA
Port H data
Large current
12mA
Data bus
RD (Port H)
8 pins
– 10 –
Hi-Z
CXP87452/87460
Pin
Circuit format
Port I
When reset
AAAA
AAAA
AA
AAA
AA
AAA
AA
AAA
AA
AA
AA
Port I
function select
PI1/PO
PI2/PWM
PI3/TO
PI1: From general purpose prescaler
PI2: From 14-bit PWM
PI3: From timer/counter
MPX
Port I data
Port I direction
Data bus
IP
AAAA
AAAA
AAAA
AAAA
RD (Port I)
3 pins
Port I
AA
AA
AA
Port I data
PI4/INT1
PI7/SI1
Port I direction
Hi-Z
IP
Data bus
RD (Port I)
2 pins
Hi-Z
Schmitt input
PI4: To interruption circuit
PI7: To serial CH1
AAAA
AAAA
AAA
AAAA
AAA
AA
AAAA
AAA
AA
AAAA AA
AA
AAA
AAA
AAA
AAA
AA
Port I
Port I
function select
From serial CH1
MPX
PI5/SCK1
PI6/SO1
Port I data
MPX
Port I direction
Data bus
RD (Port I)
2 pins
Port J data
Port J direction
Data bus
RD
(Port J)
8 pins
Hi-Z
IP
Note)
PI5 is schmitt input
PI6 is inverter input
To serial CH1
Port J
PJ0
to
PJ7
AA
AA
AA
AA
Edge detection
Standby release
– 11 –
AA
AA
AA
AA
IP
Hi-Z
CXP87452/87460
AA
AA
AAAA
Pin
Circuit format
When reset
Schmitt input
CS0
SI0
SO0
SO0 from SIO
1 pin
SO0 output enable
Internal serial clock
from SIO
SCK0
External serial clock to SIO
1 pin
Schmitt input
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
A
AAA
AA
A
AA
A
AA
AA
AAAA
AA
EXTAL
XTAL
2 pins
XTAL
AA
AA
AA
AA
AA
AA
Hi-Z
Hi-Z
IP
SCK0 output enable
EXTAL
Hi-Z
To SIO
IP
2 pins
IP
• Shows the circuit
composition during
oscillation.
• Feedback resistor is
removed during stop.
Oscillation
Pull-up resistor
Mask option
Schmitt input
OP
RST
L level
IP
From power on reset circuit
(mask option)
1 pin
MP
IP
1 pin
Port I
Hi-Z
CPU mode
Port K
OSCI
PI0/PCK/OSCI
PK0/OSCO
IP
Oscillation
OSCO
Fig. 1
PI0/PCK
or PK0
2 pins
IP
Note) Circuit format of Fig. 1 or Fig. 2 can be
selected with mask option.
– 12 –
Fig. 2
Data bus
RD
Port I
Port K
Hi-Z
CXP87452/87460
Absolute Maximum Ratings
Item
(Vss = 0V)
Symbol
VDD
Power supply voltage
AVDD
AVSS
Rating
Unit
–0.3 to +7.0
AVss to +7.0∗1
V
V
Remarks
V
Input voltage
VIN
–0.3 to +0.3
–0.3 to +7.0∗2
Output voltage
VOUT
–0.3 to +7.0∗2
V
High level output current
IOH
–5
mA
High level total output current
∑IOH
–50
mA
IOL
15
mA
IOLC
20
mA
Other than large current output
pins: per pin
Large current output pin∗3: per pin
Low level total output current
∑IOL
130
mA
Total of output pins
Operating temperature
Topr
–20 to +75
°C
Storage temperature
Tstg
–55 to +150
°C
Allowable power dissipation
PD
Low level output current
V
600
380
Total of output pins
QFP
mW
LQFP
∗1 AVDD and VDD should be set to a same voltage.
∗2 VIN and VOUT should not exceed VDD + 0.3V. (CS0, SI0, PG and PH excluded.)
∗3 The large current operation transistors are the N-CH transistors of the PD and PH ports.
Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should
better take place under the recommended operating conditions. Exceeding those conditions may
adversely affect the reliability of the LSI.
– 13 –
CXP87452/87460
Recommended Operating Conditions
Item
Power supply voltage
Analog power supply
High level
input voltage
Symbol
Min.
Max.
Unit
3.0
5.5
V
Guaranteed range during high speed mode
(1/2 dividing clock) operation
2.7
5.5
V
Guaranteed range during low speed mode
(1/16 dividing clock) operation
2.5
5.5
V
3.0
5.5
V
Guaranteed data hold operation range
during STOP
∗1
VIH
0.7VDD
VDD
V
∗2
VIHS
0.8VDD
VDD
V
5.5
V
VIHTS
2.2
5.5
V
VDD
AVDD
VIHEX
Low level
input voltage
VDD – 0.4 VDD + 0.3
V
VDD – 0.2 VDD + 0.2
V
CMOS schmitt input∗3 and PE0/INT0 pins
CMOS schmitt input∗4
TTL schmitt input∗5, ∗8
EXTAL pin∗6, ∗8
0.3VDD
V
0.2VDD
V
∗2, ∗7
0
0.2VDD
V
0
0.8
V
–0.3
0.4
V
–0.3
0.2
V
–20
+75
°C
0
VILS
VILTS
Operating temperature Topr
Remarks
EXTAL pin∗6, ∗7
∗2, ∗8
VIL
VILEX
∗1
∗2
∗3
∗4
∗5
∗6
∗7
∗8
(Vss = 0V)
CMOS schmitt input∗3, ∗4 and PE0/INT0 pins
TTL schmitt input∗5, ∗8
EXTAL pin∗6, ∗8
EXTAL pin∗6, ∗7
AVDD and VDD should be set to a same voltage.
Normal input port (each pin of PC, PD, PF0 to PF3, PI PJ, and PK), MP pin.
Each pin of SCK0, RST, PE1/EC/INT2, PI1/PO, PI4/INT1, PI5/SCK1 and PI7/SI1.
Each pin of CS0, SI0, and PG (for PG and PG5, when CMOS schmitt input is selected.)
Each pin of PG4 and PG5 (When TTL schmitt input is selected with mask option)
It specifies only when the external clock is input.
In case of 3.0 to 3.6V supply voltage (VDD).
In case of 4.5 to 5.5V supply voltage (VDD).
– 14 –
CXP87452/87460
Electrical Characteristics
DC Characteristics
Supply voltage (VDD) 4.5 to 5.5V
Item
High level
output voltage
Symbol
VOH
Low level
output voltage VOL
(Ta = –20 to +75°C, Vss = 0V)
Pin
PA to PE,
PF4 to PF7,
PH (VOL only)
PI1 to PI7, PJ,
SO, SCK, RST∗1
(VOL only)
PD, PH
IIHE
Input current
I/O leakage
current
IILE
EXTAL
Unit
VDD = 4.5V, IOH = –1.2mA
3.5
V
VDD = 4.5V, IOL = 1.8mA
0.4
V
VDD = 4.5V, IOL = 3.6mA
0.6
V
VDD = 4.5V, IOL = 12.0mA
1.5
V
VDD = 5.5V, VIH = 5.5V
0.5
40
µA
VDD = 5.5V, VIL = 0.4V
–0.5
–40
µA
–1.5
–400
µA
±10
µA
31
50
mA
2.0
8.0
mA
10
µA
20
pF
IIZ
PA to PK,
MP,
AN0 to AN3,
CS, SI, SO,
SCK, RST∗2
VDD=5.5V,
VI = 0, 5.5V
Crystal oscillation
(C1 = C2 = 15pF) of 16MHz
VDD = 5V ± 0.5V∗4
SLEEP mode
VDD = 5V ± 0.5V
IDDS3
Max.
V
VDD = 5.5V, VIL = 0.4V
VDD
Typ.
4.0
RST∗2
IDDS1
Min.
VDD = 4.5V, IOH = –0.5mA
IILR
IDD1
Supply
current∗3
Condition
STOP mode
VDD = 5.5V
Input capacity
CIN
Other than VDD,
Clock 1MHz
Vss, AVDD, and
0V other than the measured pins
AVss pins
10
∗1 RST pin specifies only when the power on reset circuit has been selected with mask option.
∗2 RST pin specifies the input current when the pull-up resistor is selected, and specifies leakage current
when non-resistance is selected.
∗3 When entire output pins are open.
∗4 When setting upper 2 bits (CPU clock selection) of clock control register CLC (address: 00FEH) to "00" and
operating in high speed mode (1/2 dividing clock).
– 15 –
CXP87452/87460
Supply voltage (VDD) 3.0 to 3.6V
Item
High level
output voltage
Symbol
VOH
Low level
output voltage VOL
(Ta = –20 to +75°C, Vss = 0V)
Pin
I/O leakage
current
IILE
Typ.
Max.
Unit
VDD = 3.0V, IOH = –0.15mA
2.7
V
VDD = 3.0V, IOH = –0.5mA
2.3
V
PD, PH
EXTAL
VDD = 3.0V, IOL = 1.2mA
0.3
V
VDD = 3.0V, IOL = 1.6mA
0.5
V
VDD = 3.0V, IOL = 5.0mA
1.0
V
VDD = 3.6V, VIH = 3.6V
0.3
20
µA
VDD = 3.6V, VIL = 0.3V
–0.3
–20
µA
IILR
RST∗2
VDD = 3.6V, VIL =0.3V
–0.9
–200
µA
IIZ
PA to PK,
MP,
AN0 to AN3,
CS, SI, SO,
SCK, RST∗2
VDD = 5.5V,
VI = 0, 5.5V
±10
µA
15
30
mA
0.8
2.5
mA
10
µA
20
pF
Crystal oscillation
(C1 = C2 = 15pF) of 12MHz
IDD2
Supply
current∗3
Min.
PA to PE,
PF4 to PF7,
PH (VOL only)
PI1 to PI7, PJ,
SO, SCK, RST∗1
(VOL only)
IIHE
Input current
Condition
IDDS2
VDD = 3.3V ± 0.3V∗4
VDD
SLEEP mode
VDD = 3.3V ± 0.3V
IDDS3
STOP mode
VDD = 5.5V
Input capacity
CIN
Other than VDD,
Clock 1MHz
Vss, AVDD, and
0V other than the measured pins
AVss pins
10
∗1 RST pin specifies only where the power on reset circuit has been selected with mask option.
∗2 RST pin specifies the input current when the pull-up resistor is selected, and specifies leakage current
when non-resistance is selected.
∗3 When entire output pins are open.
∗4 When setting upper 2 bits (CPU clock selection) of clock control register CLC (address: 00FEH) to "00" and
operating in high speed mode (1/2 dividing clock).
– 16 –
CXP87452/87460
AC Characteristics
(1) Clock timing
Item
(Ta = –20 to +75°C, VDD = 3.0 to 5.5V, Vss = 0V)
Symbol
Pin
Condition
VDD = 4.5 to 5.5V
System clock frequency
fC
XTAL
EXTAL
Fig. 1,
Fig. 2
System clock input pulse
width
tXL,
tXH
XTAL
EXTAL
VDD = 4.5 to 5.5V
Fig. 1,
Fig. 2 (External clock drive)
System clock input
rising and falling times
tCR,
tCF
tEL,
tEH
tER,
tEF
XTAL
EXTAL
Fig. 1, Fig. 2
(External clock drive)
PE1/EC
Fig. 3
PE1/EC
Fig. 3
Event count clock input
pulse width
Event count clock input
rising and falling times
Min.
Max.
1
16
1
12
28
Unit
MHz
ns
37.5
200
tsys × 4∗
ns
ns
20
ms
∗ tsys indicates three values according to the contents of the clock control register (address; 00FEH) upper 2
bits (CPU clock selection).
tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11")
Fig. 1. Clock timing
1/fc
VDD – 0.4V
XTAL
EXTAL
0.4V
tCF
tXH
Fig. 2. Clock applied condition
AAAA
AAAA
AAAA
External clock
EXTAL
XTAL
C1
tCR
AAAA
AAAA
AAAA
Crystal oscillation
Ceramic oscillation
EXTAL
tXL
C2
XTAL
74HC04
Fig. 3. Event count clock timing
0.8VDD
EC
0.2VDD
tEH
tEF
– 17 –
tEL
tER
CXP87452/87460
(2) Serial transfer (CH0)
Item
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V)
Symbol
Pin
Condition
Min.
Max.
Unit
CS ↓ → SCK
delay time
tDCSK
SCK0
Chip select transfer mode
(SCK = output mode)
tsys + 200
ns
CS ↑ → SCK
floating delay time
tDCSKF SCK0
Chip select transfer mode
(SCK = output mode)
tsys + 200
ns
CS ↓ → SO
delay time
tDCSO
SO0
Chip select transfer mode
tsys + 200
ns
CS ↓ → SO
floating delay time
tDCSOF SO0
Chip select transfer mode
tsys + 200
ns
CS
high level width
tWHCS CS0
Chip select transfer mode
tsys + 200
ns
SCK
cycle time
Input mode
SCK0
2tsys + 200
ns
tKCY
8000/fc
ns
SCK
high and low level widths
tKH
tKL
tsys + 100
ns
SCK0
Output mode
8000/fc – 100
ns
SI input setup time
(against SCK ↑)
SCK input mode
SI0
–tsys + 100
ns
tSIK
200
ns
SI input hold time
0
(against SCK ↑)
SI0
2tsys + 100
ns
tKSI
100
ns
SCK ↓ → SO delay time
tKSO
SO0
Output mode
Input mode
SCK output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode
2tsys + 200
ns
100
ns
Note 1) tsys indicates three values according to the contents of the clock control register (address; 00FEH)
upper 2 bits (CPU clock selection).
tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11")
Note 2) CS, SCK, SI and SO means each pin of CS → CS0, SCK → SCK0, SI → SI0, and SO → SO0 respectively.
Note 3) The load of SCK output mode and SO output delay time is 50pF + 1TTL.
– 18 –
CXP87452/87460
Serial transfer (CH0)
Item
(Ta = –20 to +75°C, VDD = 3.0 to 3.6V, Vss = 0V)
Symbol
Pin
Condition
Min.
Max.
Unit
CS ↓ → SCK
delay time
tDCSK
SCK0
Chip select transfer mode
(SCK = output mode)
tsys + 250
ns
CS ↑ → SCK
floating delay time
tDCSKF SCK0
Chip select transfer mode
(SCK = output mode)
tsys + 200
ns
CS ↓ → SO
delay time
tDCSO
SO0
Chip select transfer mode
tsys + 250
ns
CS ↓ → SO
floating delay time
tDCSOF SO0
Chip select transfer mode
tsys + 200
ns
CS
high level width
tWHCS CS0
Chip select transfer mode
tsys + 200
ns
SCK
cycle time
Input mode
SCK0
2tsys + 200
ns
tKCY
16000/fc
ns
SCK
high and low level widths
tKH
tKL
tsys + 100
ns
SCK0
Output mode
8000/fc – 150
ns
SI input setup time
(against SCK ↑)
SCK input mode
SI0
–tsys + 100
ns
tSIK
200
ns
SI input hold time
(against SCK ↑)
SI0
2tsys + 100
ns
tKSI
100
ns
SCK ↓ → SO delay time
tKSO
SO0
Output mode
Input mode
SCK output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode
2tsys + 250
ns
125
ns
Note 1) tsys indicates three values according to the contents of the clock control register (address; 00FEH)
upper 2 bits (CPU clock selection).
tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11")
Note 2) CS, SCK, SI and SO means each pin of CS → CS0, SCK → SCK0, SI → SI0, and SO → SO0 respectively.
Note 3) The load of SCK output mode and SO output delay time is 50pF.
– 19 –
CXP87452/87460
Fig. 4. Serial transfer timing (CH0)
tWHCS
CS0
0.8VDD
0.2VDD
tKCY
tDCSK
tKL
tDCSKF
tKH
0.8VDD
0.8VDD
SCK0
0.2VDD
tKSI
tSIK
0.8VDD
Input
data
SI0
0.2VDD
tDCSO
tKSO
tDCSOF
0.8VDD
SO0
Output
data
0.2VDD
– 20 –
CXP87452/87460
Serial transfer (CH1) (SIO mode)
Item
Symbol
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V)
Pin
Condition
tKCY
SCK1
SCK1 high and low
level widths
tKH
tKL
SCK1
SI1 input setup time
(against SCK1 ↑)
tSIK
SI1
SI1 input hold time
(against SCK1 ↑)
tKSI
SI1
SCK1 ↓ → SO1 delay time
tKSO
SO1
Max.
Unit
2tsys + 200
ns
16000/fc
ns
tsys + 100
ns
8000/fc – 100
ns
SCK1 input mode
100
ns
SCK1 output mode
200
ns
tsys + 200
ns
100
ns
Input mode
SCK1 cycle time
Min.
Output mode
Input mode
Output mode
SCK1 input mode
SCK1 output mode
SCK1 input mode
SCK1 output mode
tsys + 200
ns
100
ns
Note 1) tsys indicates three values according to the contents of the clock control register (address; 00FEH)
upper 2 bits (CPU clock selection).
tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11")
Note 2) The load of SCK1 output mode and SO1 output delay time is 50pF + 1TTL.
Serial transfer (CH1) (SIO mode)
Item
Symbol
(Ta = –20 to +75°C, VDD = 3.0 to 3.6V, Vss = 0V)
Pin
SCK1 cycle time
tKCY
SCK1
SCK1 high and low
level widths
tKH
tKL
SCK1
SI1 input setup time
(against SCK1 ↑)
tSIK
SI1
SI1 input hold time
(against SCK1 ↑)
tKSI
SI1
SCK1 ↓ → SO1 delay time
tKSO
SO1
Condition
Min.
Max.
Unit
2tsys + 200
ns
16000/fc
ns
tsys + 100
ns
8000/fc – 150
ns
SCK1 input mode
100
ns
SCK1 output mode
200
ns
tsys + 200
ns
100
ns
Input mode
Output mode
Input mode
Output mode
SCK1 input mode
SCK1 output mode
SCK1 input mode
SCK1 output mode
tsys + 250
ns
125
ns
Note 1) tsys indicates three values according to the contents of the clock control register (address; 00FEH)
upper 2 bits (CPU clock selection).
tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11")
Note 2) The load of SCK1 output mode and SO1 output delay time is 50pF.
– 21 –
CXP87452/87460
Fig. 5. Serial transfer CH1 timing (SIO mode)
tKCY
tKL
tKH
SCK1
0.8VDD
0.2VDD
tSIK
tKSI
0.8VDD
SI1
Input data
0.2VDD
tKSO
0.8VDD
SO1
Output data
0.2VDD
– 22 –
CXP87452/87460
Serial transfer (CH1) (Special mode)
Item
Symbol
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V)
Pin
Condition
Min.
Typ.
Max.
Unit
SO1 cycle time
tLCY
SO1
SI1
SI1 data setup time
tLSU
tLHD
SI1
2
µs
SI1
2
µs
SI1 data hold time
104
Note 1)
µs
Note 1) tLCY specifies only serial mode register (CH1) (SIOM1: Address 01FAH) lower 2 bits (SO1 clock
selection) has been set at 104µs.
Note 2) The load of SO1 pin is 50pF + 1TTL.
Serial transfer (CH1) (Special mode)
Item
Symbol
(Ta = –20 to +75°C, VDD = 3.0 to 3.6V, Vss = 0V)
Pin
Condition
Min.
Typ.
Max.
Unit
SO1 cycle time
tLCY
SO1
SI1
SI1 data setup time
tLSU
tLHD
SI1
2
µs
SI1
2
µs
SI1 data hold time
104
Note 1)
µs
Note 1) tLCY specifies only serial mode register (CH1) (SIOM1: Address 01FAH) lower 2 bits (SO1 clock
selection) has been set at 104µs.
Note 2) The load of SO1 pin is 50pF.
Fig. 6. Serial transfer CH1 timing (Special mode)
tLCY
tLCY
SO1
Start bit
0.5VDD
Output data bit
tLCY/2
tLSU
tLHD
Input
data bit
SI1
– 23 –
0.8VDD
0.2VDD
CXP87452/87460
(3) A/D converter characteristics (Ta = –20 to +75°C, VDD = AVDD = 4.5 to 5.5V, AVREF = 4.0 to AVDD, Vss = AVSS = 0V)
Item
Symbol
Pin
Condition
Min.
Typ.
Max.
Unit
8
Bits
±1
LSB
±2
LSB
Resolution
Only for A/D converter
operation
Ta = 25°C
VDD = AVDD = AVREF = 5.0V
VSS = AVSS = 0V
Linearity error
Absolute error
Conversion time
Sampling time
tCONV
tSAMP
Reference input voltage VREF
Analog input voltage
AVREF current
VIAN
AVREF
µs
12/fADC
µs
VDD = AVDD = 4.5 to 5.5V AVDD – 0.5
AN0 to AN11
IREF
A/D converter characteristics
Item
AVREF
160/fADC
0
Operating mode
AVREF = 4.0 to 5.5V
0.6
AVDD
V
AVREF
V
1.0
mA
10
µA
SLEEP mode
STOP mode
(Ta = –20 to +75°C, VDD = AVDD = 3.0 to 3.6V, AVREF = 2.7 to AVDD, Vss = AVSS = 0V)
Symbol
Pin
Condition
Min.
Typ.
Max.
Unit
8
Bits
±1
LSB
±2
LSB
Resolution
Only for A/D converter
operation
Ta = 25°C
VDD = AVDD = AVREF = 3.3V
VSS = AVSS = 0V
Linearity error
Absolute error
Conversion time
Sampling time
tCONV
tSAMP
Reference input voltage VREF
Analog input voltage
AVREF current
VIAN
IREF
AVREF
µs
12/fADC
µs
VDD = AVDD = 3.0 to 3.6V AVDD – 0.3
AN0 to AN11
AVREF
160/fADC
0
Operating mode
AVREF = 2.7 to 3.6V
0.4
AVDD
V
AVREF
V
0.7
mA
10
µA
SLEEP mode
STOP mode
Fig. 7. Definitions of A/D converter terms
Digital conversion value
FFH
FEH
∗ The value of fADC is as follows by selecting ADC
operation clock (MSC: Address 01FFH bit 0).
When PS2 is selected, fADC = fc/2
Linearity error
When PS1 is selected, fADC = fc
01H
00H
VFT
VZT
Analog input
– 24 –
CXP87452/87460
(4) Interruption, reset input
(Ta = –20 to +75°C, VDD = 3.0 to 5.5V, Vss = 0V)
Item
Symbol
Pin
Condition
External interruption
high and low level widths
tIH
tIL
INT0
INT1
INT2
PJ0 to PJ7
Reset input low level width
tRSL
RST
Min.
Max.
Unit
1
µs
32/fc
µs
Fig. 8. Interruption input timing
tIH
INT0
INT1
INT2
PJ0 to PJ7
(During standby release input)
(Falling edge)
tIL
0.8VDD
0.2VDD
Fig. 9. Reset input timing
tRSL
RST
0.2VDD
(5) Power on reset
Power on reset∗
(Ta = –20 to +75°C, VDD = 3.0 to 5.5V, Vss = 0V)
Item
Symbol Pin
tR
tOFF
Power supply rising edge
Power supply cut-off time
VDD
Condition
Power on reset
Repetitive power on reset
Min.
Max.
Unit
0.05
30
ms
1
ms
∗ Specifies only when power on reset function is selected.
Fig. 10. Power on reset
3.0V
VDD
0.2V
0.2V
tR
tOFF
The power supply should rise smoothly.
– 25 –
CXP87452/87460
(6) General purpose prescaler
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V)
Item
Symbol
Pin
External clock input frequency
fPCK
PCK
External clock input pulse width
tWH, tWL
tR,
tF
tPLH
tPHL
tTLH
tTHL
PCK
External clock input
rising and falling times
Prescaler output delay time
(against PCK ↑)
Prescaler output
rising and falling times
Condition
Min.
Typ.
Max.
Unit
12
MHz
33
ns
PCK
200
ns
PO
External clock input
PCK tR = tF = 6ns
80
130
ns
60
100
ns
PO
External clock input
PCK tR = tF = 6ns
50
100
ns
20
40
ns
Note) The load of PO pin is 50pF.
General purpose prescaler
(Ta = –20 to +75°C, VDD = 3.0 to 3.6V, Vss = 0V)
Item
Symbol
Pin
External clock input frequency
fPCK
PCK
External clock input pulse width
tWH, tWL
tR,
tF
tPLH
tPHL
tTLH
tTHL
PCK
External clock input
rising and falling times
Prescaler output delay time
(against PCK ↑)
Prescaler output
rising and falling times
Condition
Min.
Typ.
PCK
MHz
200
ns
PO
External clock input
PCK tR = tF = 6ns
130
220
ns
90
150
ns
PO
External clock input
PCK tR = tF = 6ns
100
280
ns
30
70
ns
1/fPCK
tF
0.8VDD
0.5VDD
0.2VDD
tWL
tPLH
tR
tPHL
0.8VDD
PO
12
ns
Fig. 11. General purpose prescaler timing
PCK
Unit
33
Note) The load of PO pin is 50pF.
tWH
Max.
0.5VDD
0.2VDD
tTLH
tTHL
– 26 –
CXP87452/87460
(7) Others
(Ta = –20 to +75°C, VDD = 3.0 to 5.5V, Vss = 0V)
Item
Symbol
tCFH
tCFL
tDFH
DFG input
tDFL
high and low level widths
DPG minimum pulse width tDPW
CFG input
high and low level widths
DPG minimum
removal time
trem
PBCTL input
high and low level widths
tCTH
tCTL
tEIH
tEIL
tPIH
tPIL
tPSH
tPSL
EXI input
high and low level widths
PMI input
high and low level widths
PMSK input
high and low level widths
Pin
Condition
Min.
Max.
Unit
CFG
tFRC × 24 + 200
ns
DFG
tFRC × 8 + 200
ns
DPG
50
ns
DPG
50
ns
PBCTL
tsys = 2000/fc
tFRC × 8 + tsys + 200
ns
EXI0
EXI1
tsys = 2000/fc
tFRC × 8 + tsys + 200
ns
PMI
tsys + 200
ns
PMSK
tsys + 200
ns
Note 1) tsys indicates three values according to the contents of the clock control register (address; 00FEH)
upper 2 bits (CPU clock selection).
tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11")
Note 2) The value of tFRC is as follows by selecting FRC clock (FRCS: 01EEH bit 7)
When PS0 is selected, tFRC = 1000/fc (ns)
When PS1 is selected, tFRC = 2000/fc (ns)
– 27 –
CXP87452/87460
Fig. 12. Other timings
tCFH
tCFL
0.8VDD
CFG
0.2VDD
tDFH
tDFL
0.8VDD
DFG
0.2VDD
trem
tDPW
trem
0.8VDD
DPG
tCTH
tCTL
0.8VDD
PBCTL
0.2VDD
tEIH
EXI0
EXI0
tEIL
0.8VDD
0.2VDD
– 28 –
CXP87452/87460
tPIH
tPIL
0.8VDD
PMI
0.2VDD
tPSH
tPSL
0.8VDD
PMSK
0.2VDD
– 29 –
CXP87452/87460
Supplement
Fig. 13. Recommended oscillation circuit
AAAA
AAAA
Main clock
EXTAL
XTAL
Rd
C2
C1
Manufacturer
RIVER ELETEC
CO., LTD.
Model
fc (MHz)
C1 (pF)
C2 (pF)
8.00
10
10
5
5
22 (15)
22 (15)
12.00
15
15
16.00
12
12
Rd (Ω)
Circuit
example
0
(i)
0
(i)
10.00
HC-49/U03
12.00
16.00
8.00
KINSEKI LTD.
HC-49/U (-S)
10.00
Mask Option Table
Item
Content
Reset pin pull-up resistor
Non-existent
Existent
Power on reset circuit
Non-existent
Existent
Genaral purpose prescaler oscillation circuit
Input circuit format∗
Non-existent
Existent
CMOS schmitt
TTL schmitt
∗ In PG4/SYNC0/PMI pin and PG5/SYNC1 pin, the input circuit format can be selected every pin.
However, TTL schmitt can not be selected when the supply voltage (VDD) ranges from 3.5V to 5.5V.
– 30 –
CXP87452/87460
Characteristics Curve
IDD vs. fc
IDD vs. VDD
(VDD = 5V, Ta = 25°C, Typical)
20.0
1/4 dividing mode
10.0
1/16 dividing mode
1/2 dividing mode
30
5.0
SLEEP mode
1.0
0.5
0.1
(100µA)
0.05
(50µA)
IDD – Supply current [mA]
IDD – Supply current [mA]
(fc = 16MHz, Ta = 25°C, Typical)
1/2 dividing mode
20
1/4 dividing mode
10
1/16 dividing mode
0.01
(10µA)
SLEEP mode
3
4
5
6
0
7
5
10
15 16
fc – System clock [MHz]
VDD – Supply voltage [V]
IDD vs. VDD
IDD vs. fc
(fc = 12MHz, Ta = 25°C, Typical)
(VDD = 3.3V, Ta = 25°C, Typical)
1/2 dividing mode
20.0
30
1/4 dividing mode
1/16 dividing mode
5.0
SLEEP mode
1.0
0.5
0.1
(100µA)
0.05
(50µA)
IDD – Supply current [mA]
IDD – Supply current [mA]
10.0
20
1/2 dividing mode
10
1/4 dividing mode
0.01
(10µA)
1/16 dividing mode
SLEEP mode
3
4
5
6
7
0
5
10
fc – System clock [MHz]
VDD – Supply voltage [V]
– 31 –
15 16
CXP87452/87460
Unit: mm
100PIN QFP (PLASTIC)
+ 0.4
14.0 – 0.01
17.9 ± 0.4
15.8 ± 0.4
+ 0.1
0.15 – 0.05
23.9 ± 0.4
+ 0.4
20.0 – 0.1
A
0.65
+ 0.35
2.75 – 0.15
±0.12 M
0° to 15°
DETAIL A
0.8 ± 0.2
(16.3)
0.15
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SOLDER PLATING
SONY CODE
QFP-100P-L01
LEAD TREATMENT
EIAJ CODE
∗QFP100-P-1420-A
LEAD MATERIAL
COPPER / 42 ALLOY
PACKAGE WEIGHT
1.4g
JEDEC CODE
100PIN LQFP (PLASTIC)
16.0 ± 0.2
∗
14.0 ± 0.1
75
51
76
(15.0)
50
0.5 ± 0.2
A
26 (0.22)
100
1
0.5 ± 0.08
+ 0.08
0.18 – 0.03
25
+ 0.2
1.5 – 0.1
+ 0.05
0.127 – 0.02
0.1
0.1 ± 0.1
0° to 10°
0.5 ± 0.2
Package Outline
DETAIL A
NOTE: Dimension “∗” does not include mold protrusion.
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY/PHENOL RESIN
SONY CODE
LQFP-100P-L01
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
∗QFP100-P-1414-A
LEAD MATERIAL
42 ALLOY
JEDEC CODE
PACKAGE WEIGHT
– 32 –
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