Sony CXP88624 Cmos 8-bit single chip microcomputer Datasheet

CXP88616/88624
CMOS 8-bit Single Chip Microcomputer
Description
The CXP88616/88624 is a CMOS 8-bit microcomputer which consists of A/D converter, serial
interface, timer/counter, time base timer, high
precision timing pattern generation circuits, PWM
output, VISS/ VASS circuit, remote control receiving
circuit, VSYNC separator and the measurement
circuit which measure signals of capstan FG
amplifier and drum FG/PG amplifier and other servo
systems, as well as basic configurations like 8-bit
CPU, ROM, RAM and I/O port. They are integrated
into a single chip.
Also, CXP88616/88624 provides sleep/stop function
which enables to lower power consumption.
100 pin QFP (Plastic)
Structure
Silicon gate CMOS IC
Features
• A wide instruction set (213 instructions) which cover various types of data
— 16-bit arithmetic/multiplication and division/boolean bit operation instructions
• Minimum instruction cycle
250ns at 16MHz operation
• Incorporated ROM capacity
16K bytes (CXP88616)
24K bytes (CXP88624)
• Incorporated RAM capacity
672 bytes (including PPG RAM)
• Peripheral function
— A/D converter
8 bits, 14 channels, successive approximation system
(Conversion time of 20µs/16MHz)
— Serial interface
Incorporated 8-bit, 8-stage FIFO for data
(Auto transfer for 1 to 8 bytes), 1 channel
— Timer
8-bit timer/counter, 2 channels
19-bit time base timer
— High precision timing pattern generation PPG 19 pins 32-stage programmable circuit
RTG 5 pins, 1 channel
5-bit, 8-satge FIFO (RECCTL control), 1channel
— PWM/DA gate output
12 bits, 2 channels (Repetitive frequency 62.5kHz/16MHz)
DA gate pulse output, 13 bits, 2 channels
— Analog signal input circuit
Capstan FG amplifier circuit
Drum FG amplifier circuit
Drum PG amplifier circuit
PBCTL amplifier circuit
— CTL write/rewrite circuit
Recording current control circuit
— Servo input control
Capstan FG, Drum FG/PG, CTL input
— VSYNC separator
— FRC capture unit
Incorporated 26-bit and 8-stage FIFO
— VISS/VASS circuit
Pulse duty auto detection circuit
— 32kHz timer/event counter
32kHz oscillation circuit, ultra-low speed instruction mode
— Remote control reception circuit
8-bit pulse measurement counter, 6-stage FIFO
— Tri-state output
PPG 1 pin, output 8 pins
— Pseudo HSYNC output function
— High speed head switching circuit
• Interruption
20 factors, 15 vectors, multi-interruption possible
• Standby mode
SLEEP/STOP
• Package
100-pin plastic QFP
• Piggyback/evaluation chip
CXP88800 100-pin ceramic QFP
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E96108-ST
FIFO
8 BIT TIMER/COUNTER1
8 BIT TIMER/COUNTER 0
CTL R/W CONTROL
PSEUDO HSYNC GENERATOR
HGO
RECCTL
CTLCIN
12 BIT PWM GENERATOR CH1
PULSE WIDTH
COUNTER
PWM1
DAA1
VISS/VASS
FIFO
SERVO INPUT
CONTROL
REMOCON INPUT
GAIN
CONTROL
AMP
V SYNC SEPARATOR
EC
SELECT
SERIAL
INTERFACE UNIT
(CH0)
A/D CONVERTER
AVDD
12 BIT PWM GENERATOR CH0
14
AMPVDD
3
2
5
4
2
2
2
2
INT0
NMI
2
A
CH0
Vss
MP
VDD
XTAL
EXTAL
PRESCALER/
TIME BASE TIMER
RAM
672 BYTES
CLOCK
GENERATOR/
SYSTEM CONTROL
RST
FIFO
CH1
REALTIME PULSE
GENERATOR
5
RAM
FIFO
ROM
16K/24K BYTES
SPC700
CPU CORE
19
PROGRAMABLE
PATTERN
GENERATOR
FRC
CAPTURE UNIT
INT2
INTERRUPT CONTROLLER
AVREF
PWM0
DAA0
DDO
RMC
CFG
DFG
DPG
CTLAMP
EXI0
EXI1
SYNC
TO
EC
SCK0
CS0
SI0
SO0
AN0 to AN13
PPO0 to PPO18
AVss
AMPVSS
INT1/NMI
2
RTO3 to RTO7
PORT A
PORT B
PORT C
PORT D
PORT E
PORT F
PORT G
PORT H
–2–
PORT I
Block Diagram
PH0 to PH7
8
PI0 to PI7
PG0, 1
2
8
PF4 to PF7
PF0 to PF3
4
4
PE2 to PE5
PD0 to PD7
8
4
PC0 to PC7
8
PE0, 1, 6, 7
PB0 to PB7
8
4
PA0 to PA7
8
CXP88616/88624
CXP88616/88624
PE4/EXI0
PE3/SYNC
PE2
PE1
PE0
NC
NC
VSS
VDD
NC
PA7/PPO7
PA6/PPO6
PA5/PPO5
PA4/PPO4
PA3/PPO3
PA2/PPO2
PA1/PPO1
PA0/PPO0/HGO
PB7/PPO15
PB6/PPO14
Pin Assignment (Top View)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
PB5/PPO13
1
80
PE5/EXI1
PB4/PPO12
2
79
PE6/PWM0/DAA0
PB3/PPO11
3
78
PE7/PWM1/DAA1
PB2/PPO10
4
77
CFG
PB1/PPO9
5
76
DFG
PB0/PPO8
6
75
DPG
PC7/RTO7
7
74
VREFOUT
PC6/RTO6
8
73
AMPVSS
PC5/RTO5
9
72
CTLSAMPI
PC4/RTO4
10
71
CTLFAMPO
PC3/RTO3
11
70
CTLAG
PC2/PPO18
12
69
CTLAMP (+)
PC1/PPO17
13
68
CTLAMP (–)
PC0/PPO16
14
67
CTLCIN (–)
PI7
15
66
CTLCIN (+)
PI6
16
65
RECCTL (+)
PI5
17
64
RECCTL (–)
PI4
18
63
AMPVDD
PI3
19
62
RECCAP
PI2
20
61
VDD
PI1/EC/INT2
21
60
AN0/ANOUT
PI0/INT0/ENV-DET
22
59
AN1
PD7/SI0
23
58
AN2
PD6/SO0
24
57
AN3
PD5/SCK0
25
56
PF0/AN4
PD4/CS0
26
55
PF1/AN5
PD3/TO/DDO/ADJ/SRVO
27
54
AVDD
PD2
28
53
AVREF
PD1/RMC
29
52
AVSS
PD0/INT1/NMI
30
51
PF2/AN6
PF3/AN7
PF4/AN8
PF5/AN9
PF6/AN10
PF7/AN11
PG0/AN12
EXTAL
PG1/AN13
XTAL
VSS
RST
MP
PH0
PH1
PH2
PH3
PH4
PH5
PH6
PH7
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Note) 1. NC (Pin 90) is always connected to VDD. NC (Pins 86 and 87) are left open.
2. VDD (Pins 61 and 89) are both connected to VDD
3. Vss (Pins 41 and 88) are both connected to GND.
4. MP (Pin 39) must be connected to GND.
–3–
CXP88616/88624
Pin Description
Symbol
I/O
PA0/PPO0
/HGO
Output/Real-time
output/Output
PA1/PPO1
to
PA7/PPO7
Output/
Real-time output
PB0/PPO8
to
PB7/PPO15
Output/
Real-time output
PC0/PPO16
to
PC2/PPO18
I/O/
Real-time output
Description
(Port A)
8-bit output port. Data is
gated with PPO contents
by OR-gate and they are
output.
(8 pins)
(Port B)
8-bit output port. Data is
gated with PPO contents
by OR-gate and they are
output.
Tri-state control is possible.
(8 pins)
(Port C)
8-bit output port. I/O can be
set in a unit of single bits.
Data is gated with PPO or
RT contents by OR-gate
and they are output.
(8 pins)
Pseudo HSYNC output pin.
Programmable pattern generator (PPG)
output. Functions as high precision realtime pulse output port.
(19 pins)
PA0 can be tri-state controlled with PPG.
Real-time pulse generator (RTG) output.
Functions as high precision real-time
pulse output port.
(5 pins)
PC3/RTO3
to
PC7/RTO7
I/O/
Real-time output
PD0/INT1/
NMI
I/O/Input/Input
Input pin to request external interruption
and non-maskable interruption.
PD1/RMC
I/O/Input
Remote control receiving circuit input pin.
PD2
I/O
PD3 /TO
DDO/SRVO
Timer/counter, CTL duty detector and
servo amplifier output pin.
PD4/CS0
I/O/Output/Output/ (Port D)
Output
8-bit output port. I/O can be
set in a unit of single bits.
I/O/Input
(8 pins)
PD5/SCK0
I/O/I/O
Serial clock (CH0) I/O pin.
PD6/SO0
I/O/Output
Serial data (CH0) output pin.
PD7/SI0
I/O/Input
Serial data (CH0) input pin.
PE0
Output
PE1
Output
PE2
Input
PE3/SYNC
Input/Input
PE4/EXI0
Input/Input
PE5/EXI1
Input/Input
PE6/PWM0/
DAA0
Output/Output
PE7/PWM1/
DAA1
Output/Output
Serial chip select (CH0) input pin.
(Port E)
Composite sync signal input pin.
8-bit port. Bits 2, 3, 4 and 5
External input pin for FRC capture unit.
are for inputs; bits 0, 1, 6
(2 pins)
and 7 are for outputs.
(8 pins)
PWM output pin.
(2 pins)
–4–
DA gate pulse
output pin.
(2 pins)
CXP88616/88624
Description
Description
I/O
Analog circuit internal
waveform output pin.
AN0/ANOUT
Input/Output
AN1 to AN3
Input
PF0/AN4
to
PF3/AN7
Input/Input
PF4/AN8
to
PF7/AN11
Output/Input
PG0/AN12
PG1/AN13
Input/Input
(Port G)
2-bit input port.
(2 pins)
Output
(Port H)
8-bit output port; N-ch open drain output of medium drive voltage (12V)
and large current (12mA).
(8 pins)
PH0 to PH7
PI0/INT0/
ENV-DET
I/O/Input
(Port F)
Lower 4 bits are for inputs; upper 4 bits are for
outputs. Lower 4 bits are standby release input
pins.
(8 pins)
(Port I)
8-bit I/O port. I/O can be
set in a unit of single bits.
Function as standby
release input can be set in
a unit of single bits.
(8 pins)
Analog input pin for
A/D converter.
(14 pins)
Input pin to request
Trigger pulse input
external interruption.
pin for head
Active when falling
switching.
edge.
Input pin to request
External event input external interruption.
pin for timer/counter. Active when falling
edge.
PI1/EC/
INT2
I/O/Input/Input
PI2 to PI7
I/O
CFG
Input
Capstan FG input pin.
DFG
Input
Drum FG input pin.
DPG
Input
Drum PG input pin.
RECCTL (+)
RECCTL (–)
I/O
RECCTL signal output pin.
(2 pins)
CTLCIN (+)
CTLCIN (–)
Output
Connected to RECCTL (+) and RECCTL (–) with the internal switch for
playback. (2 pins)
CTLAMP (+)
CTLAMP (–)
Input
Input PBCTL signal with capacitor coupled.
(2 pins)
CTLFAMPO
Output
PBCTL signal 1st amplifier output.
CTLSAMPI
Input
PBCTL signal 2nd amplifier input.
RECCAP
I/O
Capacitor connecting pin for the slope setting of the CTL writing
trapezoidal wave.
VREFOUT
Output
Capacitor connecting pin for the VREF level smoothing of DPG, DFG
and CFG.
CTLAG
Output
Capacitor connecting pin for the CTL and AGND smoothing.
PBCTL signal input pin.
(2 pins)
AMPVSS
Analog signal input circuit GND pin.
AMPVDD
Analog signal input circuit power supply pin.
–5–
CXP88616/88624
Symbol
I/O
Description
EXTAL
Input
XTAL
Output
Connecting pin of crystal oscillator for system clock. When supplying
the external clock, input it to EXTAL pin and input the opposite phase
clock to XTAL pin.
RST
Input
System reset pin; Low level active.
NC pin. Connect Pin 90 to VDD and leave Pins 86 and 87 open.
NC
MP
Input
Positive power supply pin for A/D converter.
AVDD
AVREF
Test mode input pin. Always connect to GND.
Input
Reference voltage input pin for A/D converter.
AVSS
GND pin for A/D converter.
VDD
Positive power supply pin.
VSS
GND pin. Connect both Vss pins to GND.
–6–
CXP88616/88624
Input/Output Circuit Formats for Pins
Pin
Circuit format
AA
AA
AA
AA
AAA
AAA
AAA
Port A
PA0/PPO0/
HGO
1 pin
AAAA
AAAA
HOUT
PPO0
MPX
PA0
Data bus
RD (Port A)
HSEL
HOUTE
When reset
AA
AA
Hi-Z
MPX
Output becomes active from high impedance by
data writing to port.
PPO1
PPG control status register bit 0
Tri-state control selection
AAA
AAA
PPO1
PA1/PPO1
PA1
1 pin
Data bus
AA
AA
Hi-Z
RD (Port A)
Output becomes active from high impedance by data
writing to port.
AA
AA
Port A
AAAA
AAAA
PPO data
PA2/PPO2
to
PA7/PPO7
Port A data
Hi-Z
Data bus
RD (Port A)
6 pins
Output becomes active from high impedance
by data writing to port.
Port B
AAAA
AAAA
AAAA
RTO data
PB0/PPO8
to
PB7/PPO15
Port B data
Data bus
RD (Port B)
8 pins
Port B tri-state
control
–7–
AA
AA
Hi-Z
CXP88616/88624
Circuit format
Pin
Port C
PC0/PPO16
to
PC2/PPO18
PC3/RTO3
to
PC7/RTO7
AAAA
AAAA
AAAA
PPO, RTO data
Port C data
When reset
AA
AA
AA
AA
Input protection circuit
Port C direction
Hi-Z
IP
Data bus
RD (Port C)
8 pins
AAAA
AAAA
AAAA
AAAA
RD (Port C direction)
Port D
AA
AA
A
A
Port D data
PD0/INT1/
NMI
PD1/RMC
PD4/CS0
PD7/SI0
Port D direction
IP
Data bus
RD (Port D)
4 pins
Schmitt input
PD1...Remote control circuit
PD0...Interruption circuit
PD4, 7...Serial CH0
Port D
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AA
AAA
AA
AAA
AA
AAA
Port D data
PD2
Port D direction
Data bus
1 pin
RD (Port D)
Port D
Hi-Z
AA
AA
A
A
Hi-Z
IP
Port D function
select
PD3...
PD3/TO/
DDO/SRVO
Timer/counter, CTL duty
detection circuit,
32kHz timer,
amplifier circuit
MPX
Port D data
Port D direction
Data bus
4 pins
RD (Port D)
–8–
AA
AA
AA
AA
IP
Hi-Z
CXP88616/88624
Pin
AAAA
AAAAAAA
AAA
AAA
AAA
AA
AAA AAA
AA
AA
Circuit format
When reset
Port D
Port D function
select
PD5/SCK0
PD6/SO0
SI0
CH0
AA
AA
A
MPX
Port D data
MPX
Port D direction
Data bus
2 pins
Hi-Z
IP
Note)
PD5 is schmitt input
PD6 is inverter input
RD (Port D)
SI0 CH0
Port E
AAA
AAA
PE0
PE1
AA
AA
Port E data
Data bus
Hi-Z
Hi-Z control
RD (Port E)
2 pins
Port E
AAAA
Schmitt input
PE2
Data bus
IP
Hi-Z
RD (Port E)
1 pin
Port E
AAAA
Schmitt input
PE3/SYNC
PE4/EXI0
PE5/EXI1
PE3
PE4
PE5
IP
Servo input
Data bus
RD (Port E)
3 pins
Note) For PE3/SYNC, CMOS schmitt input or TTL schmitt input can be selected
with the mask option.
–9–
Hi-Z
CXP88616/88624
Pin
AAAA
AAAA
AAAA
AAAA
Circuit format
Port E
AA
AA
AA
AA
Port/DA/PWM
select
PE6/PWM0/
DAA0
PE7/PWM1/
DAA1
When reset
DA gate output or
PWM output
AA
AA
MPX
Port E data
Data bus
High level
Hi-Z control
2 pins
RD (Port E)
AA
AA
AA
AA
AAAA
AAAA
AA
AA
AAAA
Input multiplexer
IP
AN0/ANOUT
A/D converter
Hi-Z
From amplifier circuit
Analog output control
1 pin
AN1
to
AN3
Input multiplexer
3 pins
Port F
PF0/AN4
to
PF3/AN7
AAAA
AAAA
Hi-Z
A/D converter
IP
Input multiplexer
IP
A/D converter
Hi-Z
Data bus
4 pins
RD (Port F)
Port F
PF4/AN8
to
PF7/AN11
AAAA
AAAAA
AAAAA
AA
AA
AA
AA
Port F data
Data bus
RD (Port F)
Port/AD select
4 pins
Hi-Z
IP
Input multiplexer
– 10 –
A/D converter
CXP88616/88624
Pin
Circuit format
Port G
PG0/AN12
to
PG1/AN13
AA
AA
AAAA
Input multiplexer
A/D converter
IP
2 pins
Hi-Z
Data bus
RD (Port G)
AAA
AAA
AA
AA
Port H
PH0
to
PH7
When reset
Medium drive
voltage12 V
Port H data
Hi-Z
Large current 12mA
Data bus
8 pins
AAAA
AA
AAAA
AAAA
AA
AAAA
AA
AA
AA
AA
AAAA
AAAA
AA
AAAA
AA
AAAA
AA
AA
AA
AA
RD (Port H)
Port I
Port I data
PI0/INT0/
EVN-DET
PI1/EC/INT2
Port I direction
IP
Data bus
RD (Port I)
Hi-Z
Edge detection
Standby release
Interruption circuit
Data bus
2 pins
RD (Port I direction)
Port I
Port I data
PI2
to
PI7
Port I direction
IP
Data bus
RD (Port I)
Edge detection
Standby release
Data bus
6 pins
RD (Port I direction)
– 11 –
Hi-Z
CXP88616/88624
Pin
CTLAMP (+)
CTLAMP (–)
CTLFAMPO
When reset
Circuit format
A
AAA
AAAA
A
AA
A
AA
A
AAAAA
A
AA
AAAAA
AAAAA
AA
AA
AAAAA
AAAA AA
AA
CTLAG
CTLAMP (+)
IP
IP
1/2AMPVDD
CTLFAMPO
CTLAMP (–)
3 pins
CTLSAMPI
Input pin charge control
Input pin charge control
IP
1/2AMPVDD
LPF circuit
CTLAG
1 pin
CFG
DFG
DPG
AAAAA
AAAAA
AA
AA
AAAA AA
AA
Input pin charge control
IP
LPF circuit
1/2AMPVDD
VREFOUT
3 pins
AA
AA
AA
AA
AMPVDD
CTLAG
VREFOUT
IP
AMPVSS
VREFOUT... CFG, DFG,
DPG amplifiers
CTLAG........ CTL amplifier
2 pins
– 12 –
1/2AMPVDD
CXP88616/88624
Pin
When reset
Circuit format
AMPVDD
AA
AAAA
AA
AA
AA
Recording current
control circuit
Write current select
RTO6
RECCTL (+)
IP
RTO7
Hi-Z
CTLCIN (+) pin
RTO3
AMPVSS
1 pin
RTG control permission
AMPVDD
AA
AA
AAAA
AA
AA
Recording current
control circuit
Write current select
RECCTL (–)
RTO7
IP
RTO6
CTLCIN (–) pin
RTO3
1 pin
Hi-Z
AMPVSS
RTG control permission
AAA
From RECCTL (+) pin
IP
CTLCIN (+)
RTO3
Hi-Z
RTG control permission
1 pin
CTLCIN (–)
AMPVSS
AAA
From RECCTL (–) pin
IP
RTO3
Hi-Z
RTG control permission
1 pin
AMPVSS
RTG control permission
RECCAP
RTO5
AA
A
A
IP
1 pin
Recording current control circuit
– 13 –
Low level
CXP88616/88624
Pin
AA
AA
AA
AA
EXTAL
XTAL
EXTAL
2 pins
XTAL
AA
AA
1 pin
• Shows the circuit
composition during
oscillation.
IP
Mask option
RST
When reset
Circuit format
AA
AA
• Feedback resistor is
removed and XTAL
becomes High level
during stop.
Oscillation
Pull up resistor
AA
Schmitt input
OP
IP
– 14 –
Low level
CXP88616/88624
Absolute Maximum Ratings
Item
(Vss = 0V reference)
Symbol
Rating
Unit
V
AVDD
–0.3 to +7.0
AVss to +7.0 ∗1
AVSS
–0.3 to +0.3
V
VDD
Supply voltage
AMPVDD AMPVSS to +7.0 ∗2
Remarks
V
V
V
Input voltage
VIN
–0.3 to +0.3
–0.3 to +7.0 ∗3
Output voltage
VOUT
–0.3 to +7.0 ∗3
V
Medium drive output voltage
VOUTP
–0.3 to +15.0
V
High level output current
IOH
–5
mA
High level total output current
∑IOH
–50
mA
Total of output pins
IOL
15
mA
Other than large current output
ports (value per pin)
IOLC
20
mA
Large current output port ∗4
(value per pin)
Low level total output current
∑IOL
130
mA
Total of output pins
Operating temperature
Topr
–20 to +75
°C
Storage temperature
Tstg
–55 to +150
°C
Allowable power dissipation
PD
600
mW
AMPVSS
V
Low level output current
Port H
QFP package type
∗1) AVDD and VDD must not exceed +0.3V.
∗2) AMPVDD and VDD must not exceed +0.3V.
∗3) VIN and VOUT must not exceed VDD +0.3V.
∗4) The large current output port is port H (PH).
Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should
better take place under the recommended operating conditions. Exceeding those conditions may
adversely affect the reliability of the LSI.
– 15 –
CXP88616/88624
Recommended Operating Conditions
Item
Supply voltage
Analog power supply
High level input voltage
Symbol
Min.
Max.
4.5
5.5
3.5
5.5
2.5
5.5
AVDD
4.5
5.5
V
Guaranteed data hold operation range
during STOP
∗1
AMPVDD
4.5
5.5
V
∗2
VIH
0.7VDD
VDD
V
∗3
VIHS
0.8VDD
VDD
V
VIHTS
2.2
VDD
V
VDD
VIHEX
Low level input voltage
Operating temperature
(Vss = 0V reference)
VDD – 0.4 VDD + 0.3
Unit
Remarks
Guaranteed operation range for 1/2 and 1/4
frequency dividing clock
V
V
Guaranteed operation range for 1/16 frequency
dividing clock or during SLEEP mode
CMOS schmitt input ∗4
TTL schmitt input ∗5
EXTAL pin∗6
∗3
VIL
0
0.3VDD
V
VILS
0
0.2VDD
V
VILTS
0
0.8
V
CMOS schmitt input ∗4
TTL schmitt input ∗5
VILEX
–0.3
0.4
V
EXTAL pin ∗6
Topr
–20
+75
°C
∗1) AVDD and VDD should be set to the same voltage.
∗2) AMPVDD and VDD should be set to the same voltage.
∗3) Normal input port (each pin of PC, PD2, PD3, PD6, PF0 to PF3, PG and PI2 to PI7), MP pin
∗4) Each pin of RST, PD0/INT1/NMI, PD1/RMC, PD4/CS0, PD5/SCK0, PD7/SI0, PE2, PE3/SYNC, PE4/EXI0,
PE5/EXI1, PI0/INT0, PI1/EC/INT2 (For PE3/SYNC, when CMOS schmitt input is selected with mask
option.)
∗5) PE3/SYNC (when TTL schmitt input is selected with mask option.)
∗6) Specifies only during external clock input.
– 16 –
CXP88616/88624
Electrical Characteristics
DC Characteristics (VDD = 4.5 to 5.5V)
Item
High level
output voltage
Low level
output voltage
Symbol
VOH
VOL
IIHE
Input current
(Ta = –20 to +75°C, Vss = 0V reference)
Pins
Conditions
Min.
Typ.
Max. Unit
PA to PD,
PE0 to PE1,
PE6 to PE7,
PF4 to PF7,
PH (VOL only)
PI
VDD = 4.5V, IOH = –0.5mA
4.0
V
VDD = 4.5V, IOH = –1.2mA
3.5
V
PH
EXTAL
IILE
VDD = 4.5V, IOL = 1.8mA
0.4
V
VDD = 4.5V, IOL = 3.6mA
0.6
V
VDD = 4.5V, IOL = 12.0mA
1.5
V
VDD = 5.5V, VIH = 5.5V
0.5
40
µA
VDD = 5.5V, VIL = 0.4V
–0.5
–40
µA
–1.5
–400
µA
IILR
RST∗1
VDD = 5.5V, VIL = 0.4V
I/O leakage
current
IIZ
PA to PG,
PI, MP,
AN0 to AN3,
RST∗1
VDD = 5.5V,
VI = 0, 5.5V
±10
µA
Open drain
output leakage
current (N-CH
Tr off state)
ILOH
PH
VDD = 5.5V
VOH = 12V
50
µA
27
45
mA
1.8
8
mA
10
µA
20
pF
16MHz crystal oscillation (C1 = C2 = 15pF)
IDD1
VDD = 5.5V∗3
IDDS1
Supply
current∗2
IDD2
IDDS2
SLEEP mode
VDD, VSS
VDD = 5.5V
STOP mode
(EXTAL pin oscillation stop)
IDDS3
VDD = 5V±0.5V
Input capacity
CIN
PC, PD,
PE2 to PE5
PF, PG, PI,
RECCTL (+),
RECCTL (–),
CTLAMP (+),
CTLAMP (–),
CTLSAMPI,
CFG, DFG,
DPG
Clock 1MHz
0V other than the measured pins
10
∗1) RST pin specifies the input current when the pull-up resistor is selected, and specifies leakage current
when no resistor is selected.
∗2) When entire output pins are open.
∗3) When setting upper 2 bits (CPU clock selection) of clock control register (CLC: 00FEH) to "00" and
operating in high speed mode (1/2 frequency dividing clock).
– 17 –
CXP88616/88624
AC Characteristics
(1) Clock timing
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Item
Symbol
Pin
Condition
Min.
System clock frequency
fC
XTAL
EXTAL
Fig. 1, Fig. 2
1
System clock input pulse width
tXL,
tXH
XTAL
EXTAL
Fig. 1, Fig. 2
External clock drive
28
tCR,
tCF
tEH,
tEL
tER,
tEF
XTAL
EXTAL
Fig. 1, Fig. 2
External clock drive
EC
Fig. 3
EC
Fig. 3
System clock input rise and
fall times
Event count clock input
pulse width
Event count clock input
rise and fall times
Typ.
Max.
Unit
16
MHz
ns
200
tsys + 200∗1
ns
ns
20
ms
∗1) tsys indicates three values according to the contents of the clock control register (CLC; 00FEH) upper 2 bits
(CPU clock selection).
tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11")
Fig. 1. Clock timing
1/fc
VDD – 0.4V
EXTAL
XTAL
0.4V
tXH
tCF
tXL
tCR
AAAA AAAAA
AAAA
AAAAA
AAAA AAAAA
Fig. 2. Clock applied condition
Crystal oscillation
Ceramic oscillation
EXTAL
External clock
EXTAL
XTAL
C1
C2
XTAL
74HC04
Fig. 3. Event count clock timing
0.8VDD
EC
0.2VDD
tEH
tEF
tEL
tER
tTH
tTF
tTL
tTR
– 18 –
CXP88616/88624
(2) Serial transfer (CH0)
Item
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Symbol
Pin
Condition
Min.
Max.
Unit
CS0 ↓ → SCK0
delay time
tDCSK
SCK0
Chip select transfer mode
(SCK0 = output mode)
tsys + 200
ns
CS0 ↑ → SCK0
floating delay time
tDCSKF SCK0
Chip select transfer mode
(SCK0 = output mode)
tsys + 200
ns
CS0 ↓ → SO0
delay time
tDCSO
SO0
Chip select transfer mode
tsys + 200
ns
CS0 ↑ → SO0
floating delay time
tDCSOF SO0
Chip select transfer mode
tsys + 200
ns
CS0
high level width
tWHCS CS0
Chip select transfer mode
tsys + 200
ns
SCK0
cycle time
tKCY
Input mode
2tsys + 200
ns
SCK0
16000/fc
ns
SCK0
high and low level widths
tKH
tKL
Input mode
tsys + 100
ns
SCK0
Output mode
8000/fc – 50
ns
SI0 input set-up time
(against SCK0 ↑)
tSIK
SCK0 input mode
100
ns
SI0
SCK0 output mode
200
ns
SI0 input hold time
(against SCK0 ↑)
tKSI
tsys + 200
ns
SI0
100
ns
SCK0 ↓ → SO0 delay time
tKSO
SO0
Output mode
SCK0 input mode
SCK0 output mode
SCK0 input mode
SCK0 output mode
tsys + 200
ns
100
ns
Note 1) tsys indicates three values according to the contents of the clock control register (CLC; 00FEH) upper
2 bits (CPU clock selection).
tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11")
Note 2) The load of SCK0 output mode and SO0 output delay time is 50pF + 1TTL.
– 19 –
CXP88616/88624
Fig. 4. Serial transfer timing (CH0)
tWHCS
0.8VDD
CS0
0.2VDD
tKCY
tDCSK
tKL
tDCSKF
tKH
0.8VDD
0.8VDD
SCK0
0.2VDD
tSIK
tKSI
0.8VDD
Input data
SI0
0.2VDD
tDCSO
tKSO
tDCSOF
0.8VDD
SO0
Output data
0.2VDD
– 20 –
CXP88616/88624
(3) A/D converter characteristics
(Ta = –20 to +75°C, VDD = AVDD = 4.5 to 5.5V, AVREF = 4.0 to AVDD, Vss = AVss = 0V reference)
Item
Symbol
Pin
Condition
Min.
Typ.
Resolution
Only for A/D converter
operation
Ta = 25°C
VDD = AVDD = AVREF = 5.0V
VDD = AVss = 0V
Linearity error
Absolute error
Sampling time
Reference input voltage
VREF
AVREF
Analog input voltage
VIAN
AN0 to AN7
IREF
8
Bits
±1
LSB
±2
LSB
µs
µs
AVDD – 0.5
AVDD
V
0
AVREF
V
1.0
mA
10
µA
0.6
Operation mode
AVREF current
Unit
160/fADC ∗1
12/fADC ∗1
tCONV
tSAMP
Conversion time
Max.
SLEEP mode
STOP mode
32kHz operation mode
AVREF
Fig. 5. Definitions of A/D converter terms
Digital conversion value
FFH
FEH
∗1) fADC indicates the below values due to the contents
of bit 0 (ADCCK) of the ADC operation clock selection
register (MSC: 01FFH), bits 7 (PCK1) and 6 (PCK0) of
the clock control register (address: 00FEH).
Linearity error
01H
00H
VFT
VZT
ADCCK
Analog input
PCK1, PCK0
0 (φ/2 selection)
1 (φ selection)
00 (φ = fEX/2)
fADC = fc/2
fADC = fc
01 (φ = fEX/4)
fADC = fc/4
fADC = fc/2
11 (φ = fEX/16)
fADC = fc/16
fADC = fc/8
– 21 –
CXP88616/88624
(4) Interruption, reset input (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Item
Symbol
Pin
Condition
Min.
Max.
Unit
External interruption high and
low level widths
tIH
tIL
INT0
INT1
INT2
NMI
1
µs
Reset input low level width
tRSL
RST
32/fc
µs
Fig. 6. Interruption input timing
tIH
INT0
INT1
INT2
NMI
(Falling edge)
tIL
0.8VDD
0.2VDD
Fig. 7. Reset input timing
tRSL
RST
0.2VDD
– 22 –
CXP88616/88624
Analog Circuit Characteristics
(1) Amplifier circuit reference voltage characteristics
(Ta = –20 to +75°C, VDD = AMPVDD = 5.0V, Vss = AMPVSS = 0V reference)
Item
Reference level
output voltage
Symbol
VOR
Pin
Min.
Typ.
Max.
Unit
VREFOUT
2.2
2.4
2.6
V
CTLAG
2.15
2.35
2.55
V
VREFOUT = VREFOUT + 0.5V
3.50
6.5
mA
VREFOUT = VREFOUT – 0.5V
–0.30
–0.85
mA
CTLAG = CTLAG + 0.5V
2.80
5.5
mA
CTLAG = CTLAG – 0.5V
–0.30
–0.85
mA
VREFOUT
Reference level
output current
IOR
CTLAG
Conditions
(2) CTL 1st amplifier characteristics
(Ta = –20 to +75°C, VDD = AMPVDD = 5.0V, Vss = AMPVSS = 0V, CTLAG reference)
Item
Voltage gain ∗1
Offset voltage
Input resistance
Charge switch ON
resistance
Symbol
AVCTL1
Pin
Min.
Typ.
Max.
Unit
Gain = 16dB
RECCTL (–) = 0V
12.5
14.5
16.5
dB
Gain = 27dB
RECCTL (–) = 0V
23.5
25.5
27.5
dB
RECCTL (+) Gain = 42dB
CTLFAMPO∗2 RECCTL (–) = 0V
39.0
41.5
44.0
dB
Gain = 58dB
RECCTL (–) = 0V
54.5
57.0
59.5
dB
CTLAMP (+) and CTLAMP (–)
= open
–40
0
+40
mV
CTLAMP (+)
Charge switch OFF
CTLAMP (+) = +0.2V
26.0
44.5
kΩ
CTLAMP (–)
Charge switch OFF
CTLAMP (–) = +0.2V
1.20
2.0
kΩ
CTLAMP (+)
Charge switch ON
CTLAMP (+) = +0.5V
560
1010
Ω
CTLAMP (–)
Charge switch ON
CTLAMP (–) = +0.5V
560
1010
Ω
VOSCTL1
RINCTL1
RCCTL1
RECCTL and
CTLCIN connection RREAD
switch ON resistance
CTLCIN 0V fix
RWRITE
switch ON resistance
Conditions
RECCTL (+) During CTL read operation,
CTLCIN (+) CTLCIN (+) – RECCTL (+) = 0.2V
315
400
770
Ω
RECCTL (–) During CTL read operation,
CTLCIN (–) CTLCIN (–) – RECCTL (–) = 0.2V
315
400
770
Ω
CTLCIN (+)
During CTL write operation,
CTLCIN (+) = AMPVSS + 0.2V
250
310
Ω
CTLCIN (–)
During CTL write operation,
CTLCIN (–) = AMPVSS + 0.2V
250
310
Ω
∗1) When CTLCIN (+), CTLAMP (+) pins and CTLCIN (–), CTLAMP (–) pins are AC coupled, and then the
signal is input from RECCTL (+) pin.
∗2) The result after measuring the CTLFAMPO output waveform or voltage gain.
Note) The gain increases by approximately 1.5dB when the AC coupling capacitor (47µF) is connected to
CTLAMP (+) and CTLAMP (–) pins, and the signal is input from CTLAMP (+) and CTLAMP (–) pins.
– 23 –
CXP88616/88624
(3) CTL 2nd amplifier characteristics
(Ta = –20 to +75°C, VDD = AMPVDD = 5.0V, Vss = AMPVSS = 0V, CTLAG reference)
Item
Voltage gain∗1, ∗2
Symbol
Pin
Min.
Typ.
Max.
Unit
Gain = 5dB
4.8
5.8
6.8
dB
Gain = 11dB
10.4
11.5
12.6
dB
Gain = 16dB
15.3
16.5
17.7
dB
Gain = 20dB
19.3
20.5
21.7
dB
Conditions
AVCTL2
LPF cut-off
frequency ∗1, ∗2
fCCTL
fDC – 3dB
15.0
25.0
40.0
kHz
Offset voltage ∗2
VOSCTL2
CTLSAMPI = open
–50
0
+50
mV
Comparator level = +100mV0-p
70.0
100
130
mV0-p
CTLSAMPI Comparator level = +250mV0-p
215
245
275
mV0-p
Comparator level = +400mV0-p
370
400
430
mV0-p
Comparator level = –100mV0-p
–70.0
–100
–130
mV0-p
Comparator level = –250mV0-p
–220
–250
–280
mV0-p
Comparator level = –400mV0-p
–370
–400
–430
mV0-p
10.0
18.0
Comparator level ∗2
VCCTL
Input resistance
RINCTL2
Charge switch OFF
CTLSAMPI = +0.2V
Charge switch ON
resistance
RCCTL2
Charge switch ON
CTLSAMPI = +0.5V
770
kΩ
1140
Ω
∗1) When the signal is input with the AC coupling capacitor (47µF) connected to CTLSAMPI pin.
∗2) The result after measuring the output waveform of amplifier internal low-pass filter or voltage value.
(4) CTLAMP characteristics (1st amplifier + 2nd amplifier)
(Ta = –20 to +75°C, VDD = AMPVDD = 5.0V, Vss = AMPVSS = 0V reference)
Item
Symbol
Pin
Conditions
Min.
Typ.
Max.
Unit
31.8
35.0
38.2
dB
±300
mV0-p
0.10
mV0-p
Voltage gain ∗1
AVCTL
CTL 1st amplifier gain = 16dB
CTL 2nd amplifier gain = 20dB
RECCTL (–) = 0V
Input amplitude
(peak value)
VPKCTL
RECCTL (–) = 0V
Input sensitivity
VSCTL
Input dead band
VNSCTL
RECCTL (+)
CTL 1st amplifier gain = 58dB
CTL 2nd amplifier gain = 20dB
Comparator level = +400mV0-p
–400mV0-p
0.015
RECCTL (–) = 0V
0.08
0.04
mV0-p
∗1) As for other combinations of the amplifier gains, CTL 1st amplifier and CTL 2nd amplifier are added
respectively.
Note) The result when the signal is input from RECCTL (+) pin with CTL 1st amplifier + CTL 2nd amplifier after
performing AC coupling of CTLCIN (+), CTLAMP (+) pins and CTLCIN (–), CTLAMP (–) pins, and
CTLFAMPO, CTLSAMPI pins.
– 24 –
CXP88616/88624
(5) CFGAMP characteristics
(Ta = –20 to +75°C, VDD = AMPVDD = 5.0V, Vss = AMPVDD = 0V, VREFOUT reference)
Item
Voltage gain ∗1, ∗2
LPF cut-off
frequency ∗1, ∗2
Offset voltage ∗2
Comparator
judgment level
width ∗2
Input sensitivity ∗1
Input dead band ∗1
Symbol
Pins
Min.
Typ.
Max.
Unit
Gain = 0dB
–0.3
0.6
2.2
dB
Gain = 20dB
19.2
20.8
22.4
dB
Gain = 34dB
33.2
34.8
36.4
dB
Gain = 38dB
37.0
38.7
40.4
dB
fCCFG
fDC – 3dB
30.0
55.0
80.0
kHz
VOSCFG
CFG = open
–50
0
+50
mV
260
320
360
mVp-p
VCCFG
Comparator schimitt width
= 320mVp-p
Comparator schimitt width
= 160mVp-p
110
155
200
mVp-p
Gain = 38dB
Comparator level = 320mVp-p
4.20
5.00
mVp-p
Gain = 38dB
Comparator level = 160mVp-p
2.10
2.40
mVp-p
AVCFG
VSCFG
VNSCFG
CFG
Conditions
Gain = 38dB
Comparator level = 320mVp-p
3.40
4.10
mVp-p
Gain = 38dB
Comparator level = 160mVp-p
1.50
2.00
mVp-p
5.5
8.3
kΩ
Input resistance
RINCFG
Charge switch OFF
CFG = +0.2V
Charge switch ON
resistance
RCCFG
Charge switch ON
CFG = +0.5V
Digital output
DTYCFG
waveform duty ∗1, ∗3
Input amplitude
(peak value) ∗1
CFG = sine wave with 50%
duty
VPKCFG
48.0
455
710
Ω
50.0
52.0
%
±2.4
V0-p
∗1) When the signal is input with the AC coupling capacitor (47µF) connected to CFG pin.
∗2) The result after measuring the output waveform of amplifier internal low-pass filter or voltage value.
∗3) The result after measuring the digital signal waveform output from the amplifier circuit.
– 25 –
CXP88616/88624
(6) DFGAMP characteristics
(Ta = –20 to +75°C, VDD = AMPVDD = 5.0V, Vss = AMPVSS = 0V, VREFOUT reference)
Item
Voltage gain ∗1, ∗2
LPF cut-off
frequency ∗1, ∗2
Offset voltage ∗2
Comparator
judgment level
width ∗2
Input sensitivity ∗1
Input dead band ∗1
Symbol
Pins
Min.
Typ.
Max.
Unit
Gain = 0dB
–0.3
0.6
2.2
dB
Gain = 20dB
19.2
20.8
22.4
dB
Gain = 34dB
33.2
34.8
36.4
dB
Gain = 38dB
37.0
38.7
40.4
dB
fCDFG
fDC – 3dB
30.0
55.0
80.0
kHz
VOSDFG
DFG = open
–50
0
+50
mV
Comparator schmitt width
= 320mVp-p
260
320
360
mVp-p
Comparator schmitt width
= 160mVp-p
110
155
200
mVp-p
Gain = 38dB
Comparator level = 320mVp-p
4.20
5.00
mVp-p
Gain = 38dB
Comparator level = 160mVp-p
2.10
2.40
mVp-p
AVDFG
VCDFG
VSDFG
VNSDFG
DFG
Conditions
Gain = 38dB
Comparator level = 320mVp-p
3.40
4.10
mVp-p
Gain = 38dB
Comparator level = 160mVp-p
1.50
2.00
mVp-p
5.5
8.3
kΩ
Input resistance
RINDFG
Charge switch OFF
DFG = +0.2V
Charge switch ON
resistance
RCDFG
Charge switch ON
DFG = +0.5V
Digital output
DTYDFG
waveform duty ∗1, ∗3
Input amplitude
(peak value) ∗1
DFG = sine wave of 50%
duty
VPKDFG
48.0
455
710
Ω
50.0
52.0
%
±2.4
V0-p
∗1) When the signal is input with the AC coupling capacitor (47µF) connected to DFG pin.
∗2) The result after measuring the output waveform of amplifier internal low-pass filter or voltage value.
∗3) The result after measuring the digital signal waveform output from the amplifier circuit.
– 26 –
CXP88616/88624
(7) DPGAMP characteristics
(Ta = –20 to +75°C, VDD = AMPVDD = 5.0V, Vss = AMPVSS = 0V, VREFOUT reference)
Item
Voltage gain ∗1, ∗2
LPF cut-off
frequency ∗1, ∗2
Offset voltage ∗2
Comparator level ∗2
Input sensitivity ∗1
Input dead band ∗1
Symbol
Pins
Conditions
AVDPG
Min.
Typ.
Max.
Unit
11.1
12.0
13.2
dB
fCDPG
fDC – 3dB
30.0
55.0
85.0
kHz
VOSDPG
DFG = open
–35
0
+35
mV
Comparator level = 600mV0-p
570
605
640
mV0-p
Comparator level = 400mV0-p
370
400
432
mV0-p
Comparator level = 200mV0-p
175
200
220
mV0-p
Comparator level = 100mV0-p
72
100
125
mV0-p
Comparator level = –600mV0-p
–572
–605
–643
mV0-p
Comparator level = –400mV0-p
–368
–400
–438
mV0-p
Comparator level = –200mV0-p
–174
–200
–223
mV0-p
Comparator level = –100mV0-p
–71
–100
–124
mV0-p
Comparator level
= 600mV0-p, 200mV0-p
150
180
mV0-p
Comparator level
= 400mV0-p, 100mV0-p
100
120
mV0-p
Comparator level
= –600mV0-p, –200mV0-p
–155
–185
mV0-p
Comparator level
= –400mV0-p, –100mV0-p
–109
–130
mV0-p
VCDPG
VSDPG
VNSDPG
DPG
Comparator level
= 600mV0-p, 200mV0-p
113
142
mV0-p
Comparator level
= 400mV0-p, 100mV0-p
70
90
mV0-p
Comparator level
= –600mV0-p, –200mV0-p
–120
–150
mV0-p
Comparator level
= –400mV0-p, –100mV0-p
–80
–103
mV0-p
24.0
44.5
kΩ
Input resistance
RINDPG
Charge switch OFF
DPG = +0.2V
Charge switch ON
resistance
RCDPG
Charge switch ON
DPG = +0.5V
Input amplitude
(peak value) ∗1
VPKDPG
450
860
Ω
±2.4
V
∗1) When the signal is input with the AC coupling capacitor (47µF) connected to DPG pin.
∗2) The result after measuring the output waveform of amplifier internal low-pass filter or voltage value.
– 27 –
CXP88616/88624
(8) CTL write circuit characteristics
(Ta = –20 to +75°C, VDD = AMPVDD = 5.0V, Vss = AMPVSS = 0V reference)
Item
Output resistance
Symbol
Min.
Typ.
Max.
Unit
RECCAP = AMPVDD – 0.5V
450
625
1005
Ω
RECCAP = AMPVDD + 0.5V
410
555
840
Ω
Write current = 2.0mA
1.3
2.0
2.9
mA
Write current = 2.5mA
1.7
2.5
3.7
mA
Write current = 3.0mA
2.1
3.1
4.5
mA
Write current = 3.5mA
RECCTL (+)
RECCTL (–) Write current = 4.0mA
2.6
3.6
5.2
mA
2.9
4.0
5.9
mA
Write current = 4.5mA
3.3
4.6
6.6
mA
Write current = 5.0mA
3.7
5.1
7.2
mA
Write current = 5.5mA
4.0
5.6
8.0
mA
Write current = 6.0mA
4.4
6.1
8.9
mA
ROH
ROL
Output current ∗1
Pins
IOREC
RECCAP
Conditions
∗1) The current value which flows when RECCTL (+) pin and RECCTL (–) pin are shorted.
(9) Amplifier operating current characteristics
(Ta = –20 to +75°C, VDD = AMPVDD = 5.0V, Vss = AMPVSS = 0V reference)
Item
Amplifier operating
current
Symbol
Pins
Conditions
When the amplifier is operating ∗1
IAMP
AMPVDD
When the amplifier is not
operating
Min.
Typ.
Max.
Unit
7.6
12.0
mA
10
µA
∗1) The CTL recording current is added during CTL write.
Note) The amplifier operation and NOT-operation is controlled according to the contents of amplifier power
supply control register (ASWC: 05E2H) bits 5, 4, 1 and 0.
– 28 –
CXP88616/88624
Supplement
Fig. 8. Recommended oscillation circuit
AAAA
AAAA
AAAA
EXTAL
XTAL
Rd
C1
Manufacturer
RIVER
ELETEC
CO., LTD.
C2
Model
HC-49/U03
fc (MHz)
C1 (pF)
C2 (pF)
8.00
10
10
5
5
8.00
16 (12)
16 (12)
10.00
16 (12)
16 (12)
12.00
12
12
16.00
12
12
10.00
Rd (Ω)
0
12.00
16.00
KINSEKI LTD.
HC-49/U (-S)
Mask option table
Item
Reset pin pull-up resistor
Input circuit format∗1
Content
Non-existent
Existent
CMOS schmitt
TTL schmitt
∗1) The input circuit format can be selected for PE3/SYNC pin.
– 29 –
0
CXP88616/88624
Characteristics Curve
IDD vs. VDD
IDD vs. fc
(fc = 16MHz, Ta = 25°C, Typical)
(VDD = 5.0V, Ta = 25°C, Typical)
50
30
1/2 dividing mode
20
25
1/4 dividing mode
1/2 dividing mode
5
1/16 dividing mode
2
SLEEP mode
1
IDD – Supply current [mA]
IDD – Supply current [mA]
10
20
15
1/4 dividing mode
10
0.5
1/16 dividing mode
5
0.2
0.1
1
SLEEP mode
2
3
4
5
6
0
7
5
10
fc – System clock [MHz]
VDD – Supply voltage [V]
– 30 –
15 16
CXP88616/88624
Package Outline
Unit: mm
100PIN QFP (PLASTIC)
23.9 ± 0.4
+ 0.4
20.0 – 0.1
+ 0.1
0.15 – 0.05
80
51
+ 0.4
14.0 – 0.1
17.9 ± 0.4
15.8 ± 0.4
50
81
A
31
100
1
0.65
30
+ 0.15
0.3 – 0.1
0.13
+ 0.2
0.1 – 0.05
+ 0.35
2.75 – 0.15
M
0° to 10°
DETAIL A
0.8 ± 0.2
(16.3)
0.15
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
QFP-100P-L01
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
QFP100-P-1420
LEAD MATERIAL
42/COPPER ALLOY
PACKAGE MASS
1.7g
JEDEC CODE
– 31 –
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