CY23020-3 10-output, 400-MHz LVPECL Zero Delay Buffer Features • • • • • • • • • • Overview 400-ps max Total Timing Budget (TTB) window 10 LVPECL outputs 1 LVPECL differential input Selectable output frequency range from 100 to 400 MHz Multiply by 2 option 15-ps RMS Cycle-Cycle Jitter Power-down mode Lock indicator 3.3V power supply Available in 48-pin QFN package TheCY23020-3 is a high-performance 400-MHz LVPECL Output phase-locked loop (PLL)-based zero delay buffer (ZDB) designed for high- speed clock distribution applications. The device features a guaranteed TTB window specifying all occurrences of output clocks with respect to the input reference clock across variations in voltage, temperature, process, frequency, and ramp rate. Additionally, the CY23020-3 can be used as a fan-out buffer via the S[1:2] control pins. In this mode, the PLL is bypassed and the reference clock is routed to the output buffers. Block Diagram Pin Configurations LOCK ÷1/÷2 REF+ REFFBIN+ FBIN- ÷1 PLL ÷2 48 47 46 45 44 F B O U T + V D D F B I N + F B I N - N C 43 L O C K 42 V D D C 41 G N D C 40 R E F - 39 R E F + 38 V D D 37 Q 9 + FBOUT+ FBOUT- 1 FBOUT- Q1+ Q1- 2 GND GND 35 Q2+ Q2- 3 Q1- Q8- 34 4 Q1+ Q8+ 33 5 VDD 6 Q2+ Q7+ 31 7 Q2- Q7- 30 8 GND GND 29 9 Q3- Q6- 28 10 Q3+ Q6+ 27 11 VDD 12 Q4+ Q3+ Q9- 36 Q3Q4+ VDD 32 CY23020-3 Q4- S1:2 RANGE MUL Q5+ Q4- Control Logic Q6+ Q6Q7+ Q7Q8+ Q8Q9+ Q9- Cypress Semiconductor Corporation Document #: 38-07473 Rev. *A • 3901 North First Street Q 4 - G N D S 2 13 14 15 • S 1 16 M U L R A N G E G N D C V D D C V D D C G N D C G N D Q 5 - 17 18 19 20 21 22 23 24 San Jose, CA 95134 VDD 26 Q5+ 25 • 408-943-2600 Revised June 5, 2003 CY23020-3 Pin Definitions[1] Pin Name Pin No. Pin Type Pin Description REF+ REF- 39 40 I Reference Inputs. Output signals are synchronized to the crossing point of REF+ and REF– signals. In DC mode, the REF+/REF- inputs must be held at opposite logical states. For optimal performance, the impedances seen by these two inputs must be equal. FBIN+ FBIN- 46 45 I Feedback Inputs. Input FBIN+/FBIN- must be fed by one of the outputs to ensure proper functionality. If the trace between FBIN+/FBIN- and FBOUT+/FBOUT- is equal in length to the traces between the outputs and the signal destinations, then the signals received at the destinations will be synchronized to the clock signal at REF+/REF- inputs. In DC mode, FBIN+/FBIN- inputs must be held at opposite logical states. For best performance, the impedances seen by these two inputs must be equal. FBOUT+ FBOUT- 48 1 O Feedback Output. In order to complete the phase locked loop, similar polarity outputs must be connected back to the FBIN+ and FBIN- pins. Any of the outputs may actually be used as the feedback source. Q1+, Q1- 4, 3 O Differential Q1 Outputs. Refer to Tables 1,2, and 3 for configuration. Q2+, Q2- 6, 7 O Differential Q2 Outputs. Refer to Tables 1,2, and 3 for configuration. Q3+, Q3- 10, 9 O Differential Q3 Outputs. Refer to Tables 1,2, and 3 for configuration. Q4 +, Q4- 12, 13 O Differential Q4 Outputs. Refer to Tables 1,2, and 3 for configuration. Q5+, Q5- 25, 24 O Differential Q5 Outputs. Refer to Tables 1,2, and 3 for configuration. Q6+, Q6- 27, 28 O Differential Q6 Outputs. Refer to Tables 1,2, and 3 for configuration. Q7+, Q7- 31, 30 O Differential Q7 Outputs. Refer to Tables 1,2, and 3 for configuration. Q8+, Q8- 33, 34 O Differential Q8 Outputs. Refer to Tables 1,2, and 3 for configuration. Q9+, Q9- 37, 36 O Differential Q9 Outputs. Refer to Tables 1,2, and 3 for configuration. 18 I Frequency Range Selection Input. To determine the correct connection for this pin, refer to Table 2. This should be a static input 43 O PLL Locked Output. When this output is HIGH, the PLL in the CY23020-3 is in steady state operation mode (Locked). When this signal is LOW, the PLL is in the process of locking onto the reference signal. 16, 15 I Output/PLL Enable Selection Bits. Refer to Table 1. RANGE 1 LOCK S1:2 VDDC 20, 21, 42 P Analog Power Connection. Connect to 3.3V. GNDC 19, 22, 41 G Analog Ground Connection. Connect to common system ground plane. VDD 5, 11, 26, 32, 38, 47 P Output Buffer Power Connections. Connect 3.3V GND 2, 8, 14, 23, 29, 35 G Ground Connections. Connect to common system ground plane. MUL[2] 17 I Multiplication Factor Select. When set HIGH, the outputs will run at twice the speed of the reference signal. This should be a static input. NC 44 NC Do Not Connect. This pin must be left floating. This pin is used by the factory for testing purposes. Table 1. Output Configuration S1 S2 Outputs 0 0 Three-state 0 1 Reserved 1 0 Reference Input 1 1 PLL Output PLL Shutdown Shutdown Enabled Notes: 1. There are no power-up sequence requirements on the power supply pins of the CY23020-3. 2. RANGE and MUL have a ~100k pull-down. Document #: 38-07473 Rev. *A Page 2 of 9 CY23020-3 Inserting Other Devices in Feedback Path Table 2. Frequency Range Setting RANGE Output Frequency Range 0 100–200 MHz 1 200–400 MHz Table 3. Frequency Multiplication Table MUL Output Frequency 0 = REF 1 = 2 * REF How to Implement Zero Delay Typically, ZDBs multiply (fan-out) single-clock signals quantity while simultaneously reducing or mitigating the time delay associated with passing the clock through a buffering device. In many cases the output clock is adjusted, in phase, to occur later or more often before the device’s input clock to compensate for a design’s physical delay inadequacies. Most commonly this is done using a simple PCB trace as a time delay element. The longer the trace the earlier the output clock edges occur with respect to the reference input clock edges. In this way such effects as undesired transit time of a clock signal across a PCB can be compensated for. Due to the fact that the device has an external feedback path the user has a wide range of control over its output to input skewing effect. One of these is to be able to synchronize the outputs of an external clock that is resultant from any of the output clocks. This implementation can be applied to any device (ASIC, multiple output clock buffer/driver, etc.) which is put into the feedback path. Referring to Figure 1, if the traces between the ASIC/buffer and the destination of the clock signal(s) (A) are equal in length to the trace between the buffer and the FBIN pin (B), the signals at the destination(s) device (C) will be driven high at the same time the Reference clock provided to the ZDB goes high. Synchronizing the other outputs of the ZDB to the outputs from the ASIC/Buffer is more complex however, as any propagation delay in the ASIC/Buffer must be accounted for. There are constraints when inserting other devices. If the devices contain PLLs or excessively long delay times they can easily cause the overall clocking system to become unstable as the components interact. For these designs it is advisable to contact Cypress for applications support. C Reference Signal Zero Delay Buffer ASIC/ Buffer Feedback Input A B Figure 1. Output Buffer in Feedback Path Table 4. Absolute Maximum Ratings[3] Parameter Description Rating Unit VDD Voltage on any VDD pin with respect to GND –0.5 to +5.0 V VIN Voltage on any input pin with respect to GND –0.5 to VDD + 0.5 V TSTG Storage Temperature –65 to +150 °C TA Operation Temperature (QFN) –40 to 85 °C 135 °C TJ Junction Temperature Table 5. PECL DC Output Specification [4] VCC = 3.135 Parameter Description Conditions VCC = 3.3 VCC = 3.465 Min. Max. Min. Max. Min. Max. VOH 1.835 2.435 2 2.6 2.165 2.765 VOL 1.135 1.735 1.3 1.9 1.465 2.065 VOH (rel to VCC) –1.3 –0.7 –1.3 –0.7 –1.3 –0.7 VOL(rel to VCC) –2 –1.4 –2 –1.4 –2 –1.4 VMID ((VOH + VOL)/2) 1.485 2.085 1.65 2.25 1.815 2.415 VMID Relative to VCC –1.65 –1.05 –1.65 –1.05 –1.65 –1.05 These result in the following mid point values:[4] Notes: 3. Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating only. Operation of the device at these or any other conditions above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability. 4. The midpoint voltage is average value of a waveform. For differential signals the midpoint is assumed to be the same for both the true and complement since the VOH and VOL of both the true and complement signals in general should be the same. VMID is not necessarily equal to the differential crossover voltage, which may be skewed if there is differential time delays between the signals. Document #: 38-07473 Rev. *A Page 3 of 9 CY23020-3 Table 5. PECL DC Output Specification (continued)[4] VCC = 3.135 Parameter Description Conditions Min. VCC = 3.3 Max. Min. Min. VCC = 3.465 Max. Min. Max. Max. Unit 70°C, VDDmax 100 µA IIL VIN = 0 10 µA IIH VIN = VDD 100 µA IPD Power-down Current Table 6. VDDC = 3.3V ±5%, VDD = 3.3V ±5% (See Test Set-ups, CL = 5 pF) Parameter Description Condition IDD Min. Typ. Loaded, VDD max, Cold, 400 MHz, all outputs switching mA 6 pF REF or FBIN ± Pin Capacitance CL[5] Load Cap VISW Single Ended Input Swing 0.5 1.25 Input Crossover Voltage (expressed relative to VDD) VDD – 1.79 VDD – 0.96 0.9 4 V/ns 0.6 1.1 V VIX VOSW VOX 5 Input Slew Rate SI [7] VOX[8] 5 Unit 300 CIN [6] 4 Max. Measured from VIX MEAS + 0.15 to VIX MEAS –0.15. (20– 80% of a min input swing sig.) Single Ended Output Swing pF V Output Crossing Point VOMID = (VH_MEAS VL_MEAS)/2 VOMID – 0.20 VOMID – 0.20 Output Crossing Point (relative to VDD) VOMID = (VH_MEAS VL_MEAS)/2 VDD – 1.79 VDD – 0.96 Table 7. VDDC = 3.3V ±5%, VDD = 3.3V ±5% (See Test Set-ups, CL = 5 pF) Parameter Description Condition Min. Measured from VIX MEAS + 0.15 to VIX MEAS –0.15. (20–80% of a min input swing sig.) Typ. Max. Unit 0.9 2 V/ns SO Output Rise/Fall Slew Rate DI Input Duty Cycle Input duty cycle 40 60 % DO Output Duty Cycle Differential crossing point 45 55 % TPDIO REFin-FBin prop delay External feedback REF, FB same frequency –50 200 ps TPDIOD REFin-FBin prop delay External feedback REF, FB same frequency x2 –50 150 ps TPDO FBout to any output prop delay –325 –100 ps 150 ps TPDOB Output-Output skew within a bank TPDOB133 Output-Output skew @133 MHz 75 ps TTB Total Timing Budget 400 ps TJCCPP Cycle-Cycle Jitter (1000 cycles) p-p REF and outputs, same frequency 100 ps TJCCRMS RMS Cycle-Cycle Jitter REF and outputs, same frequency 15 ps Tjccop Ref = x2 125 ps Tjrms Ref = x2 30 ps Notes: 5. Same as input. PECL is assumed to drive single point loads. 6. This is the output DC mid-voltage range ± the crossover voltage tolerance. Refer Input Voltage is assumed to be derived from same supply as part. This is why it is spec’d relative to VDD. 7. Crossover is within ± 20% of the center of the minimum swing. 8. Crossover is within ± 20% of the center of the minimum swing. Document #: 38-07473 Rev. *A Page 4 of 9 CY23020-3 0.57 ns All board transmission lines 50Ω and 0.57 ns propagation delay FBIN+ OUT REFIN- OUT 50 FBIN+ 100 = REF- FBIN+ OUT PULSE GEN REFIN+ OUT 50 2.3ns FBIN+ REF+ C Selected to produce 1-2.5V/ns at pin FBOUT+ Q5+ 100 FBOUT- Q1+ 100 Q5- Q4+ CL 100 Q1- Q4- CL Figure 2. Test Set-up 1 Example Document #: 38-07473 Rev. *A Page 5 of 9 CY23020-3 All board transmission lines 50Ω and 0.57ns propagation delay . 0.57ns FBIN+ OUT REFIN- OUT 450 50 50 FBIN+ 100 FBIN+ OUT 50 2.3ns = REF- PULSE GEN REFIN+ OUT 50 450 FBIN+ REF+ C Selected to produce 1-2.5V/ns at pin FBOUT+ Q5+ 100 FBOUT- Q1+ 100 Q5- Q4+ CL 100 Q1- Q4- CL Figure 3. Test Set-up 2 Example[9] Note: 9. The above configuration may provide better termination at the FBIN input. Document #: 38-07473 Rev. *A Page 6 of 9 CY23020-3 All board transmission lines 50Ω and 0.57ns propagation delay. 0.57ns FBIN+ OUT REFIN - OUT 50 FBIN -+ 100 = REF - FBIN+ OUT PULSE GEN REFIN+ OUT 50 FBIN+ REF+ C Selected to produce 1-2.5V/ns at pin FBOUT+ 100 100 FBOUT - Q1+ 100 Q5+ CL Q 5- Q4+ CL 100 Q1- Q4- Figure 4. Test Set-up 3 Example[10] Ordering Information Ordering Code CY23020LFI-3 CY23020LFI-3T Package Type Temperature Range 48-pin QFN Industrial, –40°C to +85°C 48-pin QFN–Tape and Reel Industrial, –40°C to +85°C Note: 10. If accurate pin-pin skew is not obtainable with the load capacitors, a third configuration can be made with no load C. In this case only pin-pin skew is characterized. Part must be in PLL bypass mode. Document #: 38-07473 Rev. *A Page 7 of 9 CY23020-3 Package Drawing and Dimension 48-lead QFN (7 × 7 mm) LF48 51-85152-*A Total Timing Budget and TTB are trademarks of Cypress Semiconductor. All product and company names listed in this document are the trademarks of their respective holders. Document #: 38-07473 Rev. *A Page 8 of 9 © Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY23020-3 Document History Page Document Title: CY23020-3 10-output, 400-MHz LVPECL Zero Delay Buffer Document Number: 38-07473 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 118965 11/05/02 HWT New Data Sheet *A 126939 06/10/03 RGL Fixed the block diagram (removed the C1 input) Document #: 38-07473 Rev. *A Page 9 of 9