Cypress CY2509 Spread awareâ ¢, ten/eleven output zero delay buffer Datasheet

CY2509/10
Spread Aware™, Ten/Eleven Output Zero
Delay Buffer
Features
Key Specifications
■
Spread Aware™ designed to work with spread spectrum
frequency timing generator (SSFTG) reference signals
Operating voltage: ...............................................3.3 V±10%
Well suited to both 100- and 133-MHz designs
Ten (CY2509) or eleven (CY2510) low-voltage complementary
metal oxide semiconductor (LVCMOS) / low-voltage transistortransistor logic (LVTTL) outputs.
Cycle-to-cycle jitter: ................................................. <100 ps
Operating range: ......................... 40 MHz < fOUT < 140 MHz
■
■
50 ps typical peak cycle-to-cycle jitter
■
Single output enable pin for CY2510 version, dual pins on
CY2509 devices allow shutting down a portion of the outputs
■
3.3 V power supply
■
On-chip 25  damping resistors
■
Available in 24-pin thin shrunk small outline package
(TSSOP) package
■
Improved tracking skew, but narrower frequency support limit
when compared to W132-09B/10B
Output to output skew: ............................................. <100 ps
Phase error jitter: ...................................................... <100 ps
Block Diagram
FBIN
CLK
FBOUT
PLL
Q0
Q1
Q2
OE0:4
Q3
Q4
OE
Q5
Q6
OE5:8
Q7
Q8
Q9
Configuration of these blocks dependent upon specific option being used
Cypress Semiconductor Corporation
Document Number: 38-07230 Rev. *E
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised July 5, 2011
CY2509/10
Contents
Pin Definitions .................................................................. 4
Overview ............................................................................ 4
Spread Aware..................................................................... 5
How to Implement Zero Delay ......................................... 5
Inserting Other Devices in Feedback Path ..................... 5
Absolute Maximum Ratings ............................................ 6
DC Electrical Characteristics .......................................... 6
AC Electrical Characteristics .......................................... 6
Ordering Code Definitions ........................................... 7
Document Number: 38-07230 Rev. *E
Package Drawing and Dimensions ................................. 8
Acronyms .......................................................................... 9
Document Conventions ................................................... 9
Units of Measure ......................................................... 9
Sales, Solutions, and Legal Information ...................... 11
Worldwide Sales and Design Support ....................... 11
Products .................................................................... 11
PSoC Solutions ......................................................... 11
Page 2 of 11
CY2509/10
Pin Configurations
1
24
CLK
VDD
2
23
AVDD
Q0
3
22
VDD
Q1
4
21
Q9
20
Q8
19
GND
CY2510
Q2
5
GND
6
GND
7
18
GND
Q3
8
17
Q7
Q4
9
16
Q6
VDD
10
15
Q5
OE
11
14
VDD
FBOUT
12
13
FBIN
AGND
1
24
CLK
VDD
2
23
AVDD
Q0
3
22
VDD
Q1
4
21
Q8
Q2
5
20
Q7
GND
6
19
GND
GND
7
18
GND
Q3
8
17
Q6
Q4
9
16
Q5
VDD
10
15
VDD
OE0:4
11
14
OE5:8
FBOUT
12
13
FBIN
CY2509
Document Number: 38-07230 Rev. *E
AGND
Page 3 of 11
CY2509/10
Pin Definitions
Pin
Name
Pin No
(2509)
Pin No
(2510)
Pin
Type
CLK
24
24
I
Reference input: Output signals Q0:9 will be synchronized to this signal.
FBIN
13
13
I
Feedback input: This input must be fed by one of the outputs (typically FBOUT) to
ensure proper functionality. If the trace between FBIN and FBOUT is equal in length
to the traces between the outputs and the signal destinations, then the signals
received at the destinations will be synchronized to the CLK signal input.
Q0:8
3, 4, 5, 8,
9, 16, 17,
20, 21
3, 4, 5, 8,
9, 15, 16,
17, 20
O
Integrated series resistor outputs: The frequency and phase of the signals
provided by these pins will be equal to the reference signal if properly laid out. Each
output has a 25  series damping resistor integrated.
Q9
n/a
21
O
Integrated series resistor output: The frequency and phase of the signal provided
by this pin will be equal to the reference signal if properly laid out. This output has a
25 series damping resistor integrated.
FBOUT
12
12
O
Feedback output: This output has a 25  series resistor integrated on chip. Typically
it is connected directly to the FBIN input with a trace equal in length to the traces
between outputs Q0:9 and the destination points of these output signals.
AVDD
23
23
P
Analog power connection: Connect to 3.3 V. Use ferrite beads to help reduce noise
for optimal jitter performance.
AGND
1
1
G
Analog ground connection: Connect to common system ground plane.
VDD
2, 10, 15,
22
2, 10, 14,
22
P
Power connections: Connect to 3.3 V. Use ferrite beads to help reduce noise for
optimal jitter performance.
GND
6, 7, 18,
19
6, 7, 18,
19
G
Ground connections: Connect to common system ground plane.
OE
n/a
11
I
Output enable input: Tie to VDD (HIGH, 1) for normal operation. When brought to
GND (LOW, 0) all outputs are disabled to a LOW state.
OE0:4
11
n/a
I
Output enable input: Tie to VDD (HIGH, 1) for normal operation. When brought to
GND (LOW, 0) outputs Q0:4 are disabled to a LOW state.
OE5:8
14
n/a
I
Output enable input: Tie to VDD (HIGH, 1) for normal operation. When brought to
GND (LOW, 0) outputs Q5:8 are disabled to a LOW state.
Pin Description
Overview
The CY2509/10 is a PLL-based clock driver designed for use in
dual inline memory modules. The clock driver has output
frequencies of up to 133 MHz and output to output skews of less
than 250 ps. The CY2509/10 provides minimum cycle-to-cycle
and long-term jitter, which is of significant importance to meet the
tight input-to-input skew budget in DIMM applications.
The current generation of 256- and 512-megabyte memory
modules needs to support 100-MHz clocking speeds. Especially
for cards configured in 16x4 or 8x8 format, the clock signal
provided from the motherboard is generally not strong enough to
meet all the requirements of the memory and logic on the DIMM.
The CY2509/10 takes in the signal from the motherboard and
Document Number: 38-07230 Rev. *E
buffers out clock signals with enough drive to support all the
DIMM board clocking needs. The CY2509/10 is also designed to
meet the needs of new PC133 SDRAM designs, operating to
133 MHz.
The CY2509/10 was specifically designed to accept SSFTG
signals currently being used in motherboard designs to reduce
EMI. Zero delay buffers which are not designed to pass this
feature through may cause skewing failures.
Output enable pins allow for shutdown of output when they are
not being used. This reduces EMI and power consumption.
Page 4 of 11
CY2509/10
Figure 1. CY2510 Example Schematic
VDD
0.1F
AGND
2
VDD
3
Q0
VDD 22
4
Q1
Q9
21
5
Q2
Q8
20
6
GND
7
GND
8
Q3
Q7
17
9
Q4
Q6
16
10
VDD
Q5
15
11
OE
VDD 14
12
FBOUT
FBIN 13
CLK 24
AVDD 23
0.1F
3.3V
FB
10 F
0.1F
CY2510
VDD
0.1F
1
10 F
FB
VDD
GND 19
GND 18
0.1F
VDD
Spread Aware™
Many systems being designed now utilize a technology called
Spread Spectrum Frequency Timing Generation. Cypress has
been one of the pioneers of SSFTG development, and we
designed this product so as not to filter off the Spread Spectrum
feature of the Reference input, assuming it exists. When a zero
delay buffer is not designed to pass the SS feature through, the
result is a significant amount of tracking skew which may cause
problems in systems requiring synchronization.
For more details on Spread Spectrum timing technology, please
see the Cypress application note titled, “EMI Suppression
Techniques with SSFTG ICs.”
How to Implement Zero Delay
Typically, Zero Delay Buffers (ZDBs) are used because a
designer wants to provide multiple copies of a clock signal in
phase with each other. The whole concept behind ZDBs is that
the signals at the destination chips are all going HIGH at the
same time as the input to the ZDB. In order to achieve this, layout
must compensate for trace length between the ZDB and the
target devices. The method of compensation is described below.
External feedback is the trait that allows for this compensation.
Since the PLL on the ZDB will cause the feedback signal to be
in phase with the reference signal. When laying out the board,
match the trace lengths between the output being used for feed
back and the FBIN input to the PLL.
Inserting Other Devices in Feedback Path
Another nice feature available due to the external feedback is the
ability to synchronize signals up to the signal coming from some
other device. This implementation can be applied to any device
(ASIC, multiple output clock buffer/driver, etc.) which is put into
the feedback path.
Referring to Figure 2, if the traces between the ASIC/buffer and
the destination of the clock signal(s) (A) are equal in length to the
trace between the buffer and the FBIN pin, the signals at the
destination(s) device will be driven HIGH at the same time the
Reference clock provided to the ZDB goes HIGH. Synchronizing
the other outputs of the ZDB to the outputs form the ASIC/Buffer
is more complex however, as any propagation delay in the
ASIC/Buffer must be accounted for.
Figure 2. Additional Buffering Feedback Path Example
Schematic
Reference
Signal
Feedback
Input
Zero
Delay
Buffer
ASIC/
Buffer
A
If it is desirable to either add a little delay, or slightly precede the
input signal, this may also be affected by either making the trace
to the FBIN pin a little shorter or a little longer than the traces to
the devices being clocked.
Document Number: 38-07230 Rev. *E
Page 5 of 11
CY2509/10
Absolute Maximum Ratings [1]
Stresses greater than those listed in this table may cause
permanent damage to the device. These represent a stress
rating only. Operation of the device at these or any other
conditions above those specified in the operating sections of this
specification is not implied. Maximum conditions for extended
periods may affect reliability.
.
Parameter
Description
Min
Max
Unit
V
VDD, VIN
Voltage on any pin with respect to GND
–0.5
+7.0
TSTG
Storage temperature
–65
+150
°C
TA
Operating temperature
0
+70
°C
TB
Ambient temperature under bias
–55
+125
°C
PD
Power dissipation
0.5
–
W
DC Electrical Characteristics:
TA =0 °C to 70 °C, VDD = 3.3 V ±10%
Parameter
Description
Min
Typ
Max
Unit
–
–
200
mA
Input low voltage
–
–
0.8
V
VIH
Input high voltage
2.0
–
VDD+0.3
V
IDD
Supply current
VIL
Test Condition
Unloaded, 100 MHz
VOL
Output low voltage
IOL = 12 mA
VOH
Output high voltage
IOH = –12 mA
–
–
0.8
V
2.1
–
–
V
IIL
Input low current
VIN = 0V
–
–
50
A
IIH
Input high current
VIN = VDD
–
–
50
A
Test Condition
Min
Typ
Max
Unit
load[5]
40
–
140
MHz
AC Electrical Characteristics:
TA = 0 °C to +70 °C, VDD = 3.3 V ±10%
Parameter
Description
fOUT
Output frequency
30-pF
tR
Output rise time
0.8 V to 2.0 V, 30-pF load
–
–
2.1
ns
tF
Output fall time
2.0 V to 0.8 V, 30-pF load
–
–
2.5
ns
–
–
4.5
ns
–
–
4.5
ns
tICLKR
Input clock rise
time[2]
[2]
tICLKF
Input clock fall time
tPEJ
CLK to FBIN Skew
Variation[3, 4]
Measured at VDD/2
–350
0
350
ps
tSK
Output to output skew
All outputs loaded equally
–100
0
100
ps
tD
Duty cycle
30-pF load
43
50
58
%
tLOCK
PLL lock time
Power supply stable
–
–
1.0
ms
tJC
Jitter, Cycle-to-cycle
–
50
100
ps
Notes
1. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
2. Longer input rise and fall time will degrade skew and jitter performance.
3. Skew is measured at VDD/2 on rising edges.
4. Duty cycle is measured at VDD/2.
5. Production tests are run at 133 MHz.
Document Number: 38-07230 Rev. *E
Page 6 of 11
CY2509/10
Ordering Information
Ordering Code
Package Type
Temperature Range
Pb-free
CY2509ZXC-1
24-pin TSSOP
Commercial
CY2509ZXC-1T
24-pin TSSOP - Tape and Reel
Commercial
CY2510ZXC-1
24-pin TSSOP
Commercial
CY2510ZXC-1T
24-pin TSSOP - Tape and Reel
Commercial
Ordering Code Definitions
CY
25
09/10
ZX
C
-
1
T
Tape and Reel
Device option
Commercial temp
Pb-free TSSOP package
Number of buffered outputs
Part family code
Company code
Document Number: 38-07230 Rev. *E
Page 7 of 11
CY2509/10
Package Drawing and Dimensions
24-Lead Thin Shrunk Small Outline Package (4.40-mm Body) Z24
51-85119 * C
Document Number: 38-07230 Rev. *E
Page 8 of 11
CY2509/10
Acronyms
Acronym
Description
EMI
electromagnetic interference
LVCMOS
low-voltage complementary metal oxide
semiconductor
LVTTL
low-voltage transistor-transistor logic
PLL
phase-locked loop
SSFTG
spread spectrum frequency timing generator
TSSOP
thin shrunk small outline package
ZDB
zero delay buffer
Document Conventions
Units of Measure
Symbol
Unit of Measure
°C
degree Celsius
Hz
hertz
kHz
kilohertz
MHz
Megahertz
µA
microamperes
mA
milliamperes
ms
milliseconds
mV
millivolts
ns
nanoseconds

ohms
ppm
parts per million
%
percent
V
volts
Document Number: 38-07230 Rev. *E
Page 9 of 11
CY2509/10
Document History Page
Document Title: CY2509/10 Spread Aware™, Ten/Eleven Output Zero Delay Buffer
Document Number: 38-07230
Rev.
ECN NO.
Issue
Date
Orig. of
Change
Description of Change
**
110495
01/07/02
SZV
Change from Spec number: 38-00914 to 38-07230
*A
122844
12/14/02
RBI
Power up requirements added to Operating Conditions Information
*B
352015
See ECN
RGL
Added Lead-free devices
Added typical jitter and max. VIH numbers
*C
385383
See ECN
RGL
Minor Change: Replaced the wrong package drawing
*D
2897373
03/22/10
CXQ
Updated ordering information table. Removed part numbers CY2509ZC-1,
CY2510ZC-1, CY2509ZC-1T, CY2510ZC-1T
Updated package diagram
Updated copyright section
*E
3302008
07/05/11
CXQ
Updated to latest template
Updated Figure 1 caption
Updated Figure 2 caption
Added Ordering Code Definitions
Updated Package Drawing and Dimensions
Added Acronyms and Units of Measure
Document Number: 38-07230 Rev. *E
Page 10 of 11
CY2509/10
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
Automotive
Clocks & Buffers
Interface
Lighting & Power Control
PSoC Solutions
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psoc.cypress.com/solutions
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PSoC 1 | PSoC 3 | PSoC 5
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cypress.com/go/plc
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cypress.com/go/touch
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cypress.com/go/USB
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© Cypress Semiconductor Corporation, 2010-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
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and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
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Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-07230 Rev. *E
Revised July 5, 2011
Page 11 of 11
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