PRELIMINARY CY28412 Clock Generator for Intel® Grantsdale Chipset Features • Low-voltage frequency select input • I2C Support with read back capabilities • Supports Intel£ P4 and Prescott CPU • Selectable CPU frequencies • Ideal Lexmark Spread Spectrum profile for maximum electromagnetic interference (EMI) reduction • Differential CPU clock pairs • 3.3V power supply • 100 MHz differential SRC clocks • 56-pin SSOP package • 96 MHz differential dot clock • 48 MHz USB clocks • 33 MHz PCI clock CPU SRC PCI REF DOT96 USB_48 x2 / x3 x7 / x8 x8 x2 x1 x1 Block Diagram XIN XOUT CPU_STP# PCI_STP# Pin Configuration VDD_REF REF[1:0] XTAL OSC PLL1 PLL Ref Freq Divider Network FS_[C:A] VTT_PWRGD# IREF PLL2 SDATA SCLK I2C Logic 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 CY28412 PD PCI0 PCI1 VDD_PCI VDD_CPU GND_PCI CPUT[0:1], CPUC[0:1], CPU(T/C)2_ITP] PCI2 VDD_SRC PCI3 SRCT[0:6], SRCC[0:6], PCI4 SATA[T/C] PCI5 GND_PCI VDD_PCI VDD_PCI TEST_SEL/PCIF0 PCI[0:5] ITP_EN/PCIF1 VDD_PCIF PCIF[0:1] VDD_48 USB48/FS_B GND_48 VDD_48 MHz DOT96T DOT96T DOT96C DOT96C VTT_PwrGd#/PD USB_48 SRCT0 SRCC0 SRCT1 STCC1 VDD_SRC GND_SRC SRCT2 SRCC2 SATAT SATAC VDD_REF REF0/FS_C REF1/FS_A GND_REF X1 X2 SDATA SCLK GND_CPU CPUT0 CPUC0 VDD_CPU CPUT1 CPUC1 IREF GND_A VDD_A CPUT2_ITP/SRCT6 CPUC2_ITP/SRCC6 VDD_SRC SRCT5 SRCC5 GND_SRC SRCT4 SRCC4 SRCT3 SRCC3 VDD_SRC 56 SSOP Rev 1.0, November 20, 2006 2200 Laurelwood Road, Santa Clara, CA 95054 Page 1 of 16 Tel:(408) 855-0555 Fax:(408) 855-0550 www.SpectraLinear.com CY28412 Pin Definitions Pin No. Name Type Description 47,46,44,43 CPUT/C O, DIF Differential CPU clock outputs. 39,38 CPUT2_ITP/SRCT6, CPUC2_ITP/SRCC6 O, DIF Selectable Differential CPU or SRC clock output. ITP_EN = 0 @ VTT_PWRGD# assertion = SRC6 ITP_EN = 1 @ VTT_PWRGD# assertion = CPU2 O, DIF Fixed 96-MHz clock output. 16,17 DOT96T, DOT96C 55, 54 REF0/FS_C, REF1/FS_A I/O 14.318-MHz reference clock/3.3V-tolerant input for CPU frequency selection. Input is latched upon assertion (LOW) of VTT_PWRGD#/PD Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications. 14 USB48/FS_B I/O Fixed 48-MHz USB clock output/3.3V-tolerant input for CPU frequency selection. Input is latched upon assertion (LOW) of VTT_PWRGD#/PD Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications. 42 IREF 1,2,5,6,7,8 PCI[0:5] 11 TEST_SEL/PCIF0 12 ITP_EN/PCIF1 49 SCLK 50 SDATA 27,28 SATAT, SATAC I A precision resistor is attached to this pin, which is connected to the internal current reference. O, SE 33-MHz clocks. I/O Free-running 33-MHz clocks/ 3.3V-tolerant input for selecting test mode. Input is latched upon assertion (LOW) of VTT_PWRGD#/PD 1 = All outputs are three-stated for test 0 = All outputs normal operation **This input has an internal pull-down resistor. I/O, SE Free-running 33-MHz clock/CPU2 select (sampled on the VTT_PWRGD# assertion). 1 = CPU2_ITP, 0 = SRC6 I I/O SMBus-compatible SCLOCK. SMBus-compatible SDATA. O, DIF Differential serial reference clock. Recommended output for SATA. 19,20,21,22, SRCT/C[0:5] 25,26,30,31, 32,33,35,36 O, DIF Differential serial reference clocks. 13 PWR VDD_48 3.3V power supply for outputs. 45 VDD_CPU PWR 3.3V power supply for outputs. 3,10 VDD_PCI PWR 3.3V power supply for outputs. 56 VDD_REF PWR 3.3V power supply for outputs. 23,29,37 VDD_SRC PWR 3.3V power supply for outputs. 40 VDD_A PWR 3.3V power supply for PLL. 15 GND_48 GND Ground for outputs. 48 GND_CPU GND Ground for outputs. 4,9 GND_PCI GND Ground for outputs. 53 GND_REF GND Ground for outputs. 24,34 GND_SRC GND Ground for outputs. 41 GND_A GND Ground for PLL. 18 VTT_PWRGD#/PD I, PU 3.3V LVTTL input is a level sensitive strobe used to latch the REF0/FSC, REF1/FSA, USB48/FSB, TEST_SEL/PCIF0 and ITP_EN/PCIF1 inputs. After VTT_PWRGD# (active LOW) assertion, this pin becomes a realtime input for asserting power-down (active HIGH). 52 X1 51 X2 Rev 1.0, November 20, 2006 I 14.318-MHz crystal input. O, SE 14.318-MHz crystal output. Page 2 of 16 CY28412 Frequency Select Pins (FS_A, FS_B and FS_C) Host clock frequency selection is achieved by applying the appropriate logic levels to FS_A, FS_B, FS_C inputs prior to VTT_PWRGD# assertion (as seen by the clock synthesizer). Upon VTT_PWRGD# being sampled low by the clock chip (indicating processor VTT voltage is stable), the clock chip samples the FS_A, FS_B and FS_C input values. For all logic levels of FS_A, FS_B and FS_C VTT_PWRGD# employs a one-shot functionality in that once a valid low on VTT_PWRGD# has been sampled, all further VTT_PWRGD#, FS_A, FS_B and FS_C transitions will be ignored, except in test mode. Serial Data Interface To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. Through the Serial Data Interface, various device functions, such as individual clock output buffers, can be individually enabled or disabled. The registers associated with the Serial Data Interface initial- izes to their default setting upon power-up, and therefore use of this interface is optional. Clock device register changes are normally made upon system initialization, if any are required. The interface cannot be used during system operation for power management functions. Data Protocol The clock driver serial protocol accepts byte write, byte read, block write, and block read operations from the controller. For block write/read operation, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. For byte write and byte read operations, the system controller can access individually indexed bytes. The offset of the indexed byte is encoded in the command code, as described in Table 2. The block write and block read protocol is outlined in Table 3 while Table 4 outlines the corresponding byte write and byte read protocol. The slave receiver address is 11010010 (D2h). Table 1. Frequency Select Table (FS_A, FS_B, FS_C) FS_C FS_B FS_A CPU SRC PCIF/PCI REF0 DOT96 USB 1 0 1 100 MHz 100 MHz 33 MHz 14.318 MHz 96 MHz 48 MHz 0 0 1 133 MHz 100 MHz 33 MHz 14.318 MHz 96 MHz 48 MHz 0 1 1 166 MHz 100 MHz 33 MHz 14.318 MHz 96 MHz 48 MHz 0 1 0 200 MHz 100 MHz 33 MHz 14.318 MHz 96 MHz 48 MHz 0 0 0 266 MHz 100 MHz 33 MHz 14.318 MHz 96 MHz 48 MHz 1 0 0 333 MHz 100 MHz 33 MHz 14.318 MHz 96 MHz 48 MHz 1 1 0 400 MHz 100 MHz 33 MHz 14.318 MHz 96 MHz 48 MHz 1 1 1 Reserved 100 MHz 33 MHz 14.318 MHz 96 MHz 48 MHz Table 2. Command Code Definition Bit Description 7 0 = Block read or block write operation, 1 = Byte read or byte write operation (6:0) Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000' Table 3. Block Read and Block Write Protocol Block Write Protocol Bit 1 2:8 9 10 11:18 19 20:27 28 29:36 37 38:45 46 Description Start Slave address – 7 bits Write = 0 Acknowledge from slave Command Code – 8 bits '00000000' stands for block operation Acknowledge from slave Byte Count – 8 bits Acknowledge from slave Block Read Protocol Bit 1 2:8 9 10 11:18 19 20 21:27 Description Start Slave address – 7 bits Write = 0 Acknowledge from slave Command Code – 8 bits '00000000' stands for block operation Acknowledge from slave Repeat start Slave address – 7 bits Data byte 1 – 8 bits 28 Read = 1 Acknowledge from slave 29 Acknowledge from slave Data byte 2 – 8 bits Acknowledge from slave Rev 1.0, November 20, 2006 30:37 38 Byte count from slave – 8 bits Acknowledge from master Page 3 of 16 CY28412 Table 3. Block Read and Block Write Protocol (continued) Block Write Protocol Bit .... Block Read Protocol Description Bit ...................... 39:46 Description Data byte from slave – 8 bits .... Data Byte (N – 1) – 8 bits 47 .... Acknowledge from slave 48:55 Acknowledge from master .... Data Byte N – 8 bits 56 Acknowledge from master .... Acknowledge from slave .... Data byte N from slave – 8 bits .... Stop .... Acknowledge from master .... Stop Data byte from slave – 8 bits Table 4. Byte Read and Byte Write Protocol Byte Write Protocol Bit 1 2:8 Description 1 Slave address – 7 bits 2:8 Write = 0 10 Acknowledge from slave 19 20:27 Bit Start 9 11:18 Byte Read Protocol Command Code – 8 bits '100xxxxx' stands for byte operation, bits[6:0] of the command code represents the offset of the byte to be accessed Acknowledge from slave Data byte from master – 8 bits 28 Acknowledge from slave 29 Stop Description Start Slave address – 7 bits 9 Write = 0 10 Acknowledge from slave 11:18 19 20 21:27 Command Code – 8 bits '100xxxxx' stands for byte operation, bits[6:0] of the command code represents the offset of the byte to be accessed Acknowledge from slave Repeat start Slave address – 7 bits 28 Read = 1 29 Acknowledge from slave 30:37 Data byte from slave – 8 bits 38 Acknowledge from master 39 Stop Control Registers Byte 0:Control Register 0 Bit @Pup Name 7 1 CPUT2_ITP/SRCT6 CPUC2_ITP/SRCC6 6 1 SRC[T/C]5 SRC[T/C]5 Output Enable 0 = Disable (Hi-Z), 1 = Enable 5 1 SRC[T/C]4 SRC[T/C]4 Output Enable 0 = Disable (Hi-Z), 1 = Enable 4 1 SRC[T/C]3 SRC[T/C]3 Output Enable 0 = Disable (Hi-Z), 1 = Enable 3 1 SATAT/C] SATA[T/C] Output Enable 0 = Disable (Hi-Z), 1 = Enable 2 1 SRC[T/C]2 SRC[T/C]2 Output Enable 0 = Disable (Hi-Z), 1 = Enable 1 1 SRC[T/C]1 SRC[T/C]1 Output Enable 0 = Disable (Hi-Z), 1 = Enable 0 1 SRC[T/C]0 SRC[T/C]0 Output Enable 0 = Disable (Hi-Z), 1 = Enable Rev 1.0, November 20, 2006 Description CPU[T/C]2_ITP/SRC[T/C]6 Output Enable 0 = Disable (Hi-Z), 1 = Enable Page 4 of 16 CY28412 Byte 1: Control Register 1 Bit @Pup Name Description 7 1 CPUT/C SRCT/C PCIF PCI 6 1 DOT_96T/C 5 1 USB_48 4 1 REF0 REF0 Output Enable 0 = Disabled, 1 = Enabled 3 1 REF1 REF1 Output Enable 0 = Disabled, 1 = Enabled 2 1 CPU[T/C]1 CPU[T/C]1 Output Enable 0 = Disable (Hi-Z), 1 = Enabled 1 1 CPU[T/C]0 CPU[T/C]0 Output Enable 0 = Disable (Hi-Z), 1 = Enabled 0 0 CPUT/C SRCT/C PCIF PCI Center Spread Enable 0 = ±0.25% Center Spread, 1 = –0.5% Down Spread DOT_96 MHz Output Enable 0 = Disable (Hi-Z), 1 = Enabled USB_48 MHz Output Enable 0 = Disabled, 1 = Enabled Spread Spectrum Enable 0 = Spread off, 1 = Spread on Byte 2: Control Register 2 Bit @Pup Name Description 7 1 PCI5 PCI5 Output Enable 0 = Disabled, 1 = Enabled 6 1 PCI4 PCI4 Output Enable 0 = Disabled, 1 = Enabled 5 1 PCI3 PCI3 Output Enable 0 = Disabled, 1 = Enabled 4 1 PCI2 PCI2 Output Enable 0 = Disabled, 1 = Enabled 3 1 PCI1 PCI1 Output Enable 0 = Disabled, 1 = Enabled 2 1 PCI0 PCI0 Output Enable 0 = Disabled, 1 = Enabled 1 1 PCIF1 PCIF1 Output Enable 0 = Disabled, 1 = Enabled 0 1 PCIF0 PCIF0 Output Enable 0 = Disabled, 1 = Enabled Byte 3: Control Register 3 Bit @Pup Name 7 0 CPUT2_ITP/SRCT6 CPUC2_ITP/SRCC6 Allow control of SRC[T/C]6 with assertion of SW PCI_STP# 0 = Free-running, 1 = Stopped with SW PCI_STP# 6 0 SRC[T/C]5 Allow control of SRC[T/C]5with assertion of SW PCI_STP# 0 = Free-running, 1 = Stopped with SW PCI_STP# 5 0 SRC[T/C]4 Allow control of SRC[T/C]4 with assertion of SW PCI_STP# 0 = Free-running, 1 = Stopped with SW PCI_STP# 4 0 SRC[T/C]3 Allow control of SRC[T/C]3with assertion of SW PCI_STP# 0 = Free-running, 1 = Stopped with SW PCI_STP# 3 0 SATA[T/C] Allow control of SATA[T/C] with assertion of SW PCI_STP# 0 = Free-running, 1 = Stopped with SW PCI_STP# Rev 1.0, November 20, 2006 Description Page 5 of 16 CY28412 Byte 3: Control Register 3 (continued) Bit @Pup Name Description 2 0 SRC2 Allow control of SRC[T/C]2 with assertion of SW PCI_STP# 0 = Free-running, 1 = Stopped with SW PCI_STP# 1 0 SRC1 Allow control of SRC[T/C]1 with assertion of SW PCI_STP# 0 = Free-running, 1 = Stopped with SW PCI_STP# 0 0 SRC0 Allow control of SRC[T/C]0 with assertion of SW PCI_STP# 0 = Free-running, 1 = Stopped with SW PCI_STP# Byte 4: Control Register 4 Bit @Pup Name Description 7 0 RESERVED RESERVED, Set = 0 6 0 DOT96[T/C] DOT_PWRDWN Drive Mode 0 = Driven in PWRDWN, 1 = Hi-Z 5 0 PCIF1 Allow control of PCIF2 with assertion of SW PCI_STP# 0 = Free-running, 1 = Stopped with SW PCI_STP# 4 0 PCIF0 Allow control of PCIF1 with assertion of SW PCI_STP# 0 = Free-running, 1 = Stopped with SW PCI_STP# 3 0 RESERVED RESERVED, Set = 0 2 1 RESERVED RESERVED, Set = 1 1 1 RESERVED RESERVED, Set = 1 0 1 RESERVED RESERVED, Set = 1 Byte 5: Control Register 5 Bit @Pup Name Description 7 0 6 0 RESERVED RESERVED, Set = 0 5 0 RESERVED RESERVED, Set = 0 4 0 RESERVED RESERVED, Set = 0 3 0 2 0 CPU[T/C]2 CPU[T/C]2 PWRDWN Drive Mode 0 = Driven when PD asserted,1 = Hi-Z when PD asserted 1 0 CPU[T/C]1 CPU[T/C]1 PWRDWN Drive Mode 0 = Driven when PD asserted,1 = Hi-Z when PD asserted 0 0 CPU[T/C]0 CPU[T/C]0 PWRDWN Drive Mode 0 = Driven when PD asserted,1 = Hi-Z when PD asserted SRC[T/C][6:0],SATA[T/C] SRC[T/C], SATA[T/C]Stop Drive Mode 0 = Driven when SW PCI_STP# asserted,1 = Hi-Z when PCI_STP# asserted SRC[T/C][6:0],SATA[T/C] SRC[T/C], SATA[T/C] PWRDWN Drive Mode 0 = Driven when PD asserted,1 = Hi-Z when PD asserted Rev 1.0, November 20, 2006 Page 6 of 16 CY28412 Byte 6: Control Register 6 Bit @Pup Name Description 7 0 RESERVED 6 0 5 1 REF1 REF1 Output Drive Strength 0 = Low, 1 = High 4 1 REF0 REF0 Output Drive Strength 0 = Low, 1 = High 3 1 PCIF, SRC, PCI 2 Externally selected CPUT/C FS_C. Reflects the value of the FS_C pin sampled on power up 0 = FS_C was low during VTT_PWRGD# assertion 1 Externally selected CPUT/C FS_B. Reflects the value of the FS_B pin sampled on power up 0 = FS_B was low during VTT_PWRGD# assertion 0 Externally selected CPUT/C FS_A. Reflects the value of the FS_A pin sampled on power up 0 = FS_A was low during VTT_PWRGD# assertion RESERVED, Set = 0 Test Clock Mode Entry Control 1 = Hi-Z mode, 0 = Normal operation SW PCI_STP# Function 0=SW PCI_STP assert, 1= SW PCI_STP deassert When this bit is set to 0, all STOPPABLE PCI, PCIF and SRC outputs will be stopped in a synchronous manner with no short pulses. When this bit is set to 1, all STOPPED PCI, PCIF and SRC outputs will resume in a synchronous manner with no short pulses. Byte 7: Vendor ID Bit @Pup 7 0 Revision Code Bit 3 Name Revision Code Bit 3 Description 6 0 Revision Code Bit 2 Revision Code Bit 2 5 1 Revision Code Bit 1 Revision Code Bit 1 4 0 Revision Code Bit 0 Revision Code Bit 0 3 1 Vendor ID Bit 3 Vendor ID Bit 3 2 0 Vendor ID Bit 2 Vendor ID Bit 2 1 0 Vendor ID Bit 1 Vendor ID Bit 1 0 0 Vendor ID Bit 0 Vendor ID Bit 0 Crystal Recommendations Crystal Loading The CY28412 requires a Parallel Resonance Crystal. Substituting a series resonance crystal will cause the CY28412 to operate at the wrong frequency and violate the ppm specification. For most applications there is a 300-ppm frequency shift between series and parallel crystals due to incorrect loading. Crystal loading plays a critical role in achieving low ppm performance. To realize low ppm performance, the total capacitance the crystal will see must be considered to calculate the appropriate capacitive loading (CL). The following diagram shows a typical crystal configuration using the two trim capacitors. An important clarification for the following discussion is that the trim capacitors are in series with the crystal not parallel. It’s a common misconception that load capacitors are in parallel with the crystal and should be approximately equal to the load capacitance of the crystal. This is not true. Table 5. Crystal Recommendations Frequency (Fund) Cut Loading Load Cap Drive (max.) Shunt Cap (max.) Motional (max.) Tolerance (max.) Stability (max.) Aging (max.) 14.31818 MHz AT Parallel 0.1 mW 5 pF 0.016 pF 50 ppm 50 ppm 5 ppm Rev 1.0, November 20, 2006 20 pF Page 7 of 16 CY28412 Figure 1. Crystal Capacitive Clarification Calculating Load Capacitors PD (Power-down) Clarification In addition to the standard external trim capacitors, trace capacitance and pin capacitance must also be considered to correctly calculate crystal loading. As mentioned previously, the capacitance on each side of the crystal is in series with the crystal. This means the total capacitance on each side of the crystal must be twice the specified crystal load capacitance (CL). While the capacitance on each side of the crystal is in series with the crystal, trim capacitors (Ce1,Ce2) should be calculated to provide equal capacitive loading on both sides. The VTT_PWRGD# /PD pin is a dual function pin. During initial power-up, the pin functions as VTT_PWRGD#. Once VTT_PWRGD# has been sampled low by the clock chip, the pin assumes PD functionality. The PD pin is an asynchronous active high input used to shut off all clocks cleanly prior to shutting off power to the device. This signal is synchronized internal to the device prior to powering down the clock synthesizer. PD is also an asynchronous input for powering up the system. When PD is asserted high, all clocks are driven to a low value and held prior to turning off the VCOs and the crystal oscillator. As mentioned previously, the capacitance on each side of the crystal is in series with the crystal. This mean the total capacitance on each side of the crystal must be 2 times the specified load capacitance (CL). While the capacitance on each side of the crystal is in series with the crystal, trim capacitors (Ce1,Ce2) should be calculated to provide equal capacitance loading on both sides. Use the following formulas to calculate the trim capacitor values for Ce1 and Ce2. Load Capacitance (each side) Ce = 2 * CL – (Cs + Ci) Total Capacitance (as seen by the crystal) CLe = 1 ( Ce1 + Cs1 + Ci1 1 + 1 Ce2 + Cs2 + Ci2 ) CL ................................................... Crystal load capacitance CLe .........................................Actual loading seen by crystal using standard value trim capacitors PD (Power-down) – Assertion When PD is sampled high by two consecutive rising edges of CPUC, all single-ended outputs will be held low on their next high to low transition and differential clocks must be held high or Hi-Z (depending on the state of the control register drive mode bit) on the next diff clock# high to low transition. When the SMBus PD drive mode bit corresponding to the differential (CPU, SRC, and DOT) clock output of interest is programmed to ‘0’, the clock output must be held with “Diff clock” pin driven high at 2 x Iref, and “Diff clock#” tristate. If the control register PD drive mode bit corresponding to the output of interest is programmed to “1”, then both the “Diff clock” and the “Diff clock#” are Hi-Z. Note the example below shows CPUT = 133 MHz and PD drive mode = ‘1’ for all differential outputs. This diagram and description is applicable to valid CPU frequencies 100,133,166,200,266,333, and 400 MHz. In the event that PD mode is desired as the initial power-on state, PD must be asserted high in less than 10 Ps after asserting VTT_PWRGD#. Ce .....................................................External trim capacitors Cs ............................................. Stray capacitance (terraced) Ci .......................................................... Internal capacitance (lead frame, bond wires etc.) Rev 1.0, November 20, 2006 Page 8 of 16 CY28412 PD Deassertion The power-up latency is less than 1.8 ms. This is the time from the deassertion of the PD pin or the ramping of the power supply until the time that stable clocks are output from the clock chip. All differential outputs stopped in a tristate condition resulting from power down must be driven high in less than 300 Ps of PD deassertion to a voltage greater than 200 mV. After the clock chip’s internal PLL is powered up and locked, all outputs are enabled within a few clock cycles of each other. Clock Chip Ci2 Ci1 Pin 3 to 6p X2 X1 Cs1 Cs2 Trace 2.8pF XTAL Ce1 Ce2 Trim 33pF Figure 2. Crystal Loading Example PD CPUT, 133MHz CPUC, 133MHz SRCT 100MHz SRCC 100MHz USB, 48MHz DOT96T DOT96C PCI, 33 MHz REF Figure 3. Power-down Assertion Timing Waveform Rev 1.0, November 20, 2006 Page 9 of 16 CY28412 Below is an example showing the relationship of clocks coming up. Tstable <1.8ms PD CPUT, 133MHz CPUC, 133MHz SRCT 100MHz SRCC 100MHz USB, 48MHz DOT96T DOT96C PCI, 33MHz Tdrive_PWRDN# <300PS, >200mV REF Figure 4. Power-down Deassertion Timing Waveform FS_A, FS_B,FS_C VTT_PW RGD# PW RGD_VRM 0.2-0.3mS Delay VDD Clock Gen Clock State Clock Outputs Clock VCO State 0 W ait for VTT_PW RGD# State 1 Device is not affected, VTT_PW RGD# is ignored Sample Sels State 2 Off State 3 On On Off Figure 5. VTT_PWRGD# Timing Diagram S2 S1 D elay >0.25m S VTT_PW R G D# = Low S am ple Inputs straps VDD _A = 2.0V W ait for <1.8m s S0 P ow er O ff S3 VD D_A = off N orm al O peration Enable O utputs VTT_PW RG D # = toggle Figure 6. Clock Generator Power-up/Run State Diagram Rev 1.0, November 20, 2006 Page 10 of 16 CY28412 Absolute Maximum Conditions Parameter Description Condition Min. Max. Unit VDD Core Supply Voltage –0.5 4.6 V VDD_A Analog Supply Voltage –0.5 4.6 V VIN Input Voltage Relative to VSS –0.5 VDD + 0.5 VDC TS Temperature, Storage Non-functional –65 150 °C TA Temperature, Operating Ambient Functional 0 70 °C TJ Temperature, Junction Functional – 150 °C ØJC Dissipation, Junction to Case Mil-Spec 883E Method 1012.1 – 31.89 °C/W ØJA Dissipation, Junction to Ambient JEDEC (JESD 51) – 48.29 °C/W – V ESDHBM ESD Protection (Human Body Model) MIL-STD-883, Method 3015 UL-94 Flammability Rating At 1/8 in. MSL Moisture Sensitivity Level 2000 V–0 1 Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. DC Electrical Specifications Parameter Description 3.3V Operating Voltage VDD_A, VDD_REF, VDD_PCI, VDD_3V66, VDD_48, VDD_CPU Condition 3.3 ± 5% Min. Max. Unit 3.135 3.465 V VILI2C Input Low Voltage SDATA, SCLK – 1.0 V VIHI2C Input High Voltage SDATA, SCLK 2.2 – V VIL_FS FS_(A,B,C) Input Low Voltage VSS – 0.3 0.35 V VIH_FS FS_(A,B,C) Input High Voltage 0.7 VDD + 0.5 V VIL Input Low Voltage VSS – 0.5 0.8 V VIH Input High Voltage 2.0 VDD + 0.5 V 5 PA IIL Input Low Leakage Current except internal pull-up resistors, 0 < VIN < VDD IIH Input High Leakage Current except internal pull-down resistors, 0 < VIN < VDD VOL Output Low Voltage IOL = 1 mA VOH Output High Voltage IOH = –1 mA IOZ High-impedance Output Current CIN Input Pin Capacitance COUT LIN PA –5 – 0.4 V 2.4 – V –10 10 PA 2 5 pF Output Pin Capacitance 3 6 pF Pin Inductance – 7 nH VXIH Xin High Voltage 0.7VDD VDD V VXIL Xin Low Voltage 0 0.3VDD V IDD3.3V Dynamic Supply Current At max load and freq per Figure 8 – 500 mA IPD3.3V Power-down Supply Current PD asserted, Outputs driven – 75 mA IPD3.3V Power-down Supply Current PD asserted, Outputs Hi-Z – 2 mA Rev 1.0, November 20, 2006 Page 11 of 16 CY28412 AC Electrical Specifications Parameter Description Condition Min. Max. Unit The device will operate reliably with input duty cycles up to 30/70 but the REF clock duty cycle will not be within specification 47.5 52.5 % 69.841 71.0 ns Crystal TDC XIN Duty Cycle TPERIOD XIN Period T R / TF XIN Rise and Fall Times Measured between 0.3VDD and 0.7VDD – 10.0 ns TCCJ XIN Cycle to Cycle Jitter As an average over 1-Ps duration – 500 ps LACC Long-term Accuracy Over 150 ms – 300 ppm When XIN is driven from an external clock source CPU at 0.7V TDC CPUT and CPUC Duty Cycle Measured at crossing point VOX 45 55 % TPERIOD 100 MHz CPUT and CPUC Period Measured at crossing point VOX 9.9970 10.003 ns TPERIOD 133 MHz CPUT and CPUC Period Measured at crossing point VOX 7.4978 7.5023 ns TPERIOD 166 MHz CPUT and CPUC Period Measured at crossing point VOX 5.9982 6.0018 ns TPERIOD 200 MHz CPUT and CPUC Period Measured at crossing point VOX 4.9985 5.0015 ns TPERIOD 266 MHz CPUT and CPUC Period Measured at crossing point VOX 3.7489 3.7511 ns TPERIOD 333 MHz CPUT and CPUC Period Measured at crossing point VOX 2.9991 3.0009 ns TPERIOD 400 MHz CPUT and CPUC Period Measured at crossing point VOX 2.4993 2.5008 ns TPERIODSS 100 MHz CPUT and CPUC Period, SSC Measured at crossing point VOX 9.9970 10.0533 ns TPERIODSS 133 MHz CPUT and CPUC Period, SSC Measured at crossing point VOX 7.4978 7.5400 ns TPERIODSS 166 MHz CPUT and CPUC Period, SSC Measured at crossing point VOX 5.9982 6.0320 ns TPERIODSS 200 MHz CPUT and CPUC Period, SSC Measured at crossing point VOX 4.9985 5.0266 ns TPERIODSS 266 MHz CPUT and CPUC Period, SSC Measured at crossing point VOX 3.7489 3.7700 ns TPERIODSS 333 MHz CPUT and CPUC Period, SSC Measured at crossing point VOX 2.9991 3.0160 ns TPERIODSS 400 MHz CPUT and CPUC Period, SSC Measured at crossing point VOX 2.4993 2.5133 ns TSKEW Any CPUT/C to CPUT/C Clock Skew, SSC Measured at crossing point VOX – 100 ps TCCJ CPUT/C Cycle to Cycle Jitter Measured at crossing point VOX – 85 ps TCCJ2 CPU2_ITP Cycle to Cycle Jitter Measured at crossing point VOX – 125 ps TSKEW2 CPU2_ITP to CPU0 Clock Skew Measured at crossing point VOX – 150 ps T R / TF CPUT and CPUC Rise and Fall Times Measured from VOL = 0.175 to VOH = 0.525V 175 700 ps TRFM Rise/Fall Matching Determined as a fraction of 2*(TR – TF)/(TR + TF) – 20 % 'TR Rise Time Variation – 125 ps 'TF Fall Time Variation – 125 ps VHIGH Voltage High Math averages Figure 8 660 850 mv VLOW Voltage Low Math averages Figure 8 –150 – mv 250 550 mv – VHIGH + 0.3 V –0.3 – V – 0.2 V VOX Crossing Point Voltage at 0.7V Swing VOVS Maximum Overshoot Voltage VUDS Minimum Undershoot Voltage VRB Ring Back Voltage See Figure 8. Measure SE SRC TDC SRCT and SRCC Duty Cycle Measured at crossing point VOX 45 55 % TPERIOD 100 MHz SRCT and SRCC Period Measured at crossing point VOX 9.9970 10.003 ns TPERIODSS 100 MHz SRCT and SRCC Period, SSC Measured at crossing point VOX 9.9970 10.0533 ns Rev 1.0, November 20, 2006 Page 12 of 16 CY28412 AC Electrical Specifications (continued) Parameter Description Condition Min. Max. Unit – 125 ps – 300 ppm 175 700 ps TCCJ SRCT/C Cycle to Cycle Jitter Measured at crossing point VOX LACC SRCT/C Long Term Accuracy Measured at crossing point VOX T R / TF SRCT and SRCC Rise and Fall Times Measured from VOL = 0.175 to VOH = 0.525V TRFM Rise/Fall Matching Determined as a fraction of 2*(TR – TF)/(TR + TF) – 20 % 'TR Rise Time Variation – 125 ps 'TF Fall Time Variation – 125 ps VHIGH Voltage High Math averages Figure 8 660 850 mv VLOW Voltage Low Math averages Figure 8 –150 – mv VOX Crossing Point Voltage at 0.7V Swing 250 550 mV VOVS Maximum Overshoot Voltage – VHIGH + 0.3 V VUDS Minimum Undershoot Voltage –0.3 – V VRB Ring Back Voltage See Figure 8. Measure SE – 0.2 V TSKEW Any SRCT/C to SRCT/C Clock Skew Measured at Crossing point VOX – 250 ps PCI/PCIF TDC PCI Duty Cycle Measurement at 1.5V 45 55 % TPERIOD Spread Disabled PCIF/PCI Period Measurement at 1.5V 29.9910 30.0090 ns TPERIOD Spread Enabled PCIF/PCI Period Measurement at 1.5V 29.9910 30.1598 ns THIGH PCIF and PCI high time Measurement at 2.4V 12.0 – ns TLOW PCIF and PCI low time Measurement at 0.4V 12.0 – ns T R / TF PCIF and PCI Edge Rate Measured between 0.8V and 2.0V 0.5 2.0 V/ns TSKEW Any PCI clock to Any PCI clock Skew Measurement at 1.5V – 500 ps TCCJ PCIF and PCI Cycle to Cycle Jitter Measurement at 1.5V – 500 ps TDC DOT96T and DOT96C Duty Cycle Measured at crossing point VOX 45 55 % DOT TPERIOD DOT96T and DOT96C Period Measured at crossing point VOX 10.4135 10.4198 ns TCCJ DOT96T/C Cycle to Cycle Jitter Measured at crossing point VOX – 250 ps LACC DOT96T/C Long Term Accuracy Measured at crossing point VOX – 300 ppm T R / TF DOT96T and DOT96C Rise and Fall Times Measured from VOL = 0.175 to VOH = 0.525V 175 700 ps TRFM Rise/Fall Matching Determined as a fraction of 2*(TR – TF)/(TR + TF) – 20 % 'TR Rise Time Variation – 125 ps 'TF Fall Time Variation – 125 ps VHIGH Voltage High Math averages Figure 8 660 850 mv VLOW Voltage Low Math averages Figure 8 –150 – mv 250 550 mV – VHIGH + 0.3 V –0.3 – V – 0.2 V VOX Crossing Point Voltage at 0.7V Swing VOVS Maximum Overshoot Voltage VUDS Minimum Undershoot Voltage VRB Ring Back Voltage See Figure 8. Measure SE USB TDC Duty Cycle Measurement at 1.5V 45 55 % TPERIOD Period Measurement at 1.5V 20.8271 20.8396 ns THIGH USB high time Measurement at 2.4V 8.094 10.036 ns TLOW USB low time Measurement at 0.4V 7.694 9.836 ns Rev 1.0, November 20, 2006 Page 13 of 16 CY28412 AC Electrical Specifications (continued) Parameter Description Condition T R / TF USB Edge Rate Measured between 0.8V and 2.0V TCCJ USB Cycle to Cycle Jitter Measurement at 1.5V Min. Max. Unit 1.0 2.0 V/ns – 350 ps REF TDC REF Duty Cycle Measurement at 1.5V 45 55 % TPERIOD REF Period Measurement at 1.5V 69.8203 69.8622 ns T R / TF REF Edge Rate Measured between 0.8V and 2.0V 0.5 2.0 V/ns TCCJ REF Cycle to Cycle Jitter Measurement at 1.5V – 1000 ps – 1.8 ms ENABLE/DISABLE and SETUP TSTABLE Clock Stabilization from Power-up TSS Stopclock Set-up Time TSH Stopclock Hold Time 10.0 – ns 0 – ns Test and Measurement Set-up For PCI Single-ended Signals and Reference The following diagram shows the test load configurations for the single-ended PCI, USB, and REF output signals. PCI/ USB : : : : Measurement Point 4pF Measurement Point 4pF : : Measurement Point 4pF : : REF Measurement Point 4pF : : Measurement Point 4pF Figure 7. Single-ended Load Configuration Rev 1.0, November 20, 2006 Page 14 of 16 CY28412 For Differential CPU, SRC and DOT96 Output Signals The following diagram shows the test load configuration for the differential CPU and SRC outputs. CPUT SRCT D O T96T CPUC SRCC D O T96C IR E F M e a s u re m e n t P o in t : 2pF : : D if f e r e n t ia l M e a s u re m e n t P o in t : 2pF : : Figure 8. 0.7V Single-ended Load Configuration 3 .3 V s ig n a l s T DC - - 3 .3 V 2 .4 V 1 .5 V 0 .4 V 0V TR TF Figure 9. Single-ended Output Signals (for AC Parameters Measurement) Rev 1.0, November 20, 2006 Page 15 of 16 CY28412 Ordering Information Part Number Package Type Product Flow Standard CY28412OC 56-pin SSOP Commercial, 0° to 70°C CY28412OCT 56-pin SSOP – Tape and Reel Commercial, 0° to 70°C CY28412OXC 56-pin SSOP Commercial, 0° to 70°C CY28412OXCT 56-pin SSOP – Tape and Reel Commercial, 0° to 70°C Lead-free Package Drawing and Dimensions 56-lead Shrunk Small Outline Package O56 While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for the use of any circuitry or for the infringement of any patents or other rights of third parties which would result from each use. This product is intended for use in normal commercial applications and is not warranted nor is it intended for use in life support, critical medical instruments, or any other application requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursuant to additional processing by Spectra Linear Inc., and expressed written agreement by Spectra Linear Inc. Spectra Linear Inc. reserves the right to change any circuitry or specification without notice. Rev 1.0, November 20, 2006 Page 16 of 16