SpectraLinear CY28419ZC Clock synthesizer with differential src and cpu output Datasheet

CY28419
Clock Synthesizer with Differential SRC and CPU Outputs
Features
• Four differential CPU clock pairs
• One differential SRC clock
• CK409B-compliant
• I2C support with readback capabilities
• Supports Intel Pentium£ 4-type CPUs
• Selectable CPU frequencies
• Ideal Lexmark Spread Spectrum profile for maximum
electromagnetic interference (EMI) reduction
• 3.3V power supply
• 56-pin SSOP package
• Ten copies of PCI clocks
• Two copies 48 MHz clock
CPU
SRC
3V66
PCI
REF
48M
x4
x1
x5
x 10
x2
x2
• Five copies of 3V66 with one optional VCH
[1]
Block Diagram
XIN
XOUT
Pin Configuration
VDD_REF
REF0:1
XTAL
OSC
PLL 1
PLL Ref Freq
VDD_CPU
CPUT(0:3), CPUC(0:3)
Divider
Network
VDD_SRC
SRCT, SRCC
FS_(A:B)
VTT_PWRGD#
IREF
VDD_PCI
PCIF(0:2)
PLL2
2
PCI(0:6)
3V66_4/VCH
VDD_48MHz
DOT_48
PD#
USB_48
SDATA
SCLK
I2C
Logic
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
CY28419
VDD_3V66
3V66_(0:3)
REF_0
REF_1
VDD_REF
XIN
XOUT
VSS_REF
PCIF0
PCIF1
PCIF2
VDD_PCI
VSS_PCI
PCI0
PCI1
PCI2
PCI3
VDD_PCI
VSS_PCI
PCI4
PCI5
PCI6
PD#
3V66_0
3V66_1
VDD_3V66
VSS_3V66
3V66_2
3V66_3
SCLK
FS_B
VDD_A
VSS_A
VSS_IREF
IREF
FS_A
CPUT3
CPUC3
VDD_CPU
CPUT2
CPUC2
VSS_CPU
CPUT1
CPUC1
VDD_CPU
CPUT0
CPUC0
VSS_SRC
SRCT
SRCC
VDD_SRC
VTT_PWRGD#
VDD_48
VSS_48
DOT_48
USB_48
SDATA
3V66_4/VCH
SSOP-56
Note:
1. Signals marked with [*] and [**] have internal pull-up and pull-down resistors, respectively.
Rev 1.0, November 22, 2006
2200 Laurelwood Road, Santa Clara, CA 95054
Page 1 of 15
Tel:(408) 855-0555
Fax:(408) 855-0550
www.SpectraLinear.com
CY28419
Pin Description
Pin No.
Pin Name
Pin Type
O, SE
Pin Description
1,2
REF(0:1)
4
XIN
5
XOUT
O, SE
Crystal Connection. Connection for an external 14.318-MHz crystal output.
41,44,47,50
CPUT(0:3)
O, DIF
CPU Clock Output. Differential CPU clock outputs. See Table 1 for frequency configuration.
40,43,46,49
CPUC(0:3)
O, DIF
CPU Clock Output. Differential CPU clock outputs. See Table 1 for frequency configuration.
38, 37
SRCT, SRCC
O, DIF
Differential serial reference clock.
I
Reference Clock. 3.3V 14.318-Mz clock output.
Crystal Connection or External Reference Frequency Input. This pin has dual
functions. It can be used as an external 14.318-MHz crystal connection or as an
external reference frequency input.
22,23,26,27
3V66(3:0)
O, SE
66 MHz Clock Output. 3.3V 66-MHz clock from internal VCO.
29
3V66_4VCH
O, SE
48/66 MHz Clock Output. 3.3V selectable through SMBus to be 66 or 48 MHz.
7,8,9
PCIF(0:2)
O, SE
Free Running PCI Output. 33-MHz clocks divided down from 3V66.
12,13,14,15, PCI(0:6)
18,19,20
O, SE
PCI Clock Output. 33-MHz clocks divided down from 3V66.
31,
USB_48
O, SE
Fixed 48 MHz clock output.
32
DOT_48
O, SE
Fixed 48 MHz clock output.
51,56
FS_A, FS_B
I
3.3V LVTTL input for CPU frequency selection.
52
IREF
I
Current Reference. A precision resistor is attached to this pin which is connected to
the internal current reference.
21
PD#
I, PU
35
VTT_PWRGD#
30
SDATA
I
I/O
3.3V LVTTL input for power-down# active LOW.
3.3V LVTTL input is a level-sensitive strobe used to latch the FS0 input (active
LOW).
SMBus-compatible SDATA.
28
SCLK
I
SMBus-compatible SCLOCK.
53
VSS_IREF
GND
Ground for current reference.
55
VDD_A
PWR
3.3V power supply for PLL.
54
VSS_A
GND
Ground for PLL.
42,48
VDD_CPU
PWR
3.3V power supply for outputs.
45
VSS_CPU
GND
Ground for outputs.
36
VDD_SRC
PWR
3.3V power supply for outputs.
39
VSS_SRC
GND
Ground for outputs.
34
VDD_48
PWR
3.3V power supply for outputs.
33
VSS_48
GND
Ground for outputs.
10,16
VDD_PCI
PWR
3.3V power supply for outputs.
11,17
VSS_PCI
GND
Ground for outputs.
24
VDD_3V66
PWR
3.3V power supply for outputs.
25
VSS_3V66
GND
Ground for outputs.
3
VDD_REF
PWR
3.3V power supply for outputs.
6
VSS_REF
GND
Ground for outputs.
Rev 1.0, November 22, 2006
Page 2 of 15
CY28419
Frequency Select Pins (FS_A, FS_B)
Host clock frequency selection is achieved by applying the
appropriate logic levels to FS_A and FS_B inputs prior to
VTT_PWRGD# assertion (as seen by the clock synthesizer).
Upon VTT_PWRGD# being sampled low by the clock chip
(indicating processor VTT voltage is stable), the clock chip
samples the FS_A and FS_B input values. For all logic levels
of FS_A and FS_B except MID, VTT_PWRGD# employs a
one-shot functionality in that once a valid low on
VTT_PWRGD# has been sampled low, all further
VTT_PWRGD#, FS_A and FS_B transitions will be ignored. In
the case where FS_B is at mid level when VTT_PWRGD# is
sampled low, the clock chip will assume “Test Clock Mode”.
Once “Test Clock Mode” has been invoked, all further FS_B
transitions will be ignored and FS_A will asynchronously
select between the Hi-Z and REF/N mode. Exiting test mode
is accomplished by cycling power with FS_B in a high or low
state.
Table 1. Frequency Select Table (FS_A FS_B)
FS_A
FS_B
CPU
SRC
3V66
PCIF/PCI
REF0
REF1
USB/DOT
0
0
100 MHz
100/200 MHz
66 MHz
33 MHz
14.3 MHz
14.31 MHz
48 MHz
0
MID
REF/N
REF/N
REF/N
REF/N
REF/N
REF/N
REF/N
0
1
200 MHz
100/200 MHz
66 MHz
33 MHz
14.3 MHz
14.31 MHz
48 MHz
1
0
133 MHz
100/200 MHz
66 MHz
33 MHz
14.3 MHz
14.31 MHz
48 MHz
1
1
166 MHz
100/200 MHz
66 MHz
33 MHz
14.3 MHz
14.31 MHz
48 MHz
1
MID
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Table 2. Frequency Select Table (FS_A FS_B) SMBus Bit 5 of Byte 6 = 1
FS_A
FS_B
CPU
SRC
3V66
PCIF/PCI
REF0
REF1
USB/DOT
0
0
200 MHz
100/200 MHz
66 MHz
33 MHz
14.3 MHz
14.31 MHz
48 MHz
0
1
400 MHz
100/200 MHz
66 MHz
33 MHz
14.3 MHz
14.31 MHz
48 MHz
1
0
266 MHz
100/200 MHz
66 MHz
33 MHz
14.3 MHz
14.31 MHz
48 MHz
1
1
333 MHz
100/200 MHz
66 MHz
33 MHz
14.3 MHz
14.31 MHz
48 MHz
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers, can be individually enabled or disabled.
The registers associated with the Serial Data Interface
initializes to their default setting upon power-up, and therefore
use of this interface is optional. Clock device register changes
are normally made upon system initialization, if any are
required. The interface cannot be used during system
operation for power management functions.
first) with the ability to stop after any complete byte has been
transferred. For byte write and byte read operations, the system controller can access individually indexed bytes. The offset of the indexed byte is encoded in the command code, as
described in Table 3.
The block write and block read protocol is outlined in Table 4
while Table 5 outlines the corresponding byte write and byte
read protocol. The slave receiver address is 11010010 (D2h).
Table 3. Command Code Definition
Bit
Description
7
0 = Block read or block write operation, 1 = Byte
read or byte write operation
(6:0)
Byte offset for byte read or byte write operation.
For block read or block write operations, these bits
should be '0000000'
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit
Table 4. Block Read and Block Write Protocol
Block Write Protocol
Bit
1
2:8
Description
Start
Slave address – 7 bits
Block Read Protocol
Bit
1
2:8
Description
Start
Slave address – 7 bits
9
Write = 0
9
Write = 0
10
Acknowledge from slave
10
Acknowledge from slave
11:18
Command Code – 8 bits
'00000000' stands for block operation
Rev 1.0, November 22, 2006
11:18
Command Code – 8 bits
'00000000' stands for block operation
Page 3 of 15
CY28419
Table 4. Block Read and Block Write Protocol (continued)
Block Write Protocol
19
20:27
28
29:36
37
38:45
Block Read Protocol
Acknowledge from slave
19
Acknowledge from slave
Byte Count – 8 bits
20
Repeat start
Acknowledge from slave
21:27
Slave address – 7 bits
Data byte 1 – 8 bits
28
Read = 1
Acknowledge from slave
29
Acknowledge from slave
Data byte 2 – 8 bits
30:37
38
Byte count from slave – 8 bits
46
Acknowledge from slave
....
......................
....
Data Byte (N–1) –8 bits
47
....
Acknowledge from slave
48:55
....
Data Byte N –8 bits
56
Acknowledge from master
....
Acknowledge from slave
....
Data byte N from slave – 8 bits
....
Stop
....
Acknowledge from master
....
Stop
39:46
Acknowledge from master
Data byte from slave – 8 bits
Acknowledge from master
Data byte from slave – 8 bits
Table 5. Byte Read and Byte Write Protocol
Byte Write Protocol
Bit
1
2:8
Description
Start
Slave address – 7 bits
Byte Read Protocol
Bit
1
2:8
Description
Start
Slave address – 7 bits
9
Write = 0
9
Write = 0
10
Acknowledge from slave
10
Acknowledge from slave
11:18
19
20:27
Command Code – 8 bits
'100xxxxx' stands for byte operation, bits[6:0] of the
command code represents the offset of the byte to
be accessed
11:18
Command Code – 8 bits
'100xxxxx' stands for byte operation, bits[6:0] of
the command code represents the offset of the
byte to be accessed
Acknowledge from slave
19
Acknowledge from slave
Data byte from master – 8 bits
20
Repeat start
28
Acknowledge from slave
29
Stop
21:27
Read = 1
29
Acknowledge from slave
30:37
Rev 1.0, November 22, 2006
Slave address – 7 bits
28
Data byte from slave – 8 bits
38
Acknowledge from master
39
Stop
Page 4 of 15
CY28419
Byte 0: Control Register 0
Bit
@Pup
7
0
Reserved
Name
Reserved
Description
6
1
Reserved
Reserved
5
0
Reserved
Reserved
4
0
Reserved
Reserved
3
1
Reserved
Reserved
2
1
Reserved
Reserved
1
Externally
Selected
FS_B
FS_B reflects the value of the FS_B pin sampled on power-up.
0 = FS_B low at power-up
0
Externally
Selected
FS_A
FS_A reflects the value of the FS_A pin sampled on power-up.
0 = FS_A low at power-up
Byte 1: Control Register 1
Bit
@Pup
7
0
SRCT, SRCC
Name
Allow control of SRCT/C with assertion of PCI_STP#
0 = Free Running, 1 = Stopped with PCI_STP#
Description
6
1
SRCT, SRCC
SRCT/C Output Enable
0 = Disabled (three-state), 1 = Enabled
5
1
Reserved
Reserved
4
1
Reserved
Reserved
3
1
Reserved
Reserved
2
1
CPUT2, CPUC2
CPUT/C2 Output Enable
0 = Disabled (three-state), 1 = Enabled
1
1
CPUT1, CPUC1
CPUT/C1 Output Enable,
0 = Disabled (three-state), 1 = Enabled
0
1
CPUT0, CPUC0
CPUT/C0 Output Enable
0 = Disabled (three-state), 1 = Enabled
Byte 2: Control Register 2
Bit
@Pup
7
0
SRCT, SRCC
Name
SRCT/C Pwrdwn drive mode
0 = Driven in power-down, 1 = Three-state in power-down
6
0
SRCT, SRCC
SRCT/C Stop drive mode
0 = Driven in PCI_STP, 1 = Three-state in power-down
5
0
CPUT2, CPUC2
CPUT/C2 Pwrdwn drive mode
0 = Driven in power-down, 1 = Three-state in power-down
4
0
CPUT1, CPUC1
CPUT/C1 Pwrdwn drive mode
0 = Driven in power-down, 1 = Three-state in power-down
3
0
CPUT0, CPUC0
CPUT/C0 Pwrdwn drive mode
0 = Driven in power-down, 1 = Three-state in power-down
2
0
Reserved
Reserved
1
0
Reserved
Reserved
0
0
Reserved
Reserved
Rev 1.0, November 22, 2006
Description
Page 5 of 15
CY28419
Byte 3: Control Register 3
Bit @Pup
Name
7
1
All PCI and SRC Clock outputs
except PCIF and SRC clocks
set to free-running
6
1
PCI6
5
1
PCI5
4
1
PCI4
3
1
PCI3
2
1
PCI2
1
1
PCI1
0
1
PCI0
Description
PCI_STP Control. 0 = SW PCI_STP not enabled and only the PCI_STP# pin will
stop the PCI stop enabled outputs, 1 = the PCI_STP function is enabled and the
stop enabled outputs will be stopped in a synchronous manner with no short pulses.
PCI6 Output Enable
0 = Disabled, 1 = Enabled
PCI5 Output Enable
0 = Disabled, 1 = Enabled
PCI4 Output Enable
0 = Disabled, 1 = Enabled
PCI3 Output Enable
0 = Disabled, 1 = Enabled
PCI2 Output Enable
0 = Disabled, 1 = Enabled
PCI1 Output Enable
0 = Disabled, 1 = Enabled
PCI0 Output Enable
0 = Disabled, 1 = Enabled
Byte 4: Control Register 4
Bit
7
@Pup
0
Name
USB_ 48MHz
6
1
USB_ 48MHz
5
0
PCIF2
4
0
PCIF1
3
0
PCIF0
2
1
PCIF2
1
1
PCIF1
0
1
PCIF0
Description
USB_48 Drive Strength
0 = High drive strength, 1 = Normal drive strength
USB_48 Output Enable
0 = Disabled, 1 = Enabled
Allow control of PCIF2 with assertion of PCI_STP#
0 = Free Running, 1 = Stopped with PCI_STP#
Allow control of PCIF1 with assertion of PCI_STP#
0 = Free Running, 1 = Stopped with PCI_STP#
Allow control of PCIF0 with assertion of PCI_STP#
0 = Free Running, 1 = Stopped with PCI_STP#
PCIF2 Output Enable
0 = Disabled, 1 = Enabled
PCIF1 Output Enable
0 = Disabled, 1 = Enabled
PCIF0 Output Enable
0 = Disabled, 1 = Enabled
Byte 5: Control Register 5
Bit
@Pup
7
1
DOT_48
Name
DOT_48 Output Enable
0 = Disabled, 1 = Enabled
6
1
CPUT3, CPUC3
0 = three-state, 1 = Enabled
5
0
3V66_4/VCH
VCH Select 66 MHz/48 MHz
0 = 3V66 mode, 1 = VCH (48MHz) mode
4
1
3V66_4/VCH
3V66_4/VCH Output Enable
0 = Disabled, 1 = Enabled
3
1
3V66_3
3V66_3 Output Enable
0 = Disabled, 1 = Enabled
2
1
3V66_2
3V66_2 Output Enable
0 = Disabled, 1 = Enabled
1
1
3V66_1
3V66_1 Output Enable
0 = Disabled, 1 = Enabled
0
1
3V66_0
3V66_0 Output Enable
0 = Disabled, 1 = Enabled
Rev 1.0, November 22, 2006
Description
Page 6 of 15
CY28419
Byte 6: Control Register 6
Bit
@Pup
7
0
Name
Description
Test Clock Mode
0= Disabled, 1 = Enabled
REF
PCIF
PCI
3V66
USB_48
DOT_48
CPUT/C
SRCT/C
6
0
5
0
CPUC0, CPUT0
CPUC1, CPUT1
CPUC2, CPUT2
CPUC3, CPUT3
Reserved, Set = 0
FS_A & FS_B Operation
0 = Normal, 1 = Test mode
4
0
SRCT, SRCC
SRC Frequency Select
0 = 100 MHz, 1 = 200 MHz
3
0
2
0
PCIF
PCI
3V66
SRC(T/C)
CPUT/ C
Spread Spectrum Mode
0 = Spread Off, 1 = Spread On
1
1
REF_1
REF_1 Output Enable
0 = Disabled, 1 = Enabled
0
1
REF_0
REF_0 Output Enable
0 = Disabled, 1 = Enabled
Reserved, Set = 0
Byte 7: Vendor ID
Bit
@Pup
Name
Description
7
0
Revision Code Bit 3
Revision Code Bit 3
6
0
Revision Code Bit 2
Revision Code Bit 2
5
0
Revision Code Bit 1
Revision Code Bit 1
4
0
Revision Code Bit 0
Revision Code Bit 0
3
1
Vendor ID Bit 3
Vendor ID Bit 3
2
0
Vendor ID Bit 2
Vendor ID Bit 2
1
0
Vendor ID Bit 1
Vendor ID Bit 1
0
0
Vendor ID Bit 0
Vendor ID Bit 0
Crystal Recommendations
The CY28419 requires a Parallel Resonance Crystal.
Substituting a series resonance crystal will cause the
CY28419 to operate at the wrong frequency and violate the
ppm specification. For most applications there is a 300-ppm
frequency shift between series and parallel crystals due to
incorrect loading.
Table 6. Crystal Recommendations
Frequency
(Fund)
Cut
Loading Load Cap
Drive
(max.)
Shunt Cap
(max.)
Motional
(max.)
Tolerance
(max.)
Stability
(max.)
Aging
(max.)
14.31818 MHz
AT
Parallel
0.1 mW
5 pF
0.016 pF
50 ppm
50 ppm
5 ppm
Rev 1.0, November 22, 2006
20 pF
Page 7 of 15
CY28419
Crystal Loading
Crystal loading plays a critical role in achieving low ppm performance. To realize low-ppm performance, the total capacitance
the crystal will see must be considered to calculate the appropriate capacitive loading (CL).
The following diagram shows a typical crystal configuration
using the two trim capacitors. An important clarification for the
following discussion is that the trim capacitors are in series
with the crystal not parallel. It’s a common misconception that
load capacitors are in parallel with the crystal and should be
approximately equal to the load capacitance of the crystal.
This is not true.
As mentioned previously, the capacitance on each side of the
crystal is in series with the crystal. This mean the total capacitance on each side of the crystal must be twice the specified
load capacitance(CL). While the capacitance on each side of
the crystal is in series with the crystal, trim capacitors(Ce1,Ce2) should be calculated to provide equal capacitative loading on both sides.
Use the following formulas to calculate the trim capacitor
values fro Ce1 and Ce2.
Load Capacitance (each side)
Ce = 2 * CL – (Cs + Ci)
Total Capacitance (as seen by the crystal)
CLe
=
1
1
( Ce1 + Cs1
+ Ci1 +
1
Ce2 + Cs2 + Ci2
)
CL....................................................Crystal load capacitance
CLe......................................... Actual loading seen by crystal
..................................... using standard value trim capacitors
Ce..................................................... External trim capacitors
Figure 1. Crystal Capacitive Clarification
Calculating Load Capacitors
In addition to the standard external trim capacitors, trace
capacitance and pin capacitance must also be considered to
correctly calculate crystal loading. As mentioned previously,
the capacitance on each side of the crystal is in series with the
crystal. This means the total capacitance on each side of the
crystal must be twice the specified crystal load capacitance
(CL). While the capacitance on each side of the crystal is in
series with the crystal, trim capacitors (Ce1,Ce2) should be
calculated to provide equal capacitive loading on both sides.
Clock Chip
(CY28419)
Ci2
Ci1
Pin
3 to 6p
X2
X1
Cs1
Cs ........................................... Stray capacitance (trace, etc.)
Ci ...........................................................Internal capacitance
................................................ (lead frame, bond wires, etc.)
PD# (Power-down) Clarification
The PD# pin is used to shut off all clocks and PLLs without
having to remove power from the device. All clocks are shut
down in a synchronous manner so has not to cause glitches
while transitioning to the power-down state.
PD#–Assertion
When PD# is sampled low by two consecutive rising edges of
the CPUC clock then all clock outputs (except CPU) clocks
must be held low on their next high to low transition. CPU
clocks must be held with CPUT clock pin driven high with a
value of 2x Iref and CPUC undriven as the default condition.
There exists an I2C bit that allows for the CPUT/C outputs to
be three-stated during power-down. Due to the state of internal
logic, stopping and holding the REF clock outputs in the LOW
state may require more than one clock cycle to complete.
Cs2
Trace
2.8pF
XTAL
Ce1
Ce2
Trim
33pF
Figure 2. Crystal Loading Example
Rev 1.0, November 22, 2006
Page 8 of 15
CY28419
PD#
CPUT, 133MHz
CPUC, 133MHz
SRCT 100MHz
SRCC 100MHz
3V66, 66MHz
USB, 48MHz
PCI, 33MHz
REF
Figure 3. Power-down Assertion Timing Waveforms
PD# Deassertion
The power-up latency between PD# rising to a valid logic ‘1’
level and the starting of all clocks is less than 1.8 ms. The
CPUT/C outputs must be driven to greater than 200 mV is less
than 300 us.
Tstable
<1.8ms
PD#
CPUT, 133MHz
CPUC, 133MHz
SRCT 100MHz
SRCC 100MHz
3V66, 66MHz
USB, 48MHz
PCI, 33MHz
REF
Tdrive_PWRDN#
<300PS, >200mV
Figure 4. Power-down Deassertion Timing Waveforms
Rev 1.0, November 22, 2006
Page 9 of 15
CY28419
FS_A, FS_B
VTT_PWRGD#
PWRGD_VRM
0.2-0.3mS
Delay
VDD Clock Gen
Clock State
Clock Outputs
Clock VCO
State 0
Wait for
VTT_PWRGD#
State 1
Device is not affected,
VTT_PWRGD# is ignored
Sample Sels
State 2
Off
State 3
On
On
Off
Figure 5. VTTPWRGD Timing Diagram
S2
S1
Delay
>0.25mS
VTT_PWRGD# = Low
Sample
Inputs straps
VDD_A = 2.0V
Wait for <1.8ms
S0
Power Off
S3
VDD_A = off
Normal
Operation
Enable Outputs
VTT_PWRGD# = toggle
Figure 6. Clock Generator Power-up/Run State Diagram
Rev 1.0, November 22, 2006
Page 10 of 15
CY28419
Absolute Maximum Conditions
Parameter
Description
Condition
Min.
Max.
Unit
VDD
Core Supply Voltage
–0.5
4.6
V
VDD_A
Analog Supply Voltage
–0.5
4.6
V
VIN
Input Voltage
Relative to V SS
–0.5
VDD + 0.5
VDC
TS
Temperature, Storage
Non-functional
–65
+150
°C
TA
Temperature, Operating Ambient
Functional
0
70
°C
TJ
Temperature, Junction
Functional
–
150
°C
ØJC
Dissipation, Junction to Case
Mil-Spec 883E Method 1012.1
–
15
°C/W
ØJA
Dissipation, Junction to Ambient
JEDEC (JESD 51)
–
45
°C/W
ESDHBM
ESD Protection (Human Body Model)
MIL-STD-883, Method 3015
–
V
UL-94
Flammability Rating
At 1/8 in.
MSL
Moisture Sensitivity Level
2000
V–0
1
Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing
is NOT required.
DC Electrical Specifications
Parameter
Description
Conditions
VDD, VDD_A 3.3 Operating Voltage
3.3V ± 5%
VILI2C
Input Low Voltage
SDATA, SCLK
VIHI2C
Input High Voltage
SDATA, SCLK
VIL
Input Low Voltage
VIH
Input High Voltage
IIL
Input Leakage Current
IILI2C
VOL
Min.
Max.
Unit
3.135
3.465
V
–
1.0
V
2.2
–
V
VSS – 0.5
0.8
V
2.0
VDD + 0.5
V
except Pull-ups or Pull-downs 0 < VIN < VDD
–5
5
PA
Input High Voltage
SDATA, SCLK
2.2
–
V
Output Low Voltage
IOL = 1 mA
–
0.4
V
IOH = –1 mA
VOH
Output High Voltage
IOZ
High-impedance Output Current
CIN
Input Pin Capacitance
2
5
pF
COUT
Output Pin Capacitance
3
6
pF
LIN
Pin Inductance
VXIH
Xin High Voltage
VXIL
Xin Low Voltage
IDD
Dynamic Supply Current
At 200 MHz and all outputs loaded per Table 9
and Figure 7
IPD
Power-down Supply Current
PD# asserted, Outputs Three-stated
2.4
–
V
–10
10
PA
–
7
nH
0.7VDD
VDD
V
0
0.3VDD
V
–
280
mA
–
1
mA
Conditions
Min.
Max.
Unit
The device will operate reliably with input duty
cycles up to 30/70 but the REF clock duty cycle
will not be within specification
47.5
52.5
%
AC Electrical Specifications
Parameter
Description
Crystal
TDC
XIN Duty Cycle
TPERIOD
XIN Period
When XIN is driven from an external clock source 69.841
71.0
ns
T R / TF
XIN Rise and Fall Times
Measured between 0.3VDD and 0.7VDD
–
10.0
ns
TCCJ
XIN Cycle-to-Cycle Jitter
As an average over 1-Ps duration
–
500
ps
LACC
Long-term Accuracy
Over 150 ms
–
300
ppm
Rev 1.0, November 22, 2006
Page 11 of 15
CY28419
AC Electrical Specifications (continued)
Parameter
Description
CPU at 0.7V
TDC
CPUT and CPUC Duty Cycle
Conditions
Measured at crossing point VOX
Min.
Max.
Unit
45
55
%
TPERIOD
100-MHz CPUT and CPUC Period Measured at crossing point VOX
9.9970
10.003
ns
TPERIOD
133-MHz CPUT and CPUC Period Measured at crossing point VOX
7.4978
7.5023
ns
TPERIOD
166-MHz CPUT and CPUC Period Measured at crossing point VOX
5.9982
6.0018
ns
TPERIOD
200-MHz CPUT and CPUC Period Measured at crossing point VOX
4.9985
5.0015
ns
TSKEW
Any CPU to CPU Clock Skew
Measured at crossing point VOX
–
100
ps
TCCJ
CPU Cycle-to-Cycle Jitter
Measured at crossing point VOX
–
125
ps
175
700
ps
–
20
%
TR/TF
CPUT/CPUC Rise and Fall Times
Measured from VOL = 0.175 to VOH = 0.525V
TRFM
Rise/Fall Matching
Determined as a fraction of 2*(TR–TF)/ (TR+TF)
'TR
Rise Time Variation
–
125
ps
'TF
Fall Time Variation
–
125
ps
VHIGH
Voltage High
Math average, see Figure 7
660
850
mv
VLOW
Voltage Low
Math average, see Figure 7
–150
–
mv
VOX
Crossing Point voltage at 0.7V
Swing
250
550
mv
VOVS
Maximum Overshoot Voltage
–
VHIGH + 0.3
V
VUDS
Minimum Undershoot Voltage
–0.3
–
V
VRB
Ring Back Voltage
See Figure 7. Measure SE
–
0.2
V
SRC
TDC
SRCT and SRCC Duty Cycle
Measured at crossing point VOX
45
55
%
TPERIOD
100-MHz SRCT and SRCC Period Measured at crossing point VOX
9.9970
10.003
ns
TPERIOD
200-MHz SRCT and SRCC Period Measured at crossing point VOX
4.9985
5.0015
ns
TCCJ
SRC Cycle-to-Cycle Jitter
Measured at crossing point VOX
–
125
ps
LACC
SRCT/C Long-term Accuracy
Measured at crossing point VOX
–
300
ppm
T R / TF
SRCT/SRCT\C Rise and Fall Times Measured from VOL = 0.175 to VOH = 0.525V
175
700
ps
TRFM
Rise/Fall Matching
–
20
%
'TR
Rise Time Variation
–
125
ps
'TF
Fall Time Variation
–
125
ps
Determined as a fraction of 2*(TR–TF)/ (TR+TF)
VHIGH
Voltage High
Math average, see Figure 7
660
850
mv
VLOW
Voltage Low
Math average, see Figure 7
–150
–
mv
VOX
Crossing Point Voltage at 0.7V
Swing
250
550
mV
VOVS
Maximum Overshoot Voltage
–
VHIGH+0.3
V
VUDS
Minimum Undershoot Voltage
–0.3
–
V
VRB
Ring Back Voltage
See Figure 7. Measure SE
–
0.2
V
3V66
TDC
3V66 Duty Cycle
Measurement at 1.5V
45
55
%
TPERIOD
Spread Disabled 3V66 Period
Measurement at 1.5V
14.9955
15.0045
ns
TPERIOD
Spread Enabled 3V66 Period
Measurement at 1.5V
14.9955
15.0799
ns
THIGH
3V66 High Time
Measurement at 2.0V
4.9500
–
ns
TLOW
3V66 Low Time
Measurement at 0.8V
4.5500
–
ns
T R / TF
3V66 Rise and Fall Times
Measured between 0.8V and 2.0V
0.5
2.0
ns
TSKEW
Any 3V66 to Any 3V66 Clock Skew Measurement at 1.5V
–
250
ps
TCCJ
3V66 Cycle-to-Cycle Jitter
–
250
ps
Rev 1.0, November 22, 2006
Measurement at 1.5V
Page 12 of 15
CY28419
AC Electrical Specifications (continued)
Parameter
Description
Conditions
PCI / PCIF
TDC
PCIF and PCI Duty Cycle
Measurement at 1.5V
Min.
Max.
Unit
45
55
%
TPERIOD
Spread Disabled PCIF/PCI Period Measurement at 1.5V
29.9910
30.0009
ns
TPERIOD
Spread Enabled PCIF/PCI Period
Measurement at 1.5V
29.9910
30.1598
ns
THIGH
PCIF and PCI High Time
Measurement at 2.0V
12.0
–
nS
TLOW
PCIF and PCI Low Time
Measurement at 0.8V
12.0
–
nS
T R / TF
PCIF and PCI rise and fall times
Measured between 0.8V and 2.0V
0.5
2.0
nS
TSKEW
Any PCI Clock to Any PCI Clock
Skew
Measurement at 1.5V
–
500
pS
TCCJ
PCIF and PCI Cycle-to-Cycle Jitter Measurement at 1.5V
–
250
ps
DOT
TDC
DOT Duty Cycle
Measurement at 1.5V
45
55
%
TPERIOD
DOT Period
Measurement at 1.5V
20.8257
20.8340
ns
THIGH
DOT High Time
Measurement at 2.0V
8.994
10.486
nS
TLOW
DOT Low Time
Measurement at 0.8V
8.794
10.386
nS
T R / TF
Rise and Fall Times
Measured between 0.8V and 2.0V
0.5
1.0
ns
TLTJ
Long-term Jitter
10-Ps period
–
2.0
ns
USB
TDC
USB Duty Cycle
Measurement at 1.5V
45
55
%
TPERIOD
USB Period
Measurement at 1.5V
20.8257
20.8340
ns
THIGH
USB High Time
Measurement at 2.0V
8.094
10.036
nS
TLOW
USB Low Time
Measurement at 0.8V
7.694
9.836
nS
T R / TF
Rise and Fall Times
Measured between 0.8V and 2.0V
1.0
2.0
ns
TLTJ
Long-term Jitter
125-Ps period
–
6.0
ns
REF
TDC
REF Duty Cycle
Measurement at 1.5V
45
55
%
TPERIOD
REF Period
Measurement at 1.5V
69.827
69.855
ns
T R / TF
REF Rise and Fall Times
Measured between 0.8V and 2.0V
1.0
4.0
V/ns
TCCJ
REF Cycle-to-Cycle Jitter
Measurement at 1.5V
–
1000
ps
ENABLE/DISABLE and SET-UP
TSTABLE
Clock Stabilization from Power-up
TSS
Stopclock Set-up Time
TSH
Stopclock Hold Time
Table 7. Group Timing Relationship and Tolerances
Offset
–
1.8
ms
10.0
–
ns
0
–
ns
Table 9. Maximum Lumped Capacitive Output Loads
Clock
Max Load
Unit
Group
Conditions
Min.
Max.
PCI Clocks
30
pF
3V66 to PCI
3V66 Leads PCI
1.5 ns
3.5 ns
3V66 Clocks
30
pF
Table 8. USB to DOT Phase Offset
Parameter
Typical
Value
Tolerance
DOT Skew
0°
0.0ns
1000 ps
USB Skew
180°
0.0ns
1000 ps
VCH SKew
0°
0.0ns
1000 ps
Rev 1.0, November 22, 2006
USB Clock
20
pF
DOT Clock
10
pF
REF Clock
30
pF
Page 13 of 15
CY28419
Test and Measurement Set-up
For Differential CPU and SRC Output Signals
The following diagram shows lumped test load configurations
for the differential Host Clock Outputs.
M e a s u re m e n t
P o in t
TPCB
:
CPUT
:
M e a s u re m e n t
P o in t
TPCB
:
CPUC
2pF
:
IR E F
2pF
:
Figure 7. 0.7V Load Configuration
O u tp u t u n d e r T e s t
P ro b e
Load Cap
3 .3 V s ig n a ls
tD C
-
-
3 .3 V
2 .0 V
1 .5 V
0 .8 V
0V
Tr
Tf
Figure 8. Lumped Load For Single-ended Output Signals (for AC Parameters Measurement)
Table 10.CPU Clock Current Select Function
Board Target Trace/Term Z
Reference R, Iref – VDD (3*Rr)
Output Current
Voh @ Z
50 Ohms
RREF = 475 1%, IREF = 2.32 mA
Ioh = 6*Iref
0.7V @ 50
Ordering Information
Part Number
Package Type
Product Flow
CY28419OC
56-pin Shrunk Small Outline package (SSOP)
Commercial, 0q to 70qC
CY28419OCT
56-pin Shrunk Small Outline package (SSOP) – Tape and Reel
Commercial, 0q to 70qC
CY28419ZC
56-pin Thin Shrunk Small Outline package (TSSOP)
Commercial, 0q to 70qC
CY28419ZCT
56-pin Thin Shrunk Small Outline package (TSSOP) – Tape and Reel Commercial, 0q to 70qC
Rev 1.0, November 22, 2006
Page 14 of 15
CY28419
Package Drawing and Dimensions
56-Lead Shrunk Small Outline Package O56
56-Lead Thin Shrunk Small Outline Package, Type II (6 mm x 14 mm) Z56
While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for the use of any circuitry or for the infringement of any patents or other rights of third parties which would result from each use. This product is intended for use in
normal commercial applications and is not warranted nor is it intended for use in life support, critical medical instruments, or any other application requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursuant to additional
processing by Spectra Linear Inc., and expressed written agreement by Spectra Linear Inc. Spectra Linear Inc. reserves the right to change any
circuitry or specification without notice.
Rev 1.0, November 22, 2006
Page 15 of 15
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