CY2SSTU32866 1.8V, 25-bit (1:1) or 14-bit (1:2) JEDEC-Compliant Data Register with Parity Features CSR# inputs are HIGH. If either DCS# or CSR# input is LOW, the Qn outputs will function normally. The RESET# input has priority over the DCS# and CSR# control and will force the outputs LOW. If the DCS#-control functionality is not desired, the CSR# input can be hardwired to ground, in which case the set-up time requirement for DCS# would be the same as for the other D data inputs. • Operating frequency: DC to 500 MHz • Supports DDRII SDRAM • Two operations modes: 25 bit (1:1) and 14 bit (1:2) • 1.8V operation • Fully JEDEC-compliant (JESD 82-10) • 96-ball FBGA Functional Description All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8-V CMOS drivers that have been optimized to drive the DDR-II DIMM load. The CY2SSTU32866 operates from a differential clock (CK and CK#). Data are registered at the crossing of CK going high, and CK# going LOW. The C0 input controls the pinout configuration of the 1:2 pinout from A configuration (when LOW) to B configuration (when HIGH). The C1 input controls the pinout configuration from 25-bit 1:1 (when LOW) to 14-bit 1:2 (when HIGH). The device monitors both DCS# and CSR# inputs and will gate the Qn outputs from changing states when both DCS# and The device supports low-power standby operation. When the reset input (RESET#) is LOW, the differential input receivers are disabled, and undriven (floating) data, clock, and reference voltage (VREF) inputs are allowed. In addition, when RESET# is LOW, all registers are reset and all outputs are forced LOW. The LVCMOS RESET# and Cn inputs must always be held at a valid logic HIGH or LOW level. To ensure defined outputs from the register before a stable clock has been supplied, RESET# must be held in the LOW state during power-up. In the DDR-II RDIMM application, RESET# is specified to be completely asynchronous with respect to CK and CK#. Therefore, no timing relationship can be guaranteed between the two. When entering reset, the register will be cleared and the outputs will be driven low quickly, relative to the time to disable the differential input receivers. However, when coming out of reset, the register will become active quickly, relative to the time to enable the differential input receivers. Pin Configuration A B C D E F G H J K L M N P R T 1 DCKE D2 D3 DODT D5 D6 PAR_IN CK CK# D8 D9 D10 D11 D12 D13 D14 1 2 PPO D15 D16 QERR# D17 D18 RST# DCS# CSR# D19 D20 D21 D22 D23 D24 D25 2 3 VREF GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD VREF 3 4 VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD VDD 4 5 QCKE Q2 Q3 QODT Q5 Q6 C1 QCS# ZOH Q8 Q9 Q10 Q11 Q12 Q13 Q14 5 6 NC Q15 Q16 NC Q17 Q18 C0 NC ZOL Q19 Q20 Q21 Q22 Q23 Q24 Q25 6 1:1 Register C0 = 0, C1=0 A B C D E F G H J K L M N P R T 1 DCKE D2 D3 DODT D5 D6 PAR_IN CK CK# D8 D9 D10 D11 D12 D13 D14 1 2 PPO NC NC QERR# NC NC RST# DCS# CSR# NC NC NC NC NC NC NC 2 3 VREF GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD VREF 3 4 VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD VDD 4 5 QCKEA Q2A Q3A QODTA Q5A Q6A C1 QCSA# ZOH Q8A Q9A Q10A Q11A Q12A Q13A Q14A 5 6 QCKEB Q2B Q3B QODTB Q5B Q6B C0 QCSB# ZOL Q8B Q9B Q10B Q11B Q12B Q13B Q14B 6 A B C D E F G H J K L M N P R T 1:2 Register A C0 = 0, C1=1 Rev 1.0, November 25, 2006 2200 Laurelwood Road, Santa Clara, CA 95054 1 D1 D2 D3 D4 D5 D6 PAR_IN CK CK# D8 D9 D10 DODT D12 D13 DCKE 1 2 PPO NC NC QERR# NC NC RST# DCS# CSR# NC NC NC NC NC NC NC 2 3 VREF GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD VREF 3 4 VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD VDD 4 5 Q1A Q2A Q3A Q4A Q5A Q6A C1 QCSA# ZOH Q8A Q9A Q10A QODTA Q12A Q13A QCKEA 5 6 Q1B Q2B Q3B Q4B Q5B Q6B C0 QCSB# ZOL Q8B Q9B Q10B QODTB Q12B Q13B QCKEB 6 1:2 Register B C0 = 1, C1=1 Page 1 of 24 Tel:(408) 855-0555 Fax:(408) 855-0550 www.SpectraLinear.com CY2SSTU32866 The CY2SSTV32866 accepts a parity bit from the memory controller on its parity bit (PAR_IN) input, compares it with the data received on the DIMM-independent D-inputs and indicates whether a parity error has occurred on its open-drain QERR# pin (active LOW). The convention is even parity, i.e., valid parity is defined as an even number of ones across the DIMM-independent data inputs combined with the parity input bit. When used as a single device, the C0 and C1 inputs are tied LOW. In this configuration, parity is checked on the PAR_IN input which arrives one cycle after the input data to which it applies. The partial-parity-out (PPO) and QERR# signals are produced three cycles after the corresponding data inputs. When used in pairs, the C0 input of the first register is tied LOW and the C0 input of the second register is tied HIGH. The C1 input of both registers are tied HIGH. Parity, which arrives one cycle after the data input to which it applies, is checked on the PAR_IN input of the first device. The PPO and QERR# signals are produced on the second device three clock cycles after the corresponding data inputs. The PPO output of the first register is cascaded to the PAR_IN of the second register. The QERR# output of the first register is left floating and the valid error information is latched on the QERR# output of the second register. If an error occurs and the QERR# output is driven LOW, it stays latched LOW for two clock cycles or until RESET# is driven LOW. The DIMM-dependent signals (DCKE, DCS#, DODT, and CSR#) are not included in the parity check computation. Parity is calculated using Table 1. Table 1. Parity Function Table Inputs Outputs RESET# DCS# CSR# CK CK# Sum of inputs = H (D1-25) H L X pn pn Even H L X pn pn Odd H L X pn pn H L X pn pn H H L pn H H L pn H H L H H L PAR_IN PPO QERR# L L H L H L Even H H L Odd H L H pn Even L L H pn Odd L H L pn pn Even H H L pn pn Odd H L H H H H pn pn X X PPO0 QERR#0 H X X L or H L or H X X PPO0 QERR#0 L X or Floating X or Floating X or Floating X or Floating X or Floating X or Floating L H Pin Definition Pin Number (C0 = 0, C1 = 0) Pin Name Pin Number (C0 = 0, C1 = 1) Pin Number (C0 = 1, C1 = 1) Description GND B3, B4, D3, D4, F3, F4, B3, B4, D3, D4, F3, B3, B4, D3, D4, F3, Ground H3, H4, K3, K4, M3, M4, F4, H3, H4, K3, K4, F4, H3, H4, K3, K4, P3, P4 M3, M4, P3, P4 M3, M4, P3, P4 VDD A4, C3, C4, E3, E4, G3, A4, C3, C4, E3, G4, J3, J4, L3, L4, N3, E4, G3, G4, J3, J4, L3, L4, N3, N4, R3, N4, R3, R4, T4 R4, T4 A4, C3, C4, E3, Power Supply Voltage E4, G3, G4, J3, J4, L3, L4, N3, N4, R3, R4, T4 VREF A3, T3 A3, T3 A3, T3 Input Reference Voltage ZOH J5 J5 J5 Reserved ZOL J6 J6 J6 Reserved CK H1 H1 H1 Positive Master Clock CK# J1 J1 J1 Negative Master Clock C0 G6 G6 G6 Configuration control input C1 G5 G5 G5 Configuration control input Rev 1.0, November 25, 2006 Page 2 of 24 CY2SSTU32866 Pin Definition (continued) Pin Number (C0 = 0, C1 = 0) Pin Name Pin Number (C0 = 0, C1 = 1) Pin Number (C0 = 1, C1 = 1) Description RESET# G2 G2 G2 Asynchronous reset – resets registers and disables Vref data and clock differential input receivers CSR# J2 J2 J2 Chip Select – Disables D1-D24 when both CSR# and DCS# are HIGH (VDD) DCS# H2 H2 H2 Chip Select – Disables D1-D24 when both CSR# and DCS# are HIGH (VDD) A1 Data input – clocked in on the crossing points of CK and CK# B1, C1 Data input – clocked in on the crossing points of CK and CK# D1 Data input – clocked in on the crossing points of CK and CK# D1 D2-3 B1, C1 B1, C1 D4 D5, 6, 8, 9, 10 E1, F1, K1, L1, M1 E1, F1, K1, L1, M1 E1, F1, K1, L1, M1 Data input – clocked in on the crossing points of CK and CK# D11 N1 N1 D12, 13 P1, R1 P1, R1 D14 T1 T1 D15-25 B2, C2, E2, F2, K2, L2, M2, N2, P2, R2, T2 DODT D1 D1 N1 The outputs of this register bit will not be suspended by the DCS# and CSR# Control DCKE A1 A1 T1 The outputs of this register bit will not be suspended by the DCS# and CSR# Control A5 Data Outputs that are suspended by the DCS# and CSR# control B5, C5 Data Outputs that are suspended by the DCS# and CSR# control D5 Data Outputs that are suspended by the DCS# and CSR# control B5, C5 P1, R1 Data input – clocked in on the crossing points of CK and CK# Data input – clocked in on the crossing points of CK and CK# Data input – clocked in on the crossing points of CK and CK# Q1A Q2A-3A Data input – clocked in on the crossing points of CK and CK# B5, C5 Q4A Q5A, 6A, 8A, E5, F5, K5, L5, M5 9A, 10A E5, F5, K5, L5, M5 E5, F5, K5, L5, M5 Data Outputs that are suspended by the DCS# and CSR# control Q11A N5 N5 Q12A, Q13A P5, R5 P5, R5 Q14A T5 T5 Q1B Q2B-3B B6, C6 Q4B P5, R5 Data Outputs that are suspended by the DCS# and CSR# control A6 Data Outputs that are suspended by the DCS# and CSR# control B6, C6 Data Outputs that are suspended by the DCS# and CSR# control D6 Data Outputs that are suspended by the DCS# and CSR# control Q5B, 6B, 8B, 9B, 10B, E6, F6, K6, L6, M6 E6, F6, K6, L6, M6 Data Outputs that are suspended by the DCS# and CSR# control Q11B N6 Rev 1.0, November 25, 2006 Data Outputs that are suspended by the DCS# and CSR# control Page 3 of 24 CY2SSTU32866 Pin Definition (continued) Pin Number (C0 = 0, C1 = 0) Pin Name Pin Number (C0 = 0, C1 = 1) Q12B, 13B P6, R6 Q14B T6 Q15-25 B6, C6, E6, F6, K6, L6, M6, N6, P6, R6, T6 QCSA# H5 QCSB# QODTA D5 QODTB QCKEA A5 QCKEB Pin Number (C0 = 1, C1 = 1) P6, R6 Description Data Outputs that are suspended by the DCS# and CSR# control Data Outputs that are suspended by the DCS# and CSR# control Data Outputs that are suspended by the DCS# and CSR# control H5 H5 Data outputs that will not be suspended by the DCS# and CSR# control H6 H6 Data outputs that will not be suspended by the DCS# and CSR# control D5 N5 Data outputs that will not be suspended by the DCS# and CSR# control D6 N6 Data outputs that will not be suspended by the DCS# and CSR# control A5 T5 Data outputs that will not be suspended by the DCS# and CSR# control A6 T6 Data outputs that will not be suspended by the DCS# and CSR# control PPO A2 A2 A2 Partial parity out – indicates odd parity of inputs D1-D25 QERR# D2 D2 D2 Output error bit – generated one clock cycle after the corresponding data output PAR_IN G1 G1 G1 Parity input – arrives one clock cycle after the corresponding data input NC A6, D6, H6 B2, C2, E2, F2, K2, B2, C2, E2, F2, K2, No Connect Pins L2, M2, N2, P2, L2, M2, N2, P2, R2, T2 R2, T2 Table 2. Flip Flop Function Table RESET# H H H H H H H H H H H H L Inputs DCS# CSR# CK L L pn L L pn L L L or H L H pn L H pn L H L or H H L pn H L pn H L L or H H H pn H H pn H H L or H X or Floating X or Floating X or Floating Rev 1.0, November 25, 2006 CK# pn pn L or H pn pn L or H pn pn L or H pn pn L or H X or Floating Dn, DODT, DCKE L H X L H X L H X L H X X or Floating Qn L H Q0 L H Q0 L H Q0 Q0 Q0 Q0 L Outputs QCS# QODT, QCKE L L L H Q0 Q0 L L L H Q0 Q0 H L H H Q0 Q0 H L H H Q0 Q0 L L Page 4 of 24 CY2SSTU32866 RESET CLK CLK G2 H1 J1 LPS0 (internal node) D2−D3, 22 D5−D6, D8-D25 A3, T3 VREF D D2−D3, D5−D6, D8−D25 CE CLK Q 22 22 R 22 Q2−Q3, Q5−Q6, Q8−Q25 D2−D3, D5−D6, D8−D25 Parity Generator C1 G5 1 0 D Q PPO 1 PAR_IN G1 Q D CLK R A2 CLK R 0 Q D CLK R CE D2 QERR C0 G6 CLK 2−Bit Counter R LPS1 (internal node) 0 D Q CLK 1 R Figure 1. Parity logic Diagram for 1:1 register configuration (positive logic) C0=0, C1=0 Rev 1.0, November 25, 2006 Page 5 of 24 CY2SSTU32866 RESET CLK CLK G2 H1 J1 LPS0 (internal node) D2−D3, 11 D5−D6, D8-D14 A3, T3 VREF D2−D3, D5−D6, D8−D14 CE D CLK Q 11 R 11 Q2A−Q3A, Q5A−Q6A, Q8A−Q14A 11 11 Q2B−Q3B, Q5B−Q6B, Q8B−Q14B D2−D3, D5−D6, D8−D14 Parity Generator C1 G5 1 0 D Q PPO 1 PAR_IN G1 Q D CLK R A2 CLK R 0 Q D CLK R CE D2 QERR C0 G6 CLK 2−Bit Counter R LPS1 (internal node) 0 D Q CLK 1 R Figure 2. Parity logic Diagram for 1:2 register-A configuration (positive logic) C0=0, C1=1 Rev 1.0, November 25, 2006 Page 6 of 24 CY2SSTU32866 RESET CLK CLK G2 H1 J1 LPS0 (internal node) D1−D6, D8-D13 VREF 11 A3, T3 11 D1−D6, D8−D13 CE D Q1A−Q6A, Q8A−Q13A CLK Q 11 R 11 11 D1−D6, D8−D13 Q1B−Q6B, Q8B−Q13B Parity Generator C1 G5 1 0 D Q PPO 1 PAR_IN G1 Q D CLK R A2 D CLK R 0 Q CLK R CE D2 QERR C0 G6 CLK 2−Bit Counter R LPS1 (internal node) 0 D Q CLK 1 R Figure 3. Parity logic Diagram for 1:2 register-B configuration (positive logic) C0=1, C1=1 Rev 1.0, November 25, 2006 Page 7 of 24 CY2SSTU32866 (RESET switches from L to H) RESET DCS CSR CLK CLK ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ tact D1−D25† n n+1 tsu n+3 n+2 n+4 th tpdm, tpdmss CLK to Q Q1−Q25 PAR_IN† ÎÎÎÎÎÎ ÎÎÎÎÎÎ tsu th tpd CLK to PPO PPO tPHL CLK to QERR QERR‡ tPHL, tPLH CLK to QERR Data to QERR Latency ÎÎÎÎÎÎ ÎÎÎÎÎÎ H, L, or X H or L Figure 4. CY2SSTU32866 used as single device C0=0, C1=0, RST# Switchs L to H Rev 1.0, November 25, 2006 Page 8 of 24 CY2SSTU32866 RESET ÌÌÌ ÌÌÌ ÌÌÌ ÌÌÌ ÌÌÌ ÌÌÌ ÌÌÌÌ ÌÌÌÌ ÌÌÌÌ ÌÌÌÌ ÌÌÌÌ ÌÌÌÌ ÌÌÌÌÌ ÌÌÌÌÌ ÌÌÌÌÌ ÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇ DCS CSR n n+1 n+2 n+3 n+4 CLK CLK tsu th D1−D25 tpdm, tpdmss CLK to Q Q1−Q25 tsu th PAR_IN ÇÇÇÇÇÇÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇÇÇÇÇÇÇ tpd CLK to PPO PPO Data to PPO Latency tPHL or tPLH CLK to QERR QERR† Data to QERR Latency ÉÉÉÉ ÉÉÉÉ Unknown input event ÇÇÇÇ ÇÇÇÇ Output signal is dependent on the prior unknown input event H or L Figure 5. CY2SSTU32866 used as single device, C0=0, C1=0, RST# being held high Rev 1.0, November 25, 2006 Page 9 of 24 CY2SSTU32866 RESET tinact DCS† CSR† ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ CLK† CLK† D1−D25† tRPHL RESET to Q ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ Q1−Q25 PAR_IN† tRPHL RESET to PPO ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ PPO QERR ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ tRPLH RESET to QERR H, L, or X H or L Figure 6. CY2SSTU32866 used as single device, C0=0, C1=0, RST# switchs from H to L Rev 1.0, November 25, 2006 Page 10 of 24 CY2SSTU32866 C0 = 0, C1 = 1 (RESET switches from L to H) RESET DCS CSR CLK CLK ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ tact D1−D14† n n+1 tsu n+3 n+2 n+4 th tpdm, tpdmss CLK to Q Q1−Q14 PAR_IN† ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ tsu th tpd CLK to PPO PPO tPHL CLK to QERR QERR‡ (not used) ÎÎÎÎÎ ÎÎÎÎÎ tPHL, tPLH CLK to QERR Data to QERR Latency H, L, or X H or L Figure 7. CY2SSTU32866 used as pair, C0=0, C1=1, RST# switches from L to H Rev 1.0, November 25, 2006 Page 11 of 24 CY2SSTU32866 RESET ÇÇÇ ÇÇÇ ÇÇÇ ÇÇÇ ÇÇÇ ÇÇÇÇ ÇÇÇÇ ÇÇÇÇ ÇÇÇÇ ÇÇÇÇ ÇÇÇÇ ÇÇÇÇÇ ÇÇÇÇÇ ÇÇÇÇÇ ÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉ ÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇ DCS CSR n n+1 n+2 n+3 n+4 CLK CLK tsu th D1−D14 tpdm, tpdmss CLK to Q Q1−Q14 tsu th PAR_IN ÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉ tpd CLK to PPO PPO Data to PPO Latency tPHL or tPLH CLK to QERR QERR† (not used) Data to QERR Latency ÇÇÇÇ ÇÇÇÇ Unknown input event ÉÉÉÉ ÉÉÉÉ Output signal is dependent on the prior unknown input event H or L Figure 8. CY2SSTU32866 used as pair, C0=0, C1=1, RST# being held high Rev 1.0, November 25, 2006 Page 12 of 24 CY2SSTU32866 RESET tinact DCS† CSR† ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ CLK† CLK† D1−D14† tRPHL RESET to Q ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ Q1−Q14 PAR_IN† tRPHL RESET to PPO ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ PPO QERR (not used) ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ tRPLH RESET to QERR H, L, or X H or L Figure 9. CY2SSTU32866 used as pair, C0=0, C1=1, RST# switches from H to L Rev 1.0, November 25, 2006 Page 13 of 24 CY2SSTU32866 RESET ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ DCS CSR n n+1 n+3 n+2 n+4 CLK CLK tsu tact th D1−D14† tpdm, tpdmss CLK to Q Q1−Q14 ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ tsu th PAR_IN†‡ tpd CLK to PPO PPO (not used) tPHL CLK to QERR tPHL, tPLH CLK to QERR QERR§ Data to QERR Latency ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ H, L, or X H or L Figure 10. CY2SSTU32866 used as pair, C0=1, C1=1, RST# switches from L to H Rev 1.0, November 25, 2006 Page 14 of 24 CY2SSTU32866 RESET ÇÇÇ ÇÇÇ ÇÇÇ ÇÇÇ ÇÇÇ ÇÇÇÇ ÇÇÇÇ ÇÇÇÇ ÇÇÇÇ ÇÇÇÇ ÇÇÇÇ ÇÇÇÇÇ ÇÇÇÇÇ ÇÇÇÇÇ ÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉ ÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇ DCS CSR n n+1 n+2 n+3 n+4 CLK CLK tsu th D1−D14 tpdm, tpdmss CLK to Q Q1−Q14 tsu th PAR_IN ÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉ tpd CLK to PPO PPO Data to PPO Latency tPHL or tPLH CLK to QERR QERR† (not used) Data to QERR Latency ÇÇÇÇ ÇÇÇÇ Unknown input event ÉÉÉÉ ÉÉÉÉ Output signal is dependent on the prior unknown input event H or L Figure 11. CY2SSTU32866 used as pair, C0=1, C1=1, RST# being held high Rev 1.0, November 25, 2006 Page 15 of 24 CY2SSTU32866 C0 = 1, C1 = 1 (RESET switches from H to L) RESET tinact DCS† CSR† ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ CLK† CLK† D1−D14† tRPHL RESET to Q ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ Q1−Q14 PAR_IN† tRPHL RESET to PPO ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ PPO (not used) QERR ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ H, L, or X tRPLH RESET to QERR H or L Figure 12. CY2SSTU32866 used as pair, C0=1, C1=1, RST# switches from H to L Rev 1.0, November 25, 2006 Page 16 of 24 CY2SSTU32866 Absolute Maximum Conditions [1] Parameter Description TS Storage Temperature VCC Supply Voltage Range VIN Input Voltage Range[2, 3] Condition Range[2, 3] Min. Max. Unit –65 150 C –0.5 2.5 V –0.5 VDD + 0.5 V VOUT Output Voltage –0.5 VDD + 0.5 V IIK Input Clamp Current VO < 0 or VO > VDD –50 50 mA IOK Output Clamp Current VO < 0 or VO > VDD –50 50 mA IO Continuous Output Current VO = 0 to VDD –50 50 mA ICCC Continuous Current through VDD/GND –100 100 mA Min. Max. Unit 0 70 C 1.7 1.9 V DC Electrical Specifications Parameter Description TA (Com.) Ambient Operating Temp VDD Operating Voltage Conditions VREF Voltage Reference 0.49*VDD 0.51*VDD V VTT Terminating Voltage VREF–40mV VREF+40mV V VI Input Voltage 0 VDD V II Input Current VI = VDD or GND –5 5 PA AC Input Low Voltage Data, CSR#, and PAR_IN inputs VIL – VREF – 250mV V – VREF – 125mV V AC Input High Voltage VREF + 250mV – V DC Input High Voltage VREF + 125mV – V 0.35 X VDD V DC Input Low Voltage VIH VIL Input Low Voltage VIH Input High Voltage VICR Input Low Voltage VID Input Differential Voltage VOL Output Low Voltage VOH Output High Voltage RESET#, Cn 0.65 X VDD CK, CK# V 0.675 1.125 V 600 – mV IOL = 100 PA, VCC = 1.7V to 1.9V – 0.2 V IOL = 6 mA, VCC = 1.7V – 0.5 V IOH = –100 PA, VCC = 1.7V to 1.9V IOH = –6 mA, VCC = 1.7V VDD – 0.2 – V 1.2 – V IOH Output High Current – –8 mA IOL Output Low Current – 8 mA IDD Static Standby Power Supply Current RESET# = GND, IO = 0, VDD = 1.9V 100 PA Static Operating Power Supply Current RESET# = VDD, VI = VIH(AC) or VIL(AC), IO = 0, VDD = 1.9V 40 mA Notes: 1. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “Recommended Operating Conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 3. This value is limited to 2.5V (max.) Rev 1.0, November 25, 2006 Page 17 of 24 CY2SSTU32866 DC Electrical Specifications (continued) Parameter IDDD Description Conditions Max. Unit 28 (typical) PA/MHz Dynamic Operating per each Data Input RESET# = VDD, VI = VIH(AC) or VIL(AC), CK, CK# switching 50% duty cycle, VDD = 1.8V, 1 IO switching 1:1 configuration 18 (typical) PA/MHz RESET# = VDD, VI = VIH(AC) or VIL(AC), CK, CK# switching 50% duty cycle, VDD = 1.8V, 1 IO switching 1:2 configuration 36 (typical) PA/MHz Low Power Active Mode, CLK only RESET# = VDD, VI = VIH(AC) or VIL(AC), CK, CK# switching 50% duty cycle, VDD = 1.8V, CS Enabled 27 (typical) PA/MHz Low Power Active Mode per each Data Input RESET# = VDD, VI = VIH(AC) or VIL(AC), CK, CK# switching 50% duty cycle, VDD = 1.8V, 1 IO switching 1:1 configuration, CS Enabled 2 (typical) PA/MHz RESET# = VDD, VI = VIH(AC) or VIL(AC), CK, CK# switching 50% duty cycle, VDD = 1.8V, 1 IO switching 1:2 configuration; CS Enabled 2 (typical) PA/MHz Ci (Data and CSR#) CIN Min. RESET# = VDD, VI = VIH(AC) or VIL(AC), CK, Power Supply Current Dynamic Operating Clock CK# switching 50% duty cycle, Only VDD = 1.8V VI = VREF ± 250mV 2.5 Ci (CK and CK#) VIX = 0.9V, VID = 600 mV Ci (RESET#) VI = VDD or GND 3.5 2 3 pF pF 2.5 pF AC Timing Specifications Parameter Description FCLK Clock Frequency TW Pulse Duration TACT[4] TINACT[5] TSU Set-up Time Conditions Min. Max. Unit – 500 MHz 1 – ns Differential Input Active time – 10 ns Differential Input Inactive time – 15 ns DSR# before crossing CK,CK#, CSR = H 0.7 – ns CSR# before crossing CK,CK#, DCS = H 0.7 – ns DCS# before crossing CK,CK#, CSR = L 0.5 – ns DODT, DCKE and data before crossing CK,CK#, CK going HIGH 0.5 – ns PAR_IN after crossing CK,CK# 0.5 DCS#, DODT, DCKE and data after crossing CK, CK# 0.5 PAR_IN after crossing CK, CK# 0.5 CK, CK# H or L ns TH Hold Time – – ns TPDM Propagation Delay single bit switching From CK, CK# crossing to Q 1.86 ns TPDMSS Propagation Delay simultaneous switching From CK, CK# to Q simultaneous switching 1.87 ns Propagation Delay from Low to High From CK, CK# crossing to PPO 2.15 (typical) TPD Notes: 4. Data and VREF inputs must be low a minimum time of TACT max, after RESET# is taken HIGH. 5. Data, VREF and clock inputs must be held at valid levels (not floating) a minimum time of TINACT max after RESET# is taken LOW. Rev 1.0, November 25, 2006 ns ns Page 18 of 24 CY2SSTU32866 AC Timing Specifications (continued) Parameter Description Conditions Min. Max. Unit 1.2 3 ns 1 2.4 ns TPLH Propagation Delay from Low to High TPHL Propagation Delay from Low to High From CK, CK# crossing to QERR# TrPLH Propagation Delay from Low to High RESET# LOW to QERR# HIGH TrPHL Propagation Delay from High to Low RESET# LOW to Q, PPO LOW 3 ns SLR Slew Rate Rising dv/dt_r (20 to 80%) 1 4 V/ns Slew Rate Falling dv/dt_f (20 to 80%) 1 4 V/ns – 1 V/ns dv/dt ' 3 (typical) Delta between Rising/Falling Rates ns VDD DUT RL = 1000: CK CK CK Inputs OUT TL = 350ps, 50: Test Point Test Point RL = 1000: CL = 30pF RL = 100: Test Point CL includes probe and jig capacitance Figure 13. Test Load for Timing Measurements #1 LVCMOS VDD RESET VDD/2 VDD/2 0V tact tinact IDD 90% 10% IDD tested with clock and data inputs held at VDD or GND, and IO = 0mA Figure 14. Active and Inactive Times tw VIH Input VICR VICR VID VIL VID = 600mV VIH = VREF + 250mV (AC Voltage levels) for differential inputs. VIH = VDD for LVCMOS inputs. VIL = VREF - 250mV ( AC voltage levels) for differential inputs. VIL = VDD for LVCMOS inputs Figure 15. Pulse Duration Rev 1.0, November 25, 2006 Page 19 of 24 CY2SSTU32866 CK VICR VID CK tsu th VIH VREF Input VREF VIL VID = 600mV VREF = VDD/2 VIH = VREF + 250mV (AC Voltage levels) for differential inputs. VIH = VDD for LVCMOS inputs. VIL = VREF - 250mV ( AC voltage levels) for differential inputs. VIL = VDD for LVCMOS inputs Figure 16. Set-up and Hold Times CK VICR VICR VI(P-P) CK tPLH tPHL VOH VTT VTT Output VOL tPLH and tPHL are the same as tPD Figure 17. Propagation Delay LVCMOS RESET VIH VDD/2 Input VIL tRPHL Output VOH VTT VOL tPLH and tPHL are the same as tPD VIH = VREF + 250mV (AC Voltage levels) for differential inputs. VIH = VDD for LVCMOS inputs. VIL = VREF - 250mV ( AC voltage levels) for differential inputs. VIL = VDD for LVCMOS inputs Figure 18. Propagation Delay after RESET# VDD DUT R L = 50: O UT Test Point C L = 10pF CL includes probe and jig capacitance Figure 19. Load Circuit - High to Low Slew Measurement Rev 1.0, November 25, 2006 Page 20 of 24 CY2SSTU32866 VOH OUTPUT 80% dv_f 20% VOL dt_f Figure 20. High to Low Slew Rate Measurement DUT Test Point OUT R L = 50: C L = 10pF CL includes probe and jig capacitance Figure 21. Load Circuit, Low to High slew measurement dt_r VOH 80% dv_r 20% OUTPUT VOL Figure 22. Low to High Slew Rate Measurement VDD DUT R L = 1k: OUT T e s t P o in t CL = 10pF CL includes probe and jig capacitance Figure 23. Load Circuit - High to Low Slew Rate Measurement Rev 1.0, November 25, 2006 Page 21 of 24 CY2SSTU32866 Figure 24. Open drain output - Low to High transition with respect to reset inputs Timing Inputs VICR VI(P-P) VICR tPLH VCC Output VCC/2 VOL Figure 25. Open drain output - High to Low transition with respect to clock inputs Timing Inputs VICR VI(P-P) VICR tPLH VOH 0.15V Output 0V Figure 26. Open drain output - High to Low transition with respect to clock inputs DUT Test Point OUT CL = 5pF RL = 1K: CL includes probe and jig capacitance Figure 27. Partial-parity-out Load Circuit Rev 1.0, November 25, 2006 Page 22 of 24 CY2SSTU32866 CK VICR VICR VI(P-P) CK tPLH tPHL VTT VTT Output VOH VOL VTT = VDD/2 tPLH and tPHL are the same as tPD VI(P-P) = 600mV Figure 28. Partial-parity-out ; propagation delay times with respect to clock inputs LVCMOS RESET VIH VDD/2 INPUT VIL tPHL Output VTT VOH VOL VTT = VDD/2 tPLH and tPHL are the same as tPD VIH = VREF + 250mV (AC Voltage levels) for differential inputs. VIH = VDD for LVCMOS inputs. VIL = VREF - 250mV ( AC voltage levels) for differential inputs. VIL = VDD for LVCMOS inputs Figure 29. Partial-parity-out ; propagation delay times with respect to clock inputs Rev 1.0, November 25, 2006 Page 23 of 24 CY2SSTU32866 Ordering Information Part Number Package Type Product Flow Lead Free CY2SSTU32866BFXC 96-pin FBGA Commercial, 0q to 70qC CY2SSTU32866BFXCT 96-pin FBGA – Tape and Reel Commercial, 0q to 70qC Package Drawing and Dimensions 96-Ball FBGA (5.5 x 13.5 x 1.2 MM) BF96A Ø0.05 M C Ø0.25 M C A B Ø0.50±0.05(96X) BOTTOM VIEW TOP VIEW A1 CORNER A1 CORNER 1 2 3 4 5 6 6 5 4 3 1 A A B B C C D 6.00 D E E F F G G H J K H 12.00 13.50±0.10 13.50±0.10 2 J K L DIMENSIONS IN MILLIMETERS REFERENCE JEDEC MO-205 PKG. WEIGHT: 0.23 gms L PART # M N BF96A STANDARD PKG. P BP96A LEAD FREE PKG. 0.80 M N P R R T T A 2.00 A 0.80 5.50±0.10 B 0.15 C 0.40±0.05 0.25 C 0.53±0.05 4.00 B 5.50±0.10 0.15(4X) 1.20 MAX 0.26 SEATING PLANE C While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for the use of any circuitry or for the infringement of any patents or other rights of third parties which would result from each use. This product is intended for use in normal commercial applications and is not warranted nor is it intended for use in life support, critical medical instruments, or any other application requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursuant to additional processing by Spectra Linear Inc., and expressed written agreement by Spectra Linear Inc. Spectra Linear Inc. reserves the right to change any circuitry or specification without notice. Rev 1.0, November 25, 2006 Page 24 of 24