Cypress CY62146VLL-70ZI 4m (256k x 16) static ram Datasheet

CY62146V MoBL®
4M (256K x 16) Static RAM
Features
•
•
•
•
•
•
•
Wide voltage range: 2.7V–3.6V
Ultra-low active, standby power
Easy memory expansion with CE and OE features
TTL-compatible inputs and outputs
Automatic power-down when deselected
CMOS for optimum speed/power
Package available in a standard 44-Pin TSOP Type II
(forward pinout) package
Functional Description[1]
The CY62146V is a high-performance CMOS static RAM
organized as 256K words by 16 bits. These devices feature
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life® (MoBL®) in
portable applications such as cellular telephones. The device
also has an automatic power-down feature that significantly
reduces power consumption by 99% when addresses are not
toggling. The device can also be put into standby mode when
deselected (CE HIGH). The input/output pins (I/O0 through
I/O15) are placed in a high-impedance state when: deselected
(CE HIGH), outputs are disabled (OE HIGH), BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is
written into the location specified on the address pins (A0
through A16). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O8 through I/O15) is written into the location
specified on the address pins (A0 through A17).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O8 to I/O15. See
the truth table at the back of this data sheet for a complete
description of read and write modes.
Logic Block Diagram
256K × 16
RAM Array
2048 × 2048
SENSE AMPS
ROW DECODER
DATA IN DRIVERS
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
I/O0 – I/O7
I/O8 – I/O15
A13
BHE
WE
CE
OE
BLE
A14
A15
A16
A17
A11
A12
COLUMN DECODER
Note:
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05159 Rev. *A
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised August 27, 2002
CY62146V MoBL®
Pin Configurations
TSOP II (Forward)
Top View
A4
A3
A2
A1
A0
CE
I/O0
I/O1
I/O2
I/O3
VCC
VSS
I/O4
I/O5
I/O6
I/O7
WE
A16
A15
A14
A13
A12
1
44
2
3
43
42
4
41
40
39
38
5
6
7
8
9
10
11
12
37
36
35
34
33
32
31
30
29
28
27
13
14
15
16
17
18
19
20
21
22
26
25
24
23
Maximum Ratings
A5
A6
A7
OE
BHE
BLE
I/O15
I/O14
I/O13
I/O12
VSS
VCC
I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
A17
Output Current into Outputs (LOW)............................. 20 mA
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature .................................–65°C to +150°C
Static Discharge Voltage........................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-up Current..................................................... >200 mA
Operating Range
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Supply Voltage to Ground Potential ............... –0.5V to +4.6V
Range
Ambient
Temperature
VCC
DC Voltage Applied to Outputs
in High-Z State[2] ....................................–0.5V to VCC + 0.5V
Industrial
–40°C to +85°C
2.7V to 3.6V
DC Input Voltage[2] ................................–0.5V to VCC + 0.5V
Product Portfolio
Power Dissipation
VCC Range (V)
Product
CY62146VLL
VCC(min.) VCC(typ.)
2.7
3.0
[3]
VCC(max.)
Speed
(ns)
3.6
70
Operating ICC, (mA)
Typ.[3]
7
Standby ISB2, (µA)
Maximum
Typ.[3]
Maximum
15
2
20
Notes:
2. VIL(min.) = –2.0V for pulse durations less than 20 ns.
3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25°C.
Document #: 38-05159 Rev. *A
Page 2 of 10
CY62146V MoBL®
Electrical Characteristics Over the Operating Range
CY62146V-70
Parameter
Description
Test Conditions
Typ.[3]
Min.
Max.
Unit
0.4
V
VOH
Output HIGH Voltage
IOH = –1.0 mA
VCC = 2.7V
VOL
Output LOW Voltage
IOL = 2.1 mA
VCC = 2.7V
2.4
V
VIH
Input HIGH Voltage
VCC = 3.6V
2.2
VCC + 0.5V
V
VIL
Input LOW Voltage
VCC = 2.7V
–0.5
0.8
V
IIX
Input Load Current
GND < VI < VCC
–1
+1
+1
µA
IOZ
Output Leakage Current
GND < VO < VCC, Output Disabled
–1
+1
+1
µA
ICC
VCC Operating Supply
Current
IOUT = 0 mA,
f = fMAX = 1/tRC,
CMOS Levels
7
15
mA
IOUT = 0 mA, f = 1 MHz,
CMOS Levels
1
2
mA
2
20
µA
VCC = 3.6V
ISB1
Automatic CE
Power-down Current—
CMOS Inputs
CE > VCC – 0.3V,
VIN > VCC – 0.3V or
VIN < 0.3V, f = fMAX
ISB2
Automatic CE
Power-down Current—
CMOS Inputs
CE > VCC – 0.3V
VIN > VCC – 0.3V
or VIN < 0.3V, f = 0
VCC = 3.6V
Capacitance[4]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VCC= VCC(typ.)
Max.
Unit
6
pF
8
pF
Thermal Resistance
Parameter
Description
ΘJA
Thermal Resistance
(Junction to Ambient)[4]
ΘJC
Thermal Resistance
(Junction to Case)[4]
Test Conditions
BGA
TSOPII
Unit
Still Air, soldered on a 4.25 x 1.125 inch, 4-layer
printed circuit board
55
60
°C/W
16
22
°C/W
AC Test Loads and Waveforms
R1
R1
VCC
ALL INPUT PULSES
VCC
OUTPUT
VCC Typ
OUTPUT
5 pF
30 pF
INCLUDING
JIG AND
SCOPE
R2
(a)
INCLUDING
JIG AND
SCOPE
R2
10%
GND
Rise Time: 1 V/ns
(b)
Equivalent to:
90%
10%
90%
Fall Time: 1 V/ns
(c)
THÉVENIN EQUIVALENT
RTH
OUTPUT
Note:
4. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05159 Rev. *A
VTH
Page 3 of 10
CY62146V MoBL®
Parameter
3.0V
Unit
R1
1105
Ohms
R2
1550
Ohms
RTH
645
Ohms
VTH
1.75
V
Data Retention Characteristics (Over the Operating Range)
Parameter
Description
Conditions
Min. Typ.[3] Max.
1.0
Unit
VDR
VCC for Data Retention)
ICCDR
Data Retention Current
tCDR[4]
Chip Deselect to Data
Retention Time
0
ns
tR[5]
Operation Recovery Time
70
ns
VCC= 1.0V, CE > VCC – 0.3V, VIN > VCC – 0.3V or VIN <
0.3V; No input may exceed VCC + 0.3V
1
3.6
V
10
µA
Data Retention Waveform
DATA RETENTION MODE
VCC(min.)
VCC
VDR > 1.0 V
VCC(min.)
tR
tCDR
CE
Switching Characteristics Over the Operating Range
[6]
70 ns
Parameter
Description
Min.
Max.
Unit
Read Cycle
tRC
Read Cycle Time
tAA
Address to Data Valid
70
tOHA
Data Hold from Address Change
tACE
CE LOW to Data Valid
tDOE
OE LOW to Data Valid
tLZOE
OE LOW to Low-Z[7, 8]
10
OE HIGH to High-Z
tLZCE
CE LOW to Low-Z[7]
ns
ns
25
ns
ns
20
10
High-Z[7, 8]
ns
70
5
[8]
tHZOE
ns
70
ns
ns
tHZCE
CE HIGH to
tPU
CE LOW to Power-up
tPD
CE HIGH to Power-down
70
ns
tDBE
BHE / BLE LOW to Data Valid
35
ns
tLZBE
BHE / BLE LOW to Low-Z
tHZBE
BHE / BLE HIGH to High-Z
Write
20
0
ns
ns
5
ns
20
ns
Cycle[9, 10]
tWC
Write Cycle Time
70
ns
Notes:
5. Full Device AC operation requires linear VCC ramp from VDR to VCC(min.) > 10 µs or stable VCC(min.) >10 µs.
6. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to VCC(typ.), and output loading of the specified
IOL/IOH and 30 pF load capacitance.
7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
8. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
9. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
10. The minimum write cycle time for Write Cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
Document #: 38-05159 Rev. *A
Page 4 of 10
CY62146V MoBL®
Switching Characteristics Over the Operating Range (continued)[6]
70 ns
Parameter
Description
Min.
Max.
Unit
tSCE
CE LOW to Write End
60
ns
tAW
Address Set-up to Write End
60
ns
tHA
Address Hold from Write End
0
ns
tSA
Address Set-up to Write Start
0
ns
tPWE
WE Pulse Width
40
ns
tBW
BHE / BLE Pulse Width
60
ns
tSD
Data Set-up to Write End
30
ns
tHD
Data Hold from Write End
0
ns
[7, 8]
tHZWE
WE LOW to High-Z
tLZWE
WE HIGH to Low-Z[7]
25
10
ns
ns
Switching Waveforms
Read Cycle No. 1 [11, 12]
tRC
ADDRESS
tOHA
DATA OUT
tAA
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 [12, 13]
tRC
CE
tPD
tHZCE
tACE
OE
tHZOE
tDOE
BHE/BLE
tLZOE
tHZBE
tDBE
tLZBE
DATA OUT
HIGH IMPEDANCE
HIGH
IMPEDANCE
DATA VALID
tLZCE
VCC
SUPPLY
CURRENT
tPU
ICC
50%
50%
ISB
Notes:
11. Device is continuously selected. OE, CE = VIL.
12. WE is HIGH for read cycle.
13. Address valid prior to or coincident with CE transition LOW.
Document #: 38-05159 Rev. *A
Page 5 of 10
CY62146V MoBL®
Switching Waveforms (continued)
Write Cycle No. 1 (WE Controlled)
[9, 14, 15]
tWC
ADDRESS
CE
tAW
tHA
tSA
WE
tPWE
tBW
BHE/BLE
OE
tSD
DATA I/O
tHD
DATAIN VALID
NOTE 16
tHZOE
Write Cycle No. 2 (CE Controlled)
[9, 14, 15]
tWC
ADDRESS
tSCE
CE
tSA
tAW
BHE/BLE
WE
tHA
tBW
tPWE
tSD
DATA I/O
tHD
DATAIN VALID
Notes:
14. Data I/O is high-impedance if OE = VIH.
15. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
16. During this period, the I/Os are in output state and input signals should not be applied.
Document #: 38-05159 Rev. *A
Page 6 of 10
CY62146V MoBL®
Switching Waveforms (continued)
Write Cycle No. 3 (WE Controlled, OE LOW)
[10, 15]
tWC
ADDRESS
CE
tAW
tHA
tBW
BHE/BLE
WE
tSA
tSD
DATA I/O
tHD
DATAIN VALID
NOTE 16
tLZWE
tHZWE
[16]
Write Cycle No. 4 (BHE/BLE Controlled, OE LOW)
tWC
ADDRESS
CE
tAW
tHA
tBW
BHE/BLE
tSA
WE
tSD
DATA I/O
DATAIN VALID
NOTE 16
tHZWE
Document #: 38-05159 Rev. *A
tHD
tLZWE
Page 7 of 10
CY62146V MoBL®
Typical DC and AC Characteristics
Normalized Operating Current
vs. Supply Voltage
1.4
Standby Current vs. Supply Voltage
45
MoBL
40
1.2
MoBL
35
ISB (µA)
1.0
ICC
0.8
0.6
30
20
15
0.4
10
0.2
5
0.0
2.7
3.2
SUPPLY VOLTAGE (V)
3.7
2.7
3.7
2.8
SUPPLY VOLTAGE (V)
Access Time vs. Supply Voltage
80
MoBL
70
60
TAA (ns)
50
40
30
20
10
2.7
3.7
2.8
SUPPLY VOLTAGE (V)
Truth Table
CE
WE
OE
BHE
BLE
H
X
X
X
X
High-Z
Deselect/Power-down
Standby (ISB)
L
H
L
L
L
Data Out (I/O0–I/O15)
Read
Active (ICC)
L
H
L
H
L
Data Out (I/O0–I/O7);
I/O8–I/O15 in High-Z
Read
Active (ICC)
L
H
L
L
H
Data Out (I/O8–I/O15);
I/O0–I/O7 in High-Z
Read
Active (ICC)
L
H
L
H
H
High-Z
Output Disabled
Active (ICC)
L
H
H
X
X
High-Z
Output Disabled
Active (ICC)
L
L
X
L
L
Data In (I/O0–I/O15)
Write
Active (ICC)
L
L
X
H
L
Data In (I/O0–I/O7);
I/O8–I/O15 in High-Z
Write
Active (ICC)
L
L
X
L
H
Data In (I/O8–I/O15);
I/O0–I/O7 in High-Z
Write
Active (ICC)
L
L
X
H
H
High-Z
Output Disabled
Active (ICC)
Document #: 38-05159 Rev. *A
Inputs/Outputs
Mode
Power
Page 8 of 10
CY62146V MoBL®
Ordering Information
Speed
(ns)
70
Ordering Code
CY62146VLL-70ZI
Package
Name
Z44
Package Type
44-pin TSOP II
Operating
Range
Industrial
Package Diagram
44-Pin TSOP II Z44
51-85087-A
MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor. All product and company
names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05159 Rev. *A
Page 9 of 10
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY62146V MoBL®
Document Title: CY62146V MoBL® 4M (256K x 16) Static RAM
Document Number: 38-05159
REV.
ECN NO.
Issue Date
Orig. of
Change
**
109963
10/02/01
SZV
Change from Spec number: 38-00647 to 38-05159
*A
116594
09/04/02
GBI
Added footnote 1. Deleted fBGA package; replacement fBGA package is
available in CY62146CV30.
Document #: 38-05159 Rev. *A
Description of Change
Page 10 of 10
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